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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -o - %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_ps float @image_load_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {5 ; GCN-LABEL: name: image_load_f326 ; GCN: bb.1 (%ir-block.0):7 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr18 ; GCN-NEXT: {{ $}}9 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr210 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr311 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr412 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr513 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr614 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr715 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr816 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr917 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)18 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr019 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr120 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)21 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (s32), addrspace 8)22 ; GCN-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)23 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr024 %tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)25 ret float %tex26}27 28define amdgpu_ps <2 x float> @image_load_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {29 ; GCN-LABEL: name: image_load_v2f3230 ; GCN: bb.1 (%ir-block.0):31 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr132 ; GCN-NEXT: {{ $}}33 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr234 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr335 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr436 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr537 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr638 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr739 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr840 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr941 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)42 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr043 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr144 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)45 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<2 x s32>), addrspace 8)46 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)47 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)48 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)49 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr150 %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)51 ret <2 x float> %tex52}53 54define amdgpu_ps <3 x float> @image_load_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {55 ; GCN-LABEL: name: image_load_v3f3256 ; GCN: bb.1 (%ir-block.0):57 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr158 ; GCN-NEXT: {{ $}}59 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr260 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr361 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr462 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr563 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr664 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr765 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr866 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr967 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)68 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr069 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr170 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)71 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<3 x s32>), align 16, addrspace 8)72 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)73 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)74 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)75 ; GCN-NEXT: $vgpr2 = COPY [[UV2]](s32)76 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr277 %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)78 ret <3 x float> %tex79}80 81define amdgpu_ps <4 x float> @image_load_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {82 ; GCN-LABEL: name: image_load_v4f3283 ; GCN: bb.1 (%ir-block.0):84 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr185 ; GCN-NEXT: {{ $}}86 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr287 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr388 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr489 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr590 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr691 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr792 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr893 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr994 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)95 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr096 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr197 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)98 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<4 x s32>), addrspace 8)99 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)100 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)101 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)102 ; GCN-NEXT: $vgpr2 = COPY [[UV2]](s32)103 ; GCN-NEXT: $vgpr3 = COPY [[UV3]](s32)104 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3105 %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)106 ret <4 x float> %tex107}108 109define amdgpu_ps float @image_load_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {110 ; GCN-LABEL: name: image_load_tfe_f32111 ; GCN: bb.1 (%ir-block.0):112 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1113 ; GCN-NEXT: {{ $}}114 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2115 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3116 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4117 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5118 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6119 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7120 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8121 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9122 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)123 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0124 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1125 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF126 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)127 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)128 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)129 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)130 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)131 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0132 %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)133 %tex = extractvalue { float, i32 } %res, 0134 %tfe = extractvalue { float, i32 } %res, 1135 store i32 %tfe, ptr addrspace(1) poison136 ret float %tex137}138 139define amdgpu_ps <2 x float> @image_load_tfe_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {140 ; GCN-LABEL: name: image_load_tfe_v2f32141 ; GCN: bb.1 (%ir-block.0):142 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1143 ; GCN-NEXT: {{ $}}144 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2145 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3146 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4147 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5148 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6149 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7150 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8151 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9152 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)153 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0154 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1155 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF156 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)157 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<2 x s32>), addrspace 8)158 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)159 ; GCN-NEXT: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)160 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)161 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)162 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1163 %res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)164 %tex = extractvalue { <2 x float>, i32 } %res, 0165 %tfe = extractvalue { <2 x float>, i32 } %res, 1166 store i32 %tfe, ptr addrspace(1) poison167 ret <2 x float> %tex168}169 170define amdgpu_ps <3 x float> @image_load_tfe_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {171 ; GCN-LABEL: name: image_load_tfe_v3f32172 ; GCN: bb.1 (%ir-block.0):173 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1174 ; GCN-NEXT: {{ $}}175 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2176 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3177 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4178 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5179 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6180 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7181 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8182 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9183 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)184 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0185 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1186 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF187 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)188 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<3 x s32>), align 16, addrspace 8)189 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)190 ; GCN-NEXT: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)191 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)192 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)193 ; GCN-NEXT: $vgpr2 = COPY [[UV2]](s32)194 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2195 %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)196 %tex = extractvalue { <3 x float>, i32 } %res, 0197 %tfe = extractvalue { <3 x float>, i32 } %res, 1198 store i32 %tfe, ptr addrspace(1) poison199 ret <3 x float> %tex200}201 202define amdgpu_ps <4 x float> @image_load_tfe_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {203 ; GCN-LABEL: name: image_load_tfe_v4f32204 ; GCN: bb.1 (%ir-block.0):205 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1206 ; GCN-NEXT: {{ $}}207 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2208 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3209 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4210 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5211 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6212 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7213 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8214 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9215 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)216 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0217 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1218 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF219 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)220 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<4 x s32>), addrspace 8)221 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)222 ; GCN-NEXT: G_STORE [[UV4]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)223 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)224 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)225 ; GCN-NEXT: $vgpr2 = COPY [[UV2]](s32)226 ; GCN-NEXT: $vgpr3 = COPY [[UV3]](s32)227 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3228 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)229 %tex = extractvalue { <4 x float>, i32 } %res, 0230 %tfe = extractvalue { <4 x float>, i32 } %res, 1231 store i32 %tfe, ptr addrspace(1) poison232 ret <4 x float> %tex233}234 235define amdgpu_ps float @image_load_f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {236 ; GCN-LABEL: name: image_load_f32_dmask_0000237 ; GCN: bb.1 (%ir-block.0):238 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1239 ; GCN-NEXT: {{ $}}240 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0241 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1242 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF243 ; GCN-NEXT: $vgpr0 = COPY [[DEF]](s32)244 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0245 %tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)246 ret float %tex247}248 249define amdgpu_ps <2 x float> @image_load_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {250 ; GCN-LABEL: name: image_load_v2f32_dmask_1000251 ; GCN: bb.1 (%ir-block.0):252 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1253 ; GCN-NEXT: {{ $}}254 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2255 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3256 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4257 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5258 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6259 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7260 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8261 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9262 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)263 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0264 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1265 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)266 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (s32), addrspace 8)267 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF268 ; GCN-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)269 ; GCN-NEXT: $vgpr1 = COPY [[DEF]](s32)270 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1271 %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)272 ret <2 x float> %tex273}274 275define amdgpu_ps <2 x float> @image_load_v2f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {276 ; GCN-LABEL: name: image_load_v2f32_dmask_0000277 ; GCN: bb.1 (%ir-block.0):278 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1279 ; GCN-NEXT: {{ $}}280 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0281 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1282 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF283 ; GCN-NEXT: $vgpr0 = COPY [[DEF]](s32)284 ; GCN-NEXT: $vgpr1 = COPY [[DEF]](s32)285 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1286 %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)287 ret <2 x float> %tex288}289 290define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {291 ; GCN-LABEL: name: image_load_v3f32_dmask_1100292 ; GCN: bb.1 (%ir-block.0):293 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1294 ; GCN-NEXT: {{ $}}295 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2296 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3297 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4298 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5299 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6300 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7301 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8302 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9303 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)304 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0305 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1306 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)307 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<2 x s32>), addrspace 8)308 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)309 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF310 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)311 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)312 ; GCN-NEXT: $vgpr2 = COPY [[DEF]](s32)313 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2314 %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)315 ret <3 x float> %tex316}317 318define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {319 ; GCN-LABEL: name: image_load_v3f32_dmask_1000320 ; GCN: bb.1 (%ir-block.0):321 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1322 ; GCN-NEXT: {{ $}}323 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2324 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3325 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4326 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5327 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6328 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7329 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8330 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9331 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)332 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0333 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1334 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)335 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (s32), addrspace 8)336 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF337 ; GCN-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)338 ; GCN-NEXT: $vgpr1 = COPY [[DEF]](s32)339 ; GCN-NEXT: $vgpr2 = COPY [[DEF]](s32)340 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2341 %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)342 ret <3 x float> %tex343}344 345define amdgpu_ps <3 x float> @image_load_v3f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {346 ; GCN-LABEL: name: image_load_v3f32_dmask_0000347 ; GCN: bb.1 (%ir-block.0):348 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1349 ; GCN-NEXT: {{ $}}350 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0351 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1352 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF353 ; GCN-NEXT: $vgpr0 = COPY [[DEF]](s32)354 ; GCN-NEXT: $vgpr1 = COPY [[DEF]](s32)355 ; GCN-NEXT: $vgpr2 = COPY [[DEF]](s32)356 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2357 %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)358 ret <3 x float> %tex359}360 361define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {362 ; GCN-LABEL: name: image_load_v4f32_dmask_1110363 ; GCN: bb.1 (%ir-block.0):364 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1365 ; GCN-NEXT: {{ $}}366 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2367 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3368 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4369 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5370 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6371 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7372 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8373 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9374 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)375 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0376 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1377 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)378 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<3 x s32>), align 16, addrspace 8)379 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)380 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF381 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)382 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)383 ; GCN-NEXT: $vgpr2 = COPY [[UV2]](s32)384 ; GCN-NEXT: $vgpr3 = COPY [[DEF]](s32)385 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3386 %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)387 ret <4 x float> %tex388}389 390define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {391 ; GCN-LABEL: name: image_load_v4f32_dmask_1100392 ; GCN: bb.1 (%ir-block.0):393 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1394 ; GCN-NEXT: {{ $}}395 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2396 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3397 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4398 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5399 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6400 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7401 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8402 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9403 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)404 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0405 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1406 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)407 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<2 x s32>), addrspace 8)408 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)409 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF410 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)411 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)412 ; GCN-NEXT: $vgpr2 = COPY [[DEF]](s32)413 ; GCN-NEXT: $vgpr3 = COPY [[DEF]](s32)414 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3415 %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)416 ret <4 x float> %tex417}418 419define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {420 ; GCN-LABEL: name: image_load_v4f32_dmask_1000421 ; GCN: bb.1 (%ir-block.0):422 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1423 ; GCN-NEXT: {{ $}}424 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2425 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3426 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4427 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5428 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6429 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7430 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8431 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9432 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)433 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0434 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1435 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)436 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (s32), addrspace 8)437 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF438 ; GCN-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)439 ; GCN-NEXT: $vgpr1 = COPY [[DEF]](s32)440 ; GCN-NEXT: $vgpr2 = COPY [[DEF]](s32)441 ; GCN-NEXT: $vgpr3 = COPY [[DEF]](s32)442 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3443 %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)444 ret <4 x float> %tex445}446 447define amdgpu_ps <4 x float> @image_load_v4f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {448 ; GCN-LABEL: name: image_load_v4f32_dmask_0000449 ; GCN: bb.1 (%ir-block.0):450 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1451 ; GCN-NEXT: {{ $}}452 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0453 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1454 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF455 ; GCN-NEXT: $vgpr0 = COPY [[DEF]](s32)456 ; GCN-NEXT: $vgpr1 = COPY [[DEF]](s32)457 ; GCN-NEXT: $vgpr2 = COPY [[DEF]](s32)458 ; GCN-NEXT: $vgpr3 = COPY [[DEF]](s32)459 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3460 %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)461 ret <4 x float> %tex462}463 464define amdgpu_ps float @image_load_tfe_f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {465 ; GCN-LABEL: name: image_load_tfe_f32_dmask_0000466 ; GCN: bb.1 (%ir-block.0):467 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1468 ; GCN-NEXT: {{ $}}469 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2470 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3471 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4472 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5473 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6474 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7475 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8476 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9477 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)478 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0479 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1480 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF481 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)482 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)483 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)484 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)485 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)486 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0487 %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)488 %tex = extractvalue { float, i32 } %res, 0489 %tfe = extractvalue { float, i32 } %res, 1490 store i32 %tfe, ptr addrspace(1) poison491 ret float %tex492}493 494define amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {495 ; GCN-LABEL: name: image_load_tfe_v2f32_dmask_1000496 ; GCN: bb.1 (%ir-block.0):497 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1498 ; GCN-NEXT: {{ $}}499 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2500 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3501 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4502 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5503 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6504 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7505 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8506 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9507 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)508 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0509 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1510 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF511 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)512 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)513 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)514 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)515 ; GCN-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)516 ; GCN-NEXT: $vgpr0 = COPY [[UV2]](s32)517 ; GCN-NEXT: $vgpr1 = COPY [[UV3]](s32)518 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1519 %res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)520 %tex = extractvalue { <2 x float>, i32 } %res, 0521 %tfe = extractvalue { <2 x float>, i32 } %res, 1522 store i32 %tfe, ptr addrspace(1) poison523 ret <2 x float> %tex524}525 526define amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {527 ; GCN-LABEL: name: image_load_tfe_v2f32_dmask_0000528 ; GCN: bb.1 (%ir-block.0):529 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1530 ; GCN-NEXT: {{ $}}531 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2532 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3533 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4534 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5535 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6536 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7537 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8538 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9539 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)540 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0541 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1542 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF543 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)544 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)545 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)546 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)547 ; GCN-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)548 ; GCN-NEXT: $vgpr0 = COPY [[UV2]](s32)549 ; GCN-NEXT: $vgpr1 = COPY [[UV3]](s32)550 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1551 %res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)552 %tex = extractvalue { <2 x float>, i32 } %res, 0553 %tfe = extractvalue { <2 x float>, i32 } %res, 1554 store i32 %tfe, ptr addrspace(1) poison555 ret <2 x float> %tex556}557 558define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {559 ; GCN-LABEL: name: image_load_tfe_v3f32_dmask_1100560 ; GCN: bb.1 (%ir-block.0):561 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1562 ; GCN-NEXT: {{ $}}563 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2564 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3565 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4566 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5567 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6568 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7569 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8570 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9571 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)572 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0573 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1574 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF575 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)576 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<2 x s32>), addrspace 8)577 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)578 ; GCN-NEXT: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)579 ; GCN-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)580 ; GCN-NEXT: $vgpr0 = COPY [[UV3]](s32)581 ; GCN-NEXT: $vgpr1 = COPY [[UV4]](s32)582 ; GCN-NEXT: $vgpr2 = COPY [[UV5]](s32)583 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2584 %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)585 %tex = extractvalue { <3 x float>, i32 } %res, 0586 %tfe = extractvalue { <3 x float>, i32 } %res, 1587 store i32 %tfe, ptr addrspace(1) poison588 ret <3 x float> %tex589}590 591define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {592 ; GCN-LABEL: name: image_load_tfe_v3f32_dmask_1000593 ; GCN: bb.1 (%ir-block.0):594 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1595 ; GCN-NEXT: {{ $}}596 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2597 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3598 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4599 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5600 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6601 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7602 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8603 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9604 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)605 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0606 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1607 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF608 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)609 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)610 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)611 ; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF612 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)613 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)614 ; GCN-NEXT: $vgpr1 = COPY [[DEF1]](s32)615 ; GCN-NEXT: $vgpr2 = COPY [[DEF1]](s32)616 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2617 %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)618 %tex = extractvalue { <3 x float>, i32 } %res, 0619 %tfe = extractvalue { <3 x float>, i32 } %res, 1620 store i32 %tfe, ptr addrspace(1) poison621 ret <3 x float> %tex622}623 624define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {625 ; GCN-LABEL: name: image_load_tfe_v3f32_dmask_0000626 ; GCN: bb.1 (%ir-block.0):627 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1628 ; GCN-NEXT: {{ $}}629 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2630 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3631 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4632 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5633 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6634 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7635 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8636 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9637 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)638 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0639 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1640 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF641 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)642 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)643 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)644 ; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF645 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)646 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)647 ; GCN-NEXT: $vgpr1 = COPY [[DEF1]](s32)648 ; GCN-NEXT: $vgpr2 = COPY [[DEF1]](s32)649 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2650 %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)651 %tex = extractvalue { <3 x float>, i32 } %res, 0652 %tfe = extractvalue { <3 x float>, i32 } %res, 1653 store i32 %tfe, ptr addrspace(1) poison654 ret <3 x float> %tex655}656 657define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {658 ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1110659 ; GCN: bb.1 (%ir-block.0):660 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1661 ; GCN-NEXT: {{ $}}662 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2663 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3664 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4665 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5666 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6667 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7668 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8669 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9670 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)671 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0672 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1673 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF674 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)675 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<3 x s32>), align 16, addrspace 8)676 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)677 ; GCN-NEXT: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)678 ; GCN-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)679 ; GCN-NEXT: $vgpr0 = COPY [[UV4]](s32)680 ; GCN-NEXT: $vgpr1 = COPY [[UV5]](s32)681 ; GCN-NEXT: $vgpr2 = COPY [[UV6]](s32)682 ; GCN-NEXT: $vgpr3 = COPY [[UV7]](s32)683 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3684 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)685 %tex = extractvalue { <4 x float>, i32 } %res, 0686 %tfe = extractvalue { <4 x float>, i32 } %res, 1687 store i32 %tfe, ptr addrspace(1) poison688 ret <4 x float> %tex689}690 691define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {692 ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1100693 ; GCN: bb.1 (%ir-block.0):694 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1695 ; GCN-NEXT: {{ $}}696 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2697 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3698 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4699 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5700 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6701 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7702 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8703 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9704 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)705 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0706 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1707 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF708 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)709 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<2 x s32>), addrspace 8)710 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)711 ; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF712 ; GCN-NEXT: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)713 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)714 ; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)715 ; GCN-NEXT: $vgpr2 = COPY [[DEF1]](s32)716 ; GCN-NEXT: $vgpr3 = COPY [[DEF1]](s32)717 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3718 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)719 %tex = extractvalue { <4 x float>, i32 } %res, 0720 %tfe = extractvalue { <4 x float>, i32 } %res, 1721 store i32 %tfe, ptr addrspace(1) poison722 ret <4 x float> %tex723}724 725define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {726 ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1000727 ; GCN: bb.1 (%ir-block.0):728 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1729 ; GCN-NEXT: {{ $}}730 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2731 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3732 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4733 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5734 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6735 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7736 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8737 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9738 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)739 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0740 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1741 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF742 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)743 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)744 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)745 ; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF746 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)747 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)748 ; GCN-NEXT: $vgpr1 = COPY [[DEF1]](s32)749 ; GCN-NEXT: $vgpr2 = COPY [[DEF1]](s32)750 ; GCN-NEXT: $vgpr3 = COPY [[DEF1]](s32)751 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3752 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)753 %tex = extractvalue { <4 x float>, i32 } %res, 0754 %tfe = extractvalue { <4 x float>, i32 } %res, 1755 store i32 %tfe, ptr addrspace(1) poison756 ret <4 x float> %tex757}758 759define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {760 ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_0000761 ; GCN: bb.1 (%ir-block.0):762 ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1763 ; GCN-NEXT: {{ $}}764 ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2765 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3766 ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4767 ; GCN-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5768 ; GCN-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6769 ; GCN-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7770 ; GCN-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8771 ; GCN-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9772 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)773 ; GCN-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0774 ; GCN-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1775 ; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF776 ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)777 ; GCN-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s32), addrspace 8)778 ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)779 ; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF780 ; GCN-NEXT: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)781 ; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)782 ; GCN-NEXT: $vgpr1 = COPY [[DEF1]](s32)783 ; GCN-NEXT: $vgpr2 = COPY [[DEF1]](s32)784 ; GCN-NEXT: $vgpr3 = COPY [[DEF1]](s32)785 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3786 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)787 %tex = extractvalue { <4 x float>, i32 } %res, 0788 %tfe = extractvalue { <4 x float>, i32 } %res, 1789 store i32 %tfe, ptr addrspace(1) poison790 ret <4 x float> %tex791}792 793declare float @llvm.amdgcn.image.load.2d.f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0794declare <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0795declare <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0796declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0797declare { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0798declare { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0799declare { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0800declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0801 802attributes #0 = { nounwind readonly }803