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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s3 4--- |5 6 define i32 @widen_load_range0_tbaa(ptr addrspace(1) %ptr) {7 %load = load i24, ptr addrspace(1) %ptr, !range !0, !tbaa !18 %zext = zext i24 %load to i329 ret i32 %zext10 }11 12 define i32 @widen_load_range1_tbaa(ptr addrspace(1) %ptr) {13 %load = load i24, ptr addrspace(1) %ptr, !range !0, !tbaa !114 %zext = zext i24 %load to i3215 ret i32 %zext16 }17 18 define i32 @widen_load_tbaa0(ptr addrspace(1) %ptr) {19 %load = load i24, ptr addrspace(1) %ptr, !tbaa !120 %zext = zext i24 %load to i3221 ret i32 %zext22 }23 24 define i32 @widen_load_tbaa1(ptr addrspace(1) %ptr) {25 %load = load i24, ptr addrspace(1) %ptr, !tbaa !126 %zext = zext i24 %load to i3227 ret i32 %zext28 }29 30 !0 = !{i24 0, i24 1048575}31 !1 = !{!"omnipotent char", !2}32 !2 = !{!"Simple C/C++ TBAA"}33 !3 = !{i24 0, i24 1048575}34...35 36# Make sure range metadata is not preserved when widening loads, but37# tbaa is.38---39name: widen_load_range0_tbaa40body: |41 bb.0:42 liveins: $vgpr0_vgpr143 ; SI-LABEL: name: widen_load_range0_tbaa44 ; SI: liveins: $vgpr0_vgpr145 ; SI-NEXT: {{ $}}46 ; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr147 ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)48 ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1677721549 ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]50 ; SI-NEXT: $vgpr0 = COPY [[AND]](s32)51 %0:_(p1) = COPY $vgpr0_vgpr152 %1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !range !0, !tbaa !1)53 %2:_(s32) = G_ZEXT %154 $vgpr0 = COPY %255 56...57 58# Result register type already matches the widened memory type.59---60name: widen_load_range1_tbaa61body: |62 bb.0:63 liveins: $vgpr0_vgpr164 ; SI-LABEL: name: widen_load_range1_tbaa65 ; SI: liveins: $vgpr0_vgpr166 ; SI-NEXT: {{ $}}67 ; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr168 ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)69 ; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)70 %0:_(p1) = COPY $vgpr0_vgpr171 %1:_(s32) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !range !3, !tbaa !1)72 $vgpr0 = COPY %173 74...75---76name: widen_load_tbaa077body: |78 bb.0:79 liveins: $vgpr0_vgpr180 ; SI-LABEL: name: widen_load_tbaa081 ; SI: liveins: $vgpr0_vgpr182 ; SI-NEXT: {{ $}}83 ; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr184 ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)85 ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1677721586 ; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]87 ; SI-NEXT: $vgpr0 = COPY [[AND]](s32)88 %0:_(p1) = COPY $vgpr0_vgpr189 %1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !tbaa !1)90 %2:_(s32) = G_ZEXT %191 $vgpr0 = COPY %292 93...94 95# Result register type already matches the widened memory type.96---97name: widen_load_tbaa198body: |99 bb.0:100 liveins: $vgpr0_vgpr1101 ; SI-LABEL: name: widen_load_tbaa1102 ; SI: liveins: $vgpr0_vgpr1103 ; SI-NEXT: {{ $}}104 ; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1105 ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)106 ; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)107 %0:_(p1) = COPY $vgpr0_vgpr1108 %1:_(s32) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !tbaa !1)109 $vgpr0 = COPY %1110 111...112