704 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -o - < %s | FileCheck %s --check-prefixes=GFX,GFX63; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -o - < %s | FileCheck %s --check-prefixes=GFX,GFX84; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX105; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX12506 7declare i16 @llvm.abs.i16(i16, i1)8declare i32 @llvm.abs.i32(i32, i1)9declare i64 @llvm.abs.i64(i64, i1)10declare <2 x i8> @llvm.abs.v2i8(<2 x i8>, i1)11declare <3 x i8> @llvm.abs.v3i8(<3 x i8>, i1)12declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)13declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)14declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)15 16define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {17; GFX6-LABEL: abs_sgpr_i16:18; GFX6: ; %bb.0:19; GFX6-NEXT: s_sext_i32_i16 s0, s020; GFX6-NEXT: s_abs_i32 s0, s021; GFX6-NEXT: ; return to shader part epilog22;23; GFX8-LABEL: abs_sgpr_i16:24; GFX8: ; %bb.0:25; GFX8-NEXT: s_sext_i32_i16 s0, s026; GFX8-NEXT: s_abs_i32 s0, s027; GFX8-NEXT: ; return to shader part epilog28;29; GFX10-LABEL: abs_sgpr_i16:30; GFX10: ; %bb.0:31; GFX10-NEXT: s_sext_i32_i16 s0, s032; GFX10-NEXT: s_abs_i32 s0, s033; GFX10-NEXT: ; return to shader part epilog34;35; GFX1250-LABEL: abs_sgpr_i16:36; GFX1250: ; %bb.0:37; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 138; GFX1250-NEXT: s_sext_i32_i16 s0, s039; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)40; GFX1250-NEXT: s_abs_i32 s0, s041; GFX1250-NEXT: ; return to shader part epilog42 %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)43 ret i16 %res44}45 46define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {47; GFX6-LABEL: abs_sgpr_i32:48; GFX6: ; %bb.0:49; GFX6-NEXT: s_abs_i32 s0, s050; GFX6-NEXT: ; return to shader part epilog51;52; GFX8-LABEL: abs_sgpr_i32:53; GFX8: ; %bb.0:54; GFX8-NEXT: s_abs_i32 s0, s055; GFX8-NEXT: ; return to shader part epilog56;57; GFX10-LABEL: abs_sgpr_i32:58; GFX10: ; %bb.0:59; GFX10-NEXT: s_abs_i32 s0, s060; GFX10-NEXT: ; return to shader part epilog61;62; GFX1250-LABEL: abs_sgpr_i32:63; GFX1250: ; %bb.0:64; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 165; GFX1250-NEXT: s_abs_i32 s0, s066; GFX1250-NEXT: ; return to shader part epilog67 %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)68 ret i32 %res69}70 71define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {72; GFX6-LABEL: abs_sgpr_i64:73; GFX6: ; %bb.0:74; GFX6-NEXT: s_ashr_i32 s2, s1, 3175; GFX6-NEXT: s_add_u32 s0, s0, s276; GFX6-NEXT: s_mov_b32 s3, s277; GFX6-NEXT: s_addc_u32 s1, s1, s278; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]79; GFX6-NEXT: ; return to shader part epilog80;81; GFX8-LABEL: abs_sgpr_i64:82; GFX8: ; %bb.0:83; GFX8-NEXT: s_ashr_i32 s2, s1, 3184; GFX8-NEXT: s_add_u32 s0, s0, s285; GFX8-NEXT: s_mov_b32 s3, s286; GFX8-NEXT: s_addc_u32 s1, s1, s287; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]88; GFX8-NEXT: ; return to shader part epilog89;90; GFX10-LABEL: abs_sgpr_i64:91; GFX10: ; %bb.0:92; GFX10-NEXT: s_ashr_i32 s2, s1, 3193; GFX10-NEXT: s_add_u32 s0, s0, s294; GFX10-NEXT: s_mov_b32 s3, s295; GFX10-NEXT: s_addc_u32 s1, s1, s296; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]97; GFX10-NEXT: ; return to shader part epilog98;99; GFX1250-LABEL: abs_sgpr_i64:100; GFX1250: ; %bb.0:101; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1102; GFX1250-NEXT: s_ashr_i32 s2, s1, 31103; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)104; GFX1250-NEXT: s_mov_b32 s3, s2105; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]106; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)107; GFX1250-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]108; GFX1250-NEXT: ; return to shader part epilog109 %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)110 ret i64 %res111}112 113define amdgpu_cs <4 x i32> @abs_sgpr_v4i32(<4 x i32> inreg %arg) {114; GFX6-LABEL: abs_sgpr_v4i32:115; GFX6: ; %bb.0:116; GFX6-NEXT: s_abs_i32 s0, s0117; GFX6-NEXT: s_abs_i32 s1, s1118; GFX6-NEXT: s_abs_i32 s2, s2119; GFX6-NEXT: s_abs_i32 s3, s3120; GFX6-NEXT: ; return to shader part epilog121;122; GFX8-LABEL: abs_sgpr_v4i32:123; GFX8: ; %bb.0:124; GFX8-NEXT: s_abs_i32 s0, s0125; GFX8-NEXT: s_abs_i32 s1, s1126; GFX8-NEXT: s_abs_i32 s2, s2127; GFX8-NEXT: s_abs_i32 s3, s3128; GFX8-NEXT: ; return to shader part epilog129;130; GFX10-LABEL: abs_sgpr_v4i32:131; GFX10: ; %bb.0:132; GFX10-NEXT: s_abs_i32 s0, s0133; GFX10-NEXT: s_abs_i32 s1, s1134; GFX10-NEXT: s_abs_i32 s2, s2135; GFX10-NEXT: s_abs_i32 s3, s3136; GFX10-NEXT: ; return to shader part epilog137;138; GFX1250-LABEL: abs_sgpr_v4i32:139; GFX1250: ; %bb.0:140; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1141; GFX1250-NEXT: s_abs_i32 s0, s0142; GFX1250-NEXT: s_abs_i32 s1, s1143; GFX1250-NEXT: s_abs_i32 s2, s2144; GFX1250-NEXT: s_abs_i32 s3, s3145; GFX1250-NEXT: ; return to shader part epilog146 %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)147 ret <4 x i32> %res148}149 150define i16 @abs_vgpr_i16(i16 %arg) {151; GFX6-LABEL: abs_vgpr_i16:152; GFX6: ; %bb.0:153; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)154; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16155; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0, v0156; GFX6-NEXT: v_max_i32_e32 v0, v0, v1157; GFX6-NEXT: s_setpc_b64 s[30:31]158;159; GFX8-LABEL: abs_vgpr_i16:160; GFX8: ; %bb.0:161; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)162; GFX8-NEXT: v_sub_u16_e32 v1, 0, v0163; GFX8-NEXT: v_max_i16_e32 v0, v0, v1164; GFX8-NEXT: s_setpc_b64 s[30:31]165;166; GFX10-LABEL: abs_vgpr_i16:167; GFX10: ; %bb.0:168; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)169; GFX10-NEXT: v_sub_nc_u16 v1, 0, v0170; GFX10-NEXT: v_max_i16 v0, v0, v1171; GFX10-NEXT: s_setpc_b64 s[30:31]172;173; GFX1250-LABEL: abs_vgpr_i16:174; GFX1250: ; %bb.0:175; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0176; GFX1250-NEXT: s_wait_kmcnt 0x0177; GFX1250-NEXT: v_sub_nc_u16 v1, 0, v0178; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)179; GFX1250-NEXT: v_max_i16 v0, v0, v1180; GFX1250-NEXT: s_set_pc_i64 s[30:31]181 %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)182 ret i16 %res183}184 185define i32 @abs_vgpr_i32(i32 %arg) {186; GFX6-LABEL: abs_vgpr_i32:187; GFX6: ; %bb.0:188; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)189; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0, v0190; GFX6-NEXT: v_max_i32_e32 v0, v0, v1191; GFX6-NEXT: s_setpc_b64 s[30:31]192;193; GFX8-LABEL: abs_vgpr_i32:194; GFX8: ; %bb.0:195; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)196; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 0, v0197; GFX8-NEXT: v_max_i32_e32 v0, v0, v1198; GFX8-NEXT: s_setpc_b64 s[30:31]199;200; GFX10-LABEL: abs_vgpr_i32:201; GFX10: ; %bb.0:202; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)203; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0204; GFX10-NEXT: v_max_i32_e32 v0, v0, v1205; GFX10-NEXT: s_setpc_b64 s[30:31]206;207; GFX1250-LABEL: abs_vgpr_i32:208; GFX1250: ; %bb.0:209; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0210; GFX1250-NEXT: s_wait_kmcnt 0x0211; GFX1250-NEXT: v_sub_nc_u32_e32 v1, 0, v0212; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)213; GFX1250-NEXT: v_max_i32_e32 v0, v0, v1214; GFX1250-NEXT: s_set_pc_i64 s[30:31]215 %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)216 ret i32 %res217}218 219define i64 @abs_vgpr_i64(i64 %arg) {220; GFX6-LABEL: abs_vgpr_i64:221; GFX6: ; %bb.0:222; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1224; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2225; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc226; GFX6-NEXT: v_xor_b32_e32 v0, v0, v2227; GFX6-NEXT: v_xor_b32_e32 v1, v1, v2228; GFX6-NEXT: s_setpc_b64 s[30:31]229;230; GFX8-LABEL: abs_vgpr_i64:231; GFX8: ; %bb.0:232; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)233; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1234; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2235; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc236; GFX8-NEXT: v_xor_b32_e32 v0, v0, v2237; GFX8-NEXT: v_xor_b32_e32 v1, v1, v2238; GFX8-NEXT: s_setpc_b64 s[30:31]239;240; GFX10-LABEL: abs_vgpr_i64:241; GFX10: ; %bb.0:242; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)243; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v1244; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2245; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo246; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2247; GFX10-NEXT: v_xor_b32_e32 v1, v1, v2248; GFX10-NEXT: s_setpc_b64 s[30:31]249;250; GFX1250-LABEL: abs_vgpr_i64:251; GFX1250: ; %bb.0:252; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0253; GFX1250-NEXT: s_wait_kmcnt 0x0254; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 31, v1255; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)256; GFX1250-NEXT: v_mov_b32_e32 v3, v2257; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]258; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)259; GFX1250-NEXT: v_xor_b32_e32 v0, v0, v2260; GFX1250-NEXT: v_xor_b32_e32 v1, v1, v2261; GFX1250-NEXT: s_set_pc_i64 s[30:31]262 %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)263 ret i64 %res264}265 266define <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {267; GFX6-LABEL: abs_vgpr_v4i32:268; GFX6: ; %bb.0:269; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)270; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v0271; GFX6-NEXT: v_max_i32_e32 v0, v0, v4272; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v1273; GFX6-NEXT: v_max_i32_e32 v1, v1, v4274; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v2275; GFX6-NEXT: v_max_i32_e32 v2, v2, v4276; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v3277; GFX6-NEXT: v_max_i32_e32 v3, v3, v4278; GFX6-NEXT: s_setpc_b64 s[30:31]279;280; GFX8-LABEL: abs_vgpr_v4i32:281; GFX8: ; %bb.0:282; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)283; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v0284; GFX8-NEXT: v_max_i32_e32 v0, v0, v4285; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v1286; GFX8-NEXT: v_max_i32_e32 v1, v1, v4287; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v2288; GFX8-NEXT: v_max_i32_e32 v2, v2, v4289; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v3290; GFX8-NEXT: v_max_i32_e32 v3, v3, v4291; GFX8-NEXT: s_setpc_b64 s[30:31]292;293; GFX10-LABEL: abs_vgpr_v4i32:294; GFX10: ; %bb.0:295; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)296; GFX10-NEXT: v_sub_nc_u32_e32 v4, 0, v0297; GFX10-NEXT: v_sub_nc_u32_e32 v5, 0, v1298; GFX10-NEXT: v_sub_nc_u32_e32 v6, 0, v2299; GFX10-NEXT: v_sub_nc_u32_e32 v7, 0, v3300; GFX10-NEXT: v_max_i32_e32 v0, v0, v4301; GFX10-NEXT: v_max_i32_e32 v1, v1, v5302; GFX10-NEXT: v_max_i32_e32 v2, v2, v6303; GFX10-NEXT: v_max_i32_e32 v3, v3, v7304; GFX10-NEXT: s_setpc_b64 s[30:31]305;306; GFX1250-LABEL: abs_vgpr_v4i32:307; GFX1250: ; %bb.0:308; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0309; GFX1250-NEXT: s_wait_kmcnt 0x0310; GFX1250-NEXT: v_dual_sub_nc_u32 v4, 0, v0 :: v_dual_sub_nc_u32 v5, 0, v1311; GFX1250-NEXT: v_dual_sub_nc_u32 v6, 0, v2 :: v_dual_sub_nc_u32 v7, 0, v3312; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)313; GFX1250-NEXT: v_max_i32_e32 v0, v0, v4314; GFX1250-NEXT: v_max_i32_e32 v1, v1, v5315; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)316; GFX1250-NEXT: v_max_i32_e32 v2, v2, v6317; GFX1250-NEXT: v_max_i32_e32 v3, v3, v7318; GFX1250-NEXT: s_set_pc_i64 s[30:31]319 %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)320 ret <4 x i32> %res321}322 323define amdgpu_cs <2 x i8> @abs_sgpr_v2i8(<2 x i8> inreg %arg) {324; GFX6-LABEL: abs_sgpr_v2i8:325; GFX6: ; %bb.0:326; GFX6-NEXT: s_sext_i32_i8 s0, s0327; GFX6-NEXT: s_sext_i32_i8 s1, s1328; GFX6-NEXT: s_abs_i32 s0, s0329; GFX6-NEXT: s_abs_i32 s1, s1330; GFX6-NEXT: ; return to shader part epilog331;332; GFX8-LABEL: abs_sgpr_v2i8:333; GFX8: ; %bb.0:334; GFX8-NEXT: s_sext_i32_i8 s0, s0335; GFX8-NEXT: s_sext_i32_i8 s1, s1336; GFX8-NEXT: s_abs_i32 s0, s0337; GFX8-NEXT: s_abs_i32 s1, s1338; GFX8-NEXT: ; return to shader part epilog339;340; GFX10-LABEL: abs_sgpr_v2i8:341; GFX10: ; %bb.0:342; GFX10-NEXT: s_sext_i32_i8 s0, s0343; GFX10-NEXT: s_sext_i32_i8 s1, s1344; GFX10-NEXT: s_abs_i32 s0, s0345; GFX10-NEXT: s_abs_i32 s1, s1346; GFX10-NEXT: ; return to shader part epilog347;348; GFX1250-LABEL: abs_sgpr_v2i8:349; GFX1250: ; %bb.0:350; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1351; GFX1250-NEXT: s_sext_i32_i8 s0, s0352; GFX1250-NEXT: s_sext_i32_i8 s1, s1353; GFX1250-NEXT: s_abs_i32 s0, s0354; GFX1250-NEXT: s_abs_i32 s1, s1355; GFX1250-NEXT: ; return to shader part epilog356 %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)357 ret <2 x i8> %res358}359 360define <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {361; GFX6-LABEL: abs_vgpr_v2i8:362; GFX6: ; %bb.0:363; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)364; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8365; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v0366; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8367; GFX6-NEXT: v_max_i32_e32 v0, v0, v2368; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v1369; GFX6-NEXT: v_max_i32_e32 v1, v1, v2370; GFX6-NEXT: s_setpc_b64 s[30:31]371;372; GFX8-LABEL: abs_vgpr_v2i8:373; GFX8: ; %bb.0:374; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)375; GFX8-NEXT: v_mov_b32_e32 v2, 0376; GFX8-NEXT: v_sub_u16_sdwa v3, v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0377; GFX8-NEXT: v_sub_u16_sdwa v2, v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0378; GFX8-NEXT: v_max_i16_sdwa v0, sext(v0), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD379; GFX8-NEXT: v_max_i16_sdwa v1, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD380; GFX8-NEXT: s_setpc_b64 s[30:31]381;382; GFX10-LABEL: abs_vgpr_v2i8:383; GFX10: ; %bb.0:384; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)385; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8386; GFX10-NEXT: v_bfe_i32 v1, v1, 0, 8387; GFX10-NEXT: v_sub_nc_u16 v2, 0, v0388; GFX10-NEXT: v_sub_nc_u16 v3, 0, v1389; GFX10-NEXT: v_max_i16 v0, v0, v2390; GFX10-NEXT: v_max_i16 v1, v1, v3391; GFX10-NEXT: s_setpc_b64 s[30:31]392;393; GFX1250-LABEL: abs_vgpr_v2i8:394; GFX1250: ; %bb.0:395; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0396; GFX1250-NEXT: s_wait_kmcnt 0x0397; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 8398; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 8399; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)400; GFX1250-NEXT: v_sub_nc_u16 v2, 0, v0401; GFX1250-NEXT: v_sub_nc_u16 v3, 0, v1402; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)403; GFX1250-NEXT: v_max_i16 v0, v0, v2404; GFX1250-NEXT: v_max_i16 v1, v1, v3405; GFX1250-NEXT: s_set_pc_i64 s[30:31]406 %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)407 ret <2 x i8> %res408}409 410define amdgpu_cs <3 x i8> @abs_sgpr_v3i8(<3 x i8> inreg %arg) {411; GFX6-LABEL: abs_sgpr_v3i8:412; GFX6: ; %bb.0:413; GFX6-NEXT: s_sext_i32_i8 s0, s0414; GFX6-NEXT: s_sext_i32_i8 s1, s1415; GFX6-NEXT: s_sext_i32_i8 s2, s2416; GFX6-NEXT: s_abs_i32 s0, s0417; GFX6-NEXT: s_abs_i32 s1, s1418; GFX6-NEXT: s_abs_i32 s2, s2419; GFX6-NEXT: ; return to shader part epilog420;421; GFX8-LABEL: abs_sgpr_v3i8:422; GFX8: ; %bb.0:423; GFX8-NEXT: s_sext_i32_i8 s0, s0424; GFX8-NEXT: s_sext_i32_i8 s1, s1425; GFX8-NEXT: s_sext_i32_i8 s2, s2426; GFX8-NEXT: s_abs_i32 s0, s0427; GFX8-NEXT: s_abs_i32 s1, s1428; GFX8-NEXT: s_abs_i32 s2, s2429; GFX8-NEXT: ; return to shader part epilog430;431; GFX10-LABEL: abs_sgpr_v3i8:432; GFX10: ; %bb.0:433; GFX10-NEXT: s_sext_i32_i8 s0, s0434; GFX10-NEXT: s_sext_i32_i8 s1, s1435; GFX10-NEXT: s_sext_i32_i8 s2, s2436; GFX10-NEXT: s_abs_i32 s0, s0437; GFX10-NEXT: s_abs_i32 s1, s1438; GFX10-NEXT: s_abs_i32 s2, s2439; GFX10-NEXT: ; return to shader part epilog440;441; GFX1250-LABEL: abs_sgpr_v3i8:442; GFX1250: ; %bb.0:443; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1444; GFX1250-NEXT: s_sext_i32_i8 s0, s0445; GFX1250-NEXT: s_sext_i32_i8 s1, s1446; GFX1250-NEXT: s_sext_i32_i8 s2, s2447; GFX1250-NEXT: s_abs_i32 s0, s0448; GFX1250-NEXT: s_abs_i32 s1, s1449; GFX1250-NEXT: s_abs_i32 s2, s2450; GFX1250-NEXT: ; return to shader part epilog451 %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)452 ret <3 x i8> %res453}454 455define <3 x i8> @abs_vgpr_v3i8(<3 x i8> %arg) {456; GFX6-LABEL: abs_vgpr_v3i8:457; GFX6: ; %bb.0:458; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)459; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8460; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v0461; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8462; GFX6-NEXT: v_max_i32_e32 v0, v0, v3463; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v1464; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 8465; GFX6-NEXT: v_max_i32_e32 v1, v1, v3466; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v2467; GFX6-NEXT: v_max_i32_e32 v2, v2, v3468; GFX6-NEXT: s_setpc_b64 s[30:31]469;470; GFX8-LABEL: abs_vgpr_v3i8:471; GFX8: ; %bb.0:472; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)473; GFX8-NEXT: v_mov_b32_e32 v3, 0474; GFX8-NEXT: v_sub_u16_sdwa v4, v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0475; GFX8-NEXT: v_max_i16_sdwa v0, sext(v0), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD476; GFX8-NEXT: v_sub_u16_sdwa v4, v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0477; GFX8-NEXT: v_sub_u16_sdwa v3, v3, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0478; GFX8-NEXT: v_max_i16_sdwa v1, sext(v1), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD479; GFX8-NEXT: v_max_i16_sdwa v2, sext(v2), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD480; GFX8-NEXT: s_setpc_b64 s[30:31]481;482; GFX10-LABEL: abs_vgpr_v3i8:483; GFX10: ; %bb.0:484; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)485; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8486; GFX10-NEXT: v_bfe_i32 v1, v1, 0, 8487; GFX10-NEXT: v_bfe_i32 v2, v2, 0, 8488; GFX10-NEXT: v_sub_nc_u16 v3, 0, v0489; GFX10-NEXT: v_sub_nc_u16 v4, 0, v1490; GFX10-NEXT: v_sub_nc_u16 v5, 0, v2491; GFX10-NEXT: v_max_i16 v0, v0, v3492; GFX10-NEXT: v_max_i16 v1, v1, v4493; GFX10-NEXT: v_max_i16 v2, v2, v5494; GFX10-NEXT: s_setpc_b64 s[30:31]495;496; GFX1250-LABEL: abs_vgpr_v3i8:497; GFX1250: ; %bb.0:498; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0499; GFX1250-NEXT: s_wait_kmcnt 0x0500; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 8501; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 8502; GFX1250-NEXT: v_bfe_i32 v2, v2, 0, 8503; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)504; GFX1250-NEXT: v_sub_nc_u16 v3, 0, v0505; GFX1250-NEXT: v_sub_nc_u16 v4, 0, v1506; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)507; GFX1250-NEXT: v_sub_nc_u16 v5, 0, v2508; GFX1250-NEXT: v_max_i16 v0, v0, v3509; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)510; GFX1250-NEXT: v_max_i16 v1, v1, v4511; GFX1250-NEXT: v_max_i16 v2, v2, v5512; GFX1250-NEXT: s_set_pc_i64 s[30:31]513 %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)514 ret <3 x i8> %res515}516 517define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {518; GFX6-LABEL: abs_sgpr_v2i16:519; GFX6: ; %bb.0:520; GFX6-NEXT: s_sext_i32_i16 s0, s0521; GFX6-NEXT: s_sext_i32_i16 s1, s1522; GFX6-NEXT: s_abs_i32 s0, s0523; GFX6-NEXT: s_abs_i32 s1, s1524; GFX6-NEXT: ; return to shader part epilog525;526; GFX8-LABEL: abs_sgpr_v2i16:527; GFX8: ; %bb.0:528; GFX8-NEXT: s_lshr_b32 s1, s0, 16529; GFX8-NEXT: s_sext_i32_i16 s1, s1530; GFX8-NEXT: s_sext_i32_i16 s0, s0531; GFX8-NEXT: s_abs_i32 s1, s1532; GFX8-NEXT: s_abs_i32 s0, s0533; GFX8-NEXT: s_lshl_b32 s1, s1, 16534; GFX8-NEXT: s_or_b32 s0, s0, s1535; GFX8-NEXT: ; return to shader part epilog536;537; GFX10-LABEL: abs_sgpr_v2i16:538; GFX10: ; %bb.0:539; GFX10-NEXT: s_sext_i32_i16 s1, s0540; GFX10-NEXT: s_ashr_i32 s0, s0, 16541; GFX10-NEXT: s_abs_i32 s1, s1542; GFX10-NEXT: s_abs_i32 s0, s0543; GFX10-NEXT: s_pack_ll_b32_b16 s0, s1, s0544; GFX10-NEXT: ; return to shader part epilog545;546; GFX1250-LABEL: abs_sgpr_v2i16:547; GFX1250: ; %bb.0:548; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1549; GFX1250-NEXT: s_sext_i32_i16 s1, s0550; GFX1250-NEXT: s_ashr_i32 s0, s0, 16551; GFX1250-NEXT: s_abs_i32 s1, s1552; GFX1250-NEXT: s_abs_i32 s0, s0553; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)554; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s1, s0555; GFX1250-NEXT: ; return to shader part epilog556 %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)557 ret <2 x i16> %res558}559 560define <2 x i16> @abs_vgpr_v2i16(<2 x i16> %arg) {561; GFX6-LABEL: abs_vgpr_v2i16:562; GFX6: ; %bb.0:563; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)564; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16565; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v0566; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16567; GFX6-NEXT: v_max_i32_e32 v0, v0, v2568; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v1569; GFX6-NEXT: v_max_i32_e32 v1, v1, v2570; GFX6-NEXT: s_setpc_b64 s[30:31]571;572; GFX8-LABEL: abs_vgpr_v2i16:573; GFX8: ; %bb.0:574; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)575; GFX8-NEXT: v_mov_b32_e32 v2, 0576; GFX8-NEXT: v_sub_u16_e32 v1, 0, v0577; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1578; GFX8-NEXT: v_max_i16_e32 v1, v0, v1579; GFX8-NEXT: v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD580; GFX8-NEXT: v_or_b32_e32 v0, v1, v0581; GFX8-NEXT: s_setpc_b64 s[30:31]582;583; GFX10-LABEL: abs_vgpr_v2i16:584; GFX10: ; %bb.0:585; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)586; GFX10-NEXT: v_pk_sub_i16 v1, 0, v0587; GFX10-NEXT: v_pk_max_i16 v0, v0, v1588; GFX10-NEXT: s_setpc_b64 s[30:31]589;590; GFX1250-LABEL: abs_vgpr_v2i16:591; GFX1250: ; %bb.0:592; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0593; GFX1250-NEXT: s_wait_kmcnt 0x0594; GFX1250-NEXT: v_pk_sub_i16 v1, 0, v0595; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)596; GFX1250-NEXT: v_pk_max_i16 v0, v0, v1597; GFX1250-NEXT: s_set_pc_i64 s[30:31]598 %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)599 ret <2 x i16> %res600}601 602define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {603; GFX6-LABEL: abs_sgpr_v3i16:604; GFX6: ; %bb.0:605; GFX6-NEXT: s_sext_i32_i16 s0, s0606; GFX6-NEXT: s_sext_i32_i16 s1, s1607; GFX6-NEXT: s_sext_i32_i16 s2, s2608; GFX6-NEXT: s_abs_i32 s0, s0609; GFX6-NEXT: s_abs_i32 s1, s1610; GFX6-NEXT: s_abs_i32 s2, s2611; GFX6-NEXT: ; return to shader part epilog612;613; GFX8-LABEL: abs_sgpr_v3i16:614; GFX8: ; %bb.0:615; GFX8-NEXT: s_lshr_b32 s2, s0, 16616; GFX8-NEXT: s_sext_i32_i16 s2, s2617; GFX8-NEXT: s_sext_i32_i16 s0, s0618; GFX8-NEXT: s_abs_i32 s2, s2619; GFX8-NEXT: s_abs_i32 s0, s0620; GFX8-NEXT: s_sext_i32_i16 s1, s1621; GFX8-NEXT: s_lshl_b32 s2, s2, 16622; GFX8-NEXT: s_abs_i32 s1, s1623; GFX8-NEXT: s_or_b32 s0, s0, s2624; GFX8-NEXT: ; return to shader part epilog625;626; GFX10-LABEL: abs_sgpr_v3i16:627; GFX10: ; %bb.0:628; GFX10-NEXT: s_sext_i32_i16 s2, s0629; GFX10-NEXT: s_ashr_i32 s0, s0, 16630; GFX10-NEXT: s_abs_i32 s2, s2631; GFX10-NEXT: s_abs_i32 s0, s0632; GFX10-NEXT: s_sext_i32_i16 s1, s1633; GFX10-NEXT: s_pack_ll_b32_b16 s0, s2, s0634; GFX10-NEXT: s_abs_i32 s1, s1635; GFX10-NEXT: ; return to shader part epilog636;637; GFX1250-LABEL: abs_sgpr_v3i16:638; GFX1250: ; %bb.0:639; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1640; GFX1250-NEXT: s_sext_i32_i16 s2, s0641; GFX1250-NEXT: s_ashr_i32 s0, s0, 16642; GFX1250-NEXT: s_abs_i32 s2, s2643; GFX1250-NEXT: s_abs_i32 s0, s0644; GFX1250-NEXT: s_sext_i32_i16 s1, s1645; GFX1250-NEXT: s_pack_ll_b32_b16 s0, s2, s0646; GFX1250-NEXT: s_abs_i32 s1, s1647; GFX1250-NEXT: ; return to shader part epilog648 %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)649 ret <3 x i16> %res650}651 652define <3 x i16> @abs_vgpr_v3i16(<3 x i16> %arg) {653; GFX6-LABEL: abs_vgpr_v3i16:654; GFX6: ; %bb.0:655; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)656; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16657; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v0658; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16659; GFX6-NEXT: v_max_i32_e32 v0, v0, v3660; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v1661; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16662; GFX6-NEXT: v_max_i32_e32 v1, v1, v3663; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v2664; GFX6-NEXT: v_max_i32_e32 v2, v2, v3665; GFX6-NEXT: s_setpc_b64 s[30:31]666;667; GFX8-LABEL: abs_vgpr_v3i16:668; GFX8: ; %bb.0:669; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)670; GFX8-NEXT: v_mov_b32_e32 v3, 0671; GFX8-NEXT: v_sub_u16_e32 v2, 0, v0672; GFX8-NEXT: v_sub_u16_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1673; GFX8-NEXT: v_sub_u16_e32 v4, 0, v1674; GFX8-NEXT: v_max_i16_e32 v2, v0, v2675; GFX8-NEXT: v_max_i16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD676; GFX8-NEXT: v_or_b32_e32 v0, v2, v0677; GFX8-NEXT: v_max_i16_e32 v1, v1, v4678; GFX8-NEXT: s_setpc_b64 s[30:31]679;680; GFX10-LABEL: abs_vgpr_v3i16:681; GFX10: ; %bb.0:682; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)683; GFX10-NEXT: v_pk_sub_i16 v2, 0, v0684; GFX10-NEXT: v_sub_nc_u16 v3, 0, v1685; GFX10-NEXT: v_pk_max_i16 v0, v0, v2686; GFX10-NEXT: v_max_i16 v1, v1, v3687; GFX10-NEXT: s_setpc_b64 s[30:31]688;689; GFX1250-LABEL: abs_vgpr_v3i16:690; GFX1250: ; %bb.0:691; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0692; GFX1250-NEXT: s_wait_kmcnt 0x0693; GFX1250-NEXT: v_pk_sub_i16 v2, 0, v0694; GFX1250-NEXT: v_sub_nc_u16 v3, 0, v1695; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)696; GFX1250-NEXT: v_pk_max_i16 v0, v0, v2697; GFX1250-NEXT: v_max_i16 v1, v1, v3698; GFX1250-NEXT: s_set_pc_i64 s[30:31]699 %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)700 ret <3 x i16> %res701}702;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:703; GFX: {{.*}}704