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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX10 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX11 %s4 5declare i32 @llvm.amdgcn.ballot.i32(i1)6declare i32 @llvm.ctpop.i32(i32)7 8; Test ballot(0)9 10define amdgpu_cs i32 @constant_false() {11; CHECK-LABEL: constant_false:12; CHECK: ; %bb.0:13; CHECK-NEXT: s_mov_b32 s0, 014; CHECK-NEXT: ; return to shader part epilog15 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 0)16 ret i32 %ballot17}18 19; Test ballot(1)20 21define amdgpu_cs i32 @constant_true() {22; CHECK-LABEL: constant_true:23; CHECK: ; %bb.0:24; CHECK-NEXT: s_mov_b32 s0, exec_lo25; CHECK-NEXT: ; return to shader part epilog26 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 1)27 ret i32 %ballot28}29 30; Test ballot of a non-comparison operation31 32define amdgpu_cs i32 @non_compare(i32 %x) {33; CHECK-LABEL: non_compare:34; CHECK: ; %bb.0:35; CHECK-NEXT: v_and_b32_e32 v0, 1, v036; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v037; CHECK-NEXT: s_and_b32 s0, vcc_lo, exec_lo38; CHECK-NEXT: ; return to shader part epilog39 %trunc = trunc i32 %x to i140 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %trunc)41 ret i32 %ballot42}43 44; Test ballot of comparisons45 46define amdgpu_cs i32 @compare_ints(i32 %x, i32 %y) {47; CHECK-LABEL: compare_ints:48; CHECK: ; %bb.0:49; CHECK-NEXT: v_cmp_eq_u32_e64 s0, v0, v150; CHECK-NEXT: ; return to shader part epilog51 %cmp = icmp eq i32 %x, %y52 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)53 ret i32 %ballot54}55 56define amdgpu_cs i32 @compare_int_with_constant(i32 %x) {57; CHECK-LABEL: compare_int_with_constant:58; CHECK: ; %bb.0:59; CHECK-NEXT: v_cmp_le_i32_e64 s0, 0x63, v060; CHECK-NEXT: ; return to shader part epilog61 %cmp = icmp sge i32 %x, 9962 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)63 ret i32 %ballot64}65 66define amdgpu_cs i32 @compare_floats(float %x, float %y) {67; CHECK-LABEL: compare_floats:68; CHECK: ; %bb.0:69; CHECK-NEXT: v_cmp_gt_f32_e64 s0, v0, v170; CHECK-NEXT: ; return to shader part epilog71 %cmp = fcmp ogt float %x, %y72 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)73 ret i32 %ballot74}75 76define amdgpu_cs i32 @ctpop_of_ballot(float %x, float %y) {77; CHECK-LABEL: ctpop_of_ballot:78; CHECK: ; %bb.0:79; CHECK-NEXT: v_cmp_gt_f32_e32 vcc_lo, v0, v180; CHECK-NEXT: s_bcnt1_i32_b32 s0, vcc_lo81; CHECK-NEXT: ; return to shader part epilog82 %cmp = fcmp ogt float %x, %y83 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)84 %bcnt = call i32 @llvm.ctpop.i32(i32 %ballot)85 ret i32 %bcnt86}87 88define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_non_compare(i32 %v) {89; CHECK-LABEL: branch_divergent_ballot_ne_zero_non_compare:90; CHECK: ; %bb.0:91; CHECK-NEXT: v_and_b32_e32 v0, 1, v092; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v093; CHECK-NEXT: s_and_b32 s0, vcc_lo, exec_lo94; CHECK-NEXT: s_cmp_eq_u32 s0, 095; CHECK-NEXT: s_cbranch_scc1 .LBB7_296; CHECK-NEXT: ; %bb.1: ; %true97; CHECK-NEXT: s_mov_b32 s0, 4298; CHECK-NEXT: s_branch .LBB7_399; CHECK-NEXT: .LBB7_2: ; %false100; CHECK-NEXT: s_mov_b32 s0, 33101; CHECK-NEXT: s_branch .LBB7_3102; CHECK-NEXT: .LBB7_3:103 %c = trunc i32 %v to i1104 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)105 %ballot_ne_zero = icmp ne i32 %ballot, 0106 br i1 %ballot_ne_zero, label %true, label %false107true:108 ret i32 42109false:110 ret i32 33111}112 113define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_non_compare(i32 inreg %v) {114; CHECK-LABEL: branch_uniform_ballot_ne_zero_non_compare:115; CHECK: ; %bb.0:116; CHECK-NEXT: s_xor_b32 s0, s0, 1117; CHECK-NEXT: s_and_b32 s0, s0, 1118; CHECK-NEXT: s_cmp_lg_u32 s0, 0119; CHECK-NEXT: s_cbranch_scc1 .LBB8_2120; CHECK-NEXT: ; %bb.1: ; %true121; CHECK-NEXT: s_mov_b32 s0, 42122; CHECK-NEXT: s_branch .LBB8_3123; CHECK-NEXT: .LBB8_2: ; %false124; CHECK-NEXT: s_mov_b32 s0, 33125; CHECK-NEXT: s_branch .LBB8_3126; CHECK-NEXT: .LBB8_3:127 %c = trunc i32 %v to i1128 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)129 %ballot_ne_zero = icmp ne i32 %ballot, 0130 br i1 %ballot_ne_zero, label %true, label %false131true:132 ret i32 42133false:134 ret i32 33135}136 137define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_non_compare(i32 %v) {138; CHECK-LABEL: branch_divergent_ballot_eq_zero_non_compare:139; CHECK: ; %bb.0:140; CHECK-NEXT: v_and_b32_e32 v0, 1, v0141; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0142; CHECK-NEXT: s_and_b32 s0, vcc_lo, exec_lo143; CHECK-NEXT: s_cbranch_scc0 .LBB9_2144; CHECK-NEXT: ; %bb.1: ; %false145; CHECK-NEXT: s_mov_b32 s0, 33146; CHECK-NEXT: s_branch .LBB9_3147; CHECK-NEXT: .LBB9_2: ; %true148; CHECK-NEXT: s_mov_b32 s0, 42149; CHECK-NEXT: s_branch .LBB9_3150; CHECK-NEXT: .LBB9_3:151 %c = trunc i32 %v to i1152 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)153 %ballot_eq_zero = icmp eq i32 %ballot, 0154 br i1 %ballot_eq_zero, label %true, label %false155true:156 ret i32 42157false:158 ret i32 33159}160 161define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_non_compare(i32 inreg %v) {162; CHECK-LABEL: branch_uniform_ballot_eq_zero_non_compare:163; CHECK: ; %bb.0:164; CHECK-NEXT: s_xor_b32 s0, s0, 1165; CHECK-NEXT: s_xor_b32 s0, s0, 1166; CHECK-NEXT: s_and_b32 s0, s0, 1167; CHECK-NEXT: s_cmp_lg_u32 s0, 0168; CHECK-NEXT: s_cbranch_scc1 .LBB10_2169; CHECK-NEXT: ; %bb.1: ; %true170; CHECK-NEXT: s_mov_b32 s0, 42171; CHECK-NEXT: s_branch .LBB10_3172; CHECK-NEXT: .LBB10_2: ; %false173; CHECK-NEXT: s_mov_b32 s0, 33174; CHECK-NEXT: s_branch .LBB10_3175; CHECK-NEXT: .LBB10_3:176 %c = trunc i32 %v to i1177 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)178 %ballot_eq_zero = icmp eq i32 %ballot, 0179 br i1 %ballot_eq_zero, label %true, label %false180true:181 ret i32 42182false:183 ret i32 33184}185 186define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_compare(i32 %v) {187; CHECK-LABEL: branch_divergent_ballot_ne_zero_compare:188; CHECK: ; %bb.0:189; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0190; CHECK-NEXT: s_cmp_eq_u32 vcc_lo, 0191; CHECK-NEXT: s_cbranch_scc1 .LBB11_2192; CHECK-NEXT: ; %bb.1: ; %true193; CHECK-NEXT: s_mov_b32 s0, 42194; CHECK-NEXT: s_branch .LBB11_3195; CHECK-NEXT: .LBB11_2: ; %false196; CHECK-NEXT: s_mov_b32 s0, 33197; CHECK-NEXT: s_branch .LBB11_3198; CHECK-NEXT: .LBB11_3:199 %c = icmp ult i32 %v, 12200 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)201 %ballot_ne_zero = icmp ne i32 %ballot, 0202 br i1 %ballot_ne_zero, label %true, label %false203true:204 ret i32 42205false:206 ret i32 33207}208 209define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_compare(i32 inreg %v) {210; CHECK-LABEL: branch_uniform_ballot_ne_zero_compare:211; CHECK: ; %bb.0:212; CHECK-NEXT: s_cmp_ge_u32 s0, 12213; CHECK-NEXT: s_cbranch_scc1 .LBB12_2214; CHECK-NEXT: ; %bb.1: ; %true215; CHECK-NEXT: s_mov_b32 s0, 42216; CHECK-NEXT: s_branch .LBB12_3217; CHECK-NEXT: .LBB12_2: ; %false218; CHECK-NEXT: s_mov_b32 s0, 33219; CHECK-NEXT: s_branch .LBB12_3220; CHECK-NEXT: .LBB12_3:221 %c = icmp ult i32 %v, 12222 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)223 %ballot_ne_zero = icmp ne i32 %ballot, 0224 br i1 %ballot_ne_zero, label %true, label %false225true:226 ret i32 42227false:228 ret i32 33229}230 231define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_compare(i32 %v) {232; CHECK-LABEL: branch_divergent_ballot_eq_zero_compare:233; CHECK: ; %bb.0:234; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0235; CHECK-NEXT: s_cmp_lg_u32 vcc_lo, 0236; CHECK-NEXT: s_cbranch_scc0 .LBB13_2237; CHECK-NEXT: ; %bb.1: ; %false238; CHECK-NEXT: s_mov_b32 s0, 33239; CHECK-NEXT: s_branch .LBB13_3240; CHECK-NEXT: .LBB13_2: ; %true241; CHECK-NEXT: s_mov_b32 s0, 42242; CHECK-NEXT: s_branch .LBB13_3243; CHECK-NEXT: .LBB13_3:244 %c = icmp ult i32 %v, 12245 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)246 %ballot_eq_zero = icmp eq i32 %ballot, 0247 br i1 %ballot_eq_zero, label %true, label %false248true:249 ret i32 42250false:251 ret i32 33252}253 254define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_compare(i32 inreg %v) {255; CHECK-LABEL: branch_uniform_ballot_eq_zero_compare:256; CHECK: ; %bb.0:257; CHECK-NEXT: s_cmp_lt_u32 s0, 12258; CHECK-NEXT: s_cbranch_scc1 .LBB14_2259; CHECK-NEXT: ; %bb.1: ; %true260; CHECK-NEXT: s_mov_b32 s0, 42261; CHECK-NEXT: s_branch .LBB14_3262; CHECK-NEXT: .LBB14_2: ; %false263; CHECK-NEXT: s_mov_b32 s0, 33264; CHECK-NEXT: s_branch .LBB14_3265; CHECK-NEXT: .LBB14_3:266 %c = icmp ult i32 %v, 12267 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)268 %ballot_eq_zero = icmp eq i32 %ballot, 0269 br i1 %ballot_eq_zero, label %true, label %false270true:271 ret i32 42272false:273 ret i32 33274}275 276define amdgpu_cs i32 @branch_divergent_ballot_ne_zero_and(i32 %v1, i32 %v2) {277; CHECK-LABEL: branch_divergent_ballot_ne_zero_and:278; CHECK: ; %bb.0:279; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0280; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1281; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0282; CHECK-NEXT: s_cmp_eq_u32 s0, 0283; CHECK-NEXT: s_cbranch_scc1 .LBB15_2284; CHECK-NEXT: ; %bb.1: ; %true285; CHECK-NEXT: s_mov_b32 s0, 42286; CHECK-NEXT: s_branch .LBB15_3287; CHECK-NEXT: .LBB15_2: ; %false288; CHECK-NEXT: s_mov_b32 s0, 33289; CHECK-NEXT: s_branch .LBB15_3290; CHECK-NEXT: .LBB15_3:291 %v1c = icmp ult i32 %v1, 12292 %v2c = icmp ugt i32 %v2, 34293 %c = and i1 %v1c, %v2c294 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)295 %ballot_ne_zero = icmp ne i32 %ballot, 0296 br i1 %ballot_ne_zero, label %true, label %false297true:298 ret i32 42299false:300 ret i32 33301}302 303define amdgpu_cs i32 @branch_uniform_ballot_ne_zero_and(i32 inreg %v1, i32 inreg %v2) {304; CHECK-LABEL: branch_uniform_ballot_ne_zero_and:305; CHECK: ; %bb.0:306; CHECK-NEXT: s_cmp_ge_u32 s0, 12307; CHECK-NEXT: s_cselect_b32 s0, 1, 0308; CHECK-NEXT: s_cmp_le_u32 s1, 34309; CHECK-NEXT: s_cselect_b32 s1, 1, 0310; CHECK-NEXT: s_or_b32 s0, s0, s1311; CHECK-NEXT: s_cmp_lg_u32 s0, 0312; CHECK-NEXT: s_cbranch_scc1 .LBB16_2313; CHECK-NEXT: ; %bb.1: ; %true314; CHECK-NEXT: s_mov_b32 s0, 42315; CHECK-NEXT: s_branch .LBB16_3316; CHECK-NEXT: .LBB16_2: ; %false317; CHECK-NEXT: s_mov_b32 s0, 33318; CHECK-NEXT: s_branch .LBB16_3319; CHECK-NEXT: .LBB16_3:320 %v1c = icmp ult i32 %v1, 12321 %v2c = icmp ugt i32 %v2, 34322 %c = and i1 %v1c, %v2c323 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)324 %ballot_ne_zero = icmp ne i32 %ballot, 0325 br i1 %ballot_ne_zero, label %true, label %false326true:327 ret i32 42328false:329 ret i32 33330}331 332define amdgpu_cs i32 @branch_divergent_ballot_eq_zero_and(i32 %v1, i32 %v2) {333; CHECK-LABEL: branch_divergent_ballot_eq_zero_and:334; CHECK: ; %bb.0:335; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0336; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1337; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0338; CHECK-NEXT: s_cbranch_scc0 .LBB17_2339; CHECK-NEXT: ; %bb.1: ; %false340; CHECK-NEXT: s_mov_b32 s0, 33341; CHECK-NEXT: s_branch .LBB17_3342; CHECK-NEXT: .LBB17_2: ; %true343; CHECK-NEXT: s_mov_b32 s0, 42344; CHECK-NEXT: s_branch .LBB17_3345; CHECK-NEXT: .LBB17_3:346 %v1c = icmp ult i32 %v1, 12347 %v2c = icmp ugt i32 %v2, 34348 %c = and i1 %v1c, %v2c349 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)350 %ballot_eq_zero = icmp eq i32 %ballot, 0351 br i1 %ballot_eq_zero, label %true, label %false352true:353 ret i32 42354false:355 ret i32 33356}357 358define amdgpu_cs i32 @branch_uniform_ballot_eq_zero_and(i32 inreg %v1, i32 inreg %v2) {359; CHECK-LABEL: branch_uniform_ballot_eq_zero_and:360; CHECK: ; %bb.0:361; CHECK-NEXT: s_cmp_lt_u32 s0, 12362; CHECK-NEXT: s_cselect_b32 s0, 1, 0363; CHECK-NEXT: s_cmp_gt_u32 s1, 34364; CHECK-NEXT: s_cselect_b32 s1, 1, 0365; CHECK-NEXT: s_and_b32 s0, s0, s1366; CHECK-NEXT: s_cmp_lg_u32 s0, 0367; CHECK-NEXT: s_cbranch_scc1 .LBB18_2368; CHECK-NEXT: ; %bb.1: ; %true369; CHECK-NEXT: s_mov_b32 s0, 42370; CHECK-NEXT: s_branch .LBB18_3371; CHECK-NEXT: .LBB18_2: ; %false372; CHECK-NEXT: s_mov_b32 s0, 33373; CHECK-NEXT: s_branch .LBB18_3374; CHECK-NEXT: .LBB18_3:375 %v1c = icmp ult i32 %v1, 12376 %v2c = icmp ugt i32 %v2, 34377 %c = and i1 %v1c, %v2c378 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)379 %ballot_eq_zero = icmp eq i32 %ballot, 0380 br i1 %ballot_eq_zero, label %true, label %false381true:382 ret i32 42383false:384 ret i32 33385}386 387define amdgpu_cs i32 @branch_uniform_ballot_sgt_N_compare(i32 inreg %v) {388; CHECK-LABEL: branch_uniform_ballot_sgt_N_compare:389; CHECK: ; %bb.0:390; CHECK-NEXT: s_cmp_lt_u32 s0, 12391; CHECK-NEXT: s_cselect_b32 s0, 1, 0392; CHECK-NEXT: s_and_b32 s0, 1, s0393; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, s0394; CHECK-NEXT: s_cmp_le_i32 s0, 22395; CHECK-NEXT: s_cbranch_scc1 .LBB19_2396; CHECK-NEXT: ; %bb.1: ; %true397; CHECK-NEXT: s_mov_b32 s0, 42398; CHECK-NEXT: s_branch .LBB19_3399; CHECK-NEXT: .LBB19_2: ; %false400; CHECK-NEXT: s_mov_b32 s0, 33401; CHECK-NEXT: s_branch .LBB19_3402; CHECK-NEXT: .LBB19_3:403 %c = icmp ult i32 %v, 12404 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %c)405 %bc = icmp sgt i32 %ballot, 22406 br i1 %bc, label %true, label %false407true:408 ret i32 42409false:410 ret i32 33411}412 413; Input that is not constant or direct result of a compare.414; Tests setting 0 to inactive lanes.415define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid, i32 %cond) {416; GFX10-LABEL: non_cst_non_compare_input:417; GFX10: ; %bb.0: ; %entry418; GFX10-NEXT: s_and_b32 s0, 1, s0419; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3420; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0421; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo422; GFX10-NEXT: s_xor_b32 s1, exec_lo, s1423; GFX10-NEXT: ; %bb.1: ; %B424; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 2, v2425; GFX10-NEXT: s_andn2_b32 s0, s0, exec_lo426; GFX10-NEXT: ; implicit-def: $vgpr2427; GFX10-NEXT: s_and_b32 s2, exec_lo, vcc_lo428; GFX10-NEXT: s_or_b32 s0, s0, s2429; GFX10-NEXT: ; %bb.2: ; %Flow430; GFX10-NEXT: s_andn2_saveexec_b32 s1, s1431; GFX10-NEXT: ; %bb.3: ; %A432; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 1, v2433; GFX10-NEXT: s_andn2_b32 s0, s0, exec_lo434; GFX10-NEXT: s_and_b32 s2, exec_lo, vcc_lo435; GFX10-NEXT: s_or_b32 s0, s0, s2436; GFX10-NEXT: ; %bb.4: ; %exit437; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1438; GFX10-NEXT: s_and_b32 s0, s0, exec_lo439; GFX10-NEXT: v_mov_b32_e32 v2, s0440; GFX10-NEXT: global_store_dword v[0:1], v2, off441; GFX10-NEXT: s_endpgm442;443; GFX11-LABEL: non_cst_non_compare_input:444; GFX11: ; %bb.0: ; %entry445; GFX11-NEXT: s_and_b32 s0, 1, s0446; GFX11-NEXT: s_mov_b32 s1, exec_lo447; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s0448; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3449; GFX11-NEXT: s_xor_b32 s1, exec_lo, s1450; GFX11-NEXT: ; %bb.1: ; %B451; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 2, v2452; GFX11-NEXT: s_and_not1_b32 s0, s0, exec_lo453; GFX11-NEXT: ; implicit-def: $vgpr2454; GFX11-NEXT: s_and_b32 s2, exec_lo, vcc_lo455; GFX11-NEXT: s_or_b32 s0, s0, s2456; GFX11-NEXT: ; %bb.2: ; %Flow457; GFX11-NEXT: s_and_not1_saveexec_b32 s1, s1458; GFX11-NEXT: ; %bb.3: ; %A459; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 1, v2460; GFX11-NEXT: s_and_not1_b32 s0, s0, exec_lo461; GFX11-NEXT: s_and_b32 s2, exec_lo, vcc_lo462; GFX11-NEXT: s_or_b32 s0, s0, s2463; GFX11-NEXT: ; %bb.4: ; %exit464; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s1465; GFX11-NEXT: s_and_b32 s0, s0, exec_lo466; GFX11-NEXT: v_mov_b32_e32 v2, s0467; GFX11-NEXT: global_store_b32 v[0:1], v2, off468; GFX11-NEXT: s_endpgm469entry:470 %cmp = icmp eq i32 %cond, 0471 br i1 %cmp, label %A, label %B472 473A:474 %val_A = icmp uge i32 %tid, 1475 br label %exit476 477B:478 %val_B = icmp ult i32 %tid, 2479 br label %exit480 481exit:482 %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ]483 %ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %phi)484 store i32 %ballot, ptr addrspace(1) %out485 ret void486}487