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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @test_wave64(i32 %arg0, i64 %saved) {5; GCN-LABEL: test_wave64:6; GCN: ; %bb.0: ; %entry7; GCN-NEXT: s_load_dword s0, s[8:9], 0x08; GCN-NEXT: s_waitcnt lgkmcnt(0)9; GCN-NEXT: s_cmp_lg_u32 s0, 010; GCN-NEXT: s_cbranch_scc1 .LBB0_211; GCN-NEXT: ; %bb.1: ; %mid12; GCN-NEXT: v_mov_b32_e32 v0, 013; GCN-NEXT: global_store_dword v[0:1], v0, off14; GCN-NEXT: s_waitcnt vmcnt(0)15; GCN-NEXT: .LBB0_2: ; %bb16; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x817; GCN-NEXT: s_waitcnt lgkmcnt(0)18; GCN-NEXT: s_or_b64 exec, exec, s[0:1]19; GCN-NEXT: v_mov_b32_e32 v0, 020; GCN-NEXT: global_store_dword v[0:1], v0, off21; GCN-NEXT: s_waitcnt vmcnt(0)22; GCN-NEXT: s_endpgm23entry:24 %cond = icmp eq i32 %arg0, 025 br i1 %cond, label %mid, label %bb26 27mid:28 store volatile i32 0, ptr addrspace(1) poison29 br label %bb30 31bb:32 call void @llvm.amdgcn.end.cf.i64(i64 %saved)33 store volatile i32 0, ptr addrspace(1) poison34 ret void35}36 37declare void @llvm.amdgcn.end.cf.i64(i64 %val)38