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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn--amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s4 5define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) {6; GFX10-LABEL: test_wave32:7; GFX10: ; %bb.0: ; %entry8; GFX10-NEXT: s_clause 0x19; GFX10-NEXT: s_load_dword s0, s[8:9], 0x010; GFX10-NEXT: s_load_dword s1, s[8:9], 0x2411; GFX10-NEXT: s_waitcnt lgkmcnt(0)12; GFX10-NEXT: s_cmp_eq_u32 s0, 013; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 014; GFX10-NEXT: s_and_b32 s0, exec_lo, s015; GFX10-NEXT: s_or_b32 s0, s0, s116; GFX10-NEXT: v_mov_b32_e32 v0, s017; GFX10-NEXT: global_store_dword v[0:1], v0, off18; GFX10-NEXT: s_waitcnt_vscnt null, 0x019; GFX10-NEXT: s_endpgm20;21; GFX11-LABEL: test_wave32:22; GFX11: ; %bb.0: ; %entry23; GFX11-NEXT: s_clause 0x124; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x025; GFX11-NEXT: s_load_b32 s1, s[4:5], 0x2426; GFX11-NEXT: s_waitcnt lgkmcnt(0)27; GFX11-NEXT: s_cmp_eq_u32 s0, 028; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 029; GFX11-NEXT: s_and_b32 s0, exec_lo, s030; GFX11-NEXT: s_or_b32 s0, s0, s131; GFX11-NEXT: v_mov_b32_e32 v0, s032; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc33; GFX11-NEXT: s_waitcnt_vscnt null, 0x034; GFX11-NEXT: s_endpgm35entry:36 %cond = icmp eq i32 %arg0, 037 %break = call i32 @llvm.amdgcn.if.break.i32(i1 %cond, i32 %saved)38 store volatile i32 %break, ptr addrspace(1) poison39 ret void40}41 42declare i32 @llvm.amdgcn.if.break.i32(i1, i32)43