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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=hawaii < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @test_wave64(i32 %arg0, [8 x i32], i64 %saved) {5; GCN-LABEL: test_wave64:6; GCN: ; %bb.0: ; %entry7; GCN-NEXT: s_load_dword s2, s[8:9], 0x08; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0xa9; GCN-NEXT: s_add_i32 s12, s12, s1710; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 811; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1312; GCN-NEXT: s_waitcnt lgkmcnt(0)13; GCN-NEXT: s_cmp_eq_u32 s2, 014; GCN-NEXT: s_cselect_b32 s2, 1, 015; GCN-NEXT: s_and_b32 s2, 1, s216; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s217; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]18; GCN-NEXT: v_mov_b32_e32 v0, s019; GCN-NEXT: v_mov_b32_e32 v1, s120; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1]21; GCN-NEXT: s_waitcnt vmcnt(0)22; GCN-NEXT: s_endpgm23entry:24 %cond = icmp eq i32 %arg0, 025 %break = call i64 @llvm.amdgcn.if.break.i64(i1 %cond, i64 %saved)26 store volatile i64 %break, ptr addrspace(1) poison27 ret void28}29 30declare i64 @llvm.amdgcn.if.break.i64(i1, i64)31