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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -o - %s | FileCheck -check-prefix=UNPACKED %s3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -o - %s | FileCheck -check-prefix=GFX81 %s4; FIXME: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s5; FIXME: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s6; FIXME: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -o - %s | FileCheck -check-prefix=GFX11 %s7; FIXME: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -o - %s | FileCheck -check-prefix=GFX12 %s8 9define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, half %data) {10; UNPACKED-LABEL: image_store_f16:11; UNPACKED: ; %bb.0:12; UNPACKED-NEXT: s_mov_b32 s0, s213; UNPACKED-NEXT: s_mov_b32 s1, s314; UNPACKED-NEXT: s_mov_b32 s2, s415; UNPACKED-NEXT: s_mov_b32 s3, s516; UNPACKED-NEXT: s_mov_b32 s4, s617; UNPACKED-NEXT: s_mov_b32 s5, s718; UNPACKED-NEXT: s_mov_b32 s6, s819; UNPACKED-NEXT: s_mov_b32 s7, s920; UNPACKED-NEXT: image_store v2, v[0:1], s[0:7] dmask:0x1 unorm d1621; UNPACKED-NEXT: s_endpgm22;23; GFX81-LABEL: image_store_f16:24; GFX81: ; %bb.0:25; GFX81-NEXT: s_mov_b32 s0, s226; GFX81-NEXT: s_mov_b32 s1, s327; GFX81-NEXT: s_mov_b32 s2, s428; GFX81-NEXT: s_mov_b32 s3, s529; GFX81-NEXT: s_mov_b32 s4, s630; GFX81-NEXT: s_mov_b32 s5, s731; GFX81-NEXT: s_mov_b32 s6, s832; GFX81-NEXT: s_mov_b32 s7, s933; GFX81-NEXT: image_store v2, v[0:1], s[0:7] dmask:0x1 unorm d1634; GFX81-NEXT: s_endpgm35 call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)36 ret void37}38 39define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <2 x half> %in) {40; UNPACKED-LABEL: image_store_v2f16:41; UNPACKED: ; %bb.0:42; UNPACKED-NEXT: s_mov_b32 s0, s243; UNPACKED-NEXT: s_mov_b32 s1, s344; UNPACKED-NEXT: s_mov_b32 s2, s445; UNPACKED-NEXT: s_mov_b32 s3, s546; UNPACKED-NEXT: s_mov_b32 s4, s647; UNPACKED-NEXT: s_mov_b32 s5, s748; UNPACKED-NEXT: s_mov_b32 s6, s849; UNPACKED-NEXT: s_mov_b32 s7, s950; UNPACKED-NEXT: v_lshrrev_b32_e32 v3, 16, v251; UNPACKED-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm d1652; UNPACKED-NEXT: s_endpgm53;54; GFX81-LABEL: image_store_v2f16:55; GFX81: ; %bb.0:56; GFX81-NEXT: s_mov_b32 s0, s257; GFX81-NEXT: s_mov_b32 s1, s358; GFX81-NEXT: s_mov_b32 s2, s459; GFX81-NEXT: s_mov_b32 s3, s560; GFX81-NEXT: s_mov_b32 s4, s661; GFX81-NEXT: s_mov_b32 s5, s762; GFX81-NEXT: s_mov_b32 s6, s863; GFX81-NEXT: s_mov_b32 s7, s964; GFX81-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm d1665; GFX81-NEXT: s_endpgm66 call void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)67 ret void68}69 70define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x half> %in) {71; UNPACKED-LABEL: image_store_v3f16:72; UNPACKED: ; %bb.0:73; UNPACKED-NEXT: v_mov_b32_e32 v5, v174; UNPACKED-NEXT: v_mov_b32_e32 v1, v275; UNPACKED-NEXT: s_mov_b32 s0, s276; UNPACKED-NEXT: s_mov_b32 s1, s377; UNPACKED-NEXT: s_mov_b32 s2, s478; UNPACKED-NEXT: s_mov_b32 s3, s579; UNPACKED-NEXT: s_mov_b32 s4, s680; UNPACKED-NEXT: s_mov_b32 s5, s781; UNPACKED-NEXT: s_mov_b32 s6, s882; UNPACKED-NEXT: s_mov_b32 s7, s983; UNPACKED-NEXT: v_mov_b32_e32 v4, v084; UNPACKED-NEXT: v_lshrrev_b32_e32 v2, 16, v185; UNPACKED-NEXT: image_store v[1:3], v[4:5], s[0:7] dmask:0x7 unorm d1686; UNPACKED-NEXT: s_endpgm87;88; GFX81-LABEL: image_store_v3f16:89; GFX81: ; %bb.0:90; GFX81-NEXT: v_lshrrev_b32_e32 v4, 16, v291; GFX81-NEXT: v_lshlrev_b32_e32 v4, 16, v492; GFX81-NEXT: s_mov_b32 s0, s293; GFX81-NEXT: s_mov_b32 s1, s394; GFX81-NEXT: s_mov_b32 s2, s495; GFX81-NEXT: s_mov_b32 s3, s596; GFX81-NEXT: s_mov_b32 s4, s697; GFX81-NEXT: s_mov_b32 s5, s798; GFX81-NEXT: s_mov_b32 s6, s899; GFX81-NEXT: s_mov_b32 s7, s9100; GFX81-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD101; GFX81-NEXT: v_and_b32_e32 v3, 0xffff, v3102; GFX81-NEXT: v_mov_b32_e32 v4, 0103; GFX81-NEXT: image_store v[2:4], v[0:1], s[0:7] dmask:0x7 unorm d16104; GFX81-NEXT: s_endpgm105 call void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half> %in, i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)106 ret void107}108 109define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x half> %in) {110; UNPACKED-LABEL: image_store_v4f16:111; UNPACKED: ; %bb.0:112; UNPACKED-NEXT: v_mov_b32_e32 v6, v1113; UNPACKED-NEXT: v_mov_b32_e32 v1, v2114; UNPACKED-NEXT: s_mov_b32 s0, s2115; UNPACKED-NEXT: s_mov_b32 s1, s3116; UNPACKED-NEXT: s_mov_b32 s2, s4117; UNPACKED-NEXT: s_mov_b32 s3, s5118; UNPACKED-NEXT: s_mov_b32 s4, s6119; UNPACKED-NEXT: s_mov_b32 s5, s7120; UNPACKED-NEXT: s_mov_b32 s6, s8121; UNPACKED-NEXT: s_mov_b32 s7, s9122; UNPACKED-NEXT: v_mov_b32_e32 v5, v0123; UNPACKED-NEXT: v_lshrrev_b32_e32 v2, 16, v1124; UNPACKED-NEXT: v_lshrrev_b32_e32 v4, 16, v3125; UNPACKED-NEXT: image_store v[1:4], v[5:6], s[0:7] dmask:0xf unorm d16126; UNPACKED-NEXT: s_endpgm127;128; GFX81-LABEL: image_store_v4f16:129; GFX81: ; %bb.0:130; GFX81-NEXT: s_mov_b32 s0, s2131; GFX81-NEXT: s_mov_b32 s1, s3132; GFX81-NEXT: s_mov_b32 s2, s4133; GFX81-NEXT: s_mov_b32 s3, s5134; GFX81-NEXT: s_mov_b32 s4, s6135; GFX81-NEXT: s_mov_b32 s5, s7136; GFX81-NEXT: s_mov_b32 s6, s8137; GFX81-NEXT: s_mov_b32 s7, s9138; GFX81-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm d16139; GFX81-NEXT: s_endpgm140 call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)141 ret void142}143 144declare void @llvm.amdgcn.image.store.2d.f16.i32(half, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0145declare void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0146declare void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0147declare void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0148 149attributes #0 = { nounwind writeonly }150