117 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-32BANK %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GFX8-32BANK %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx810 < %s | FileCheck -check-prefixes=GFX8-16BANK %s5 6define amdgpu_ps float @interp_f16(float %i, i32 inreg %m0) #0 {7; GFX9-32BANK-LABEL: interp_f16:8; GFX9-32BANK: ; %bb.0:9; GFX9-32BANK-NEXT: s_mov_b32 m0, s010; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 311; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y12; GFX9-32BANK-NEXT: ; return to shader part epilog13;14; GFX8-32BANK-LABEL: interp_f16:15; GFX8-32BANK: ; %bb.0:16; GFX8-32BANK-NEXT: s_mov_b32 m0, s017; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 318; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y19; GFX8-32BANK-NEXT: ; return to shader part epilog20;21; GFX8-16BANK-LABEL: interp_f16:22; GFX8-16BANK: ; %bb.0:23; GFX8-16BANK-NEXT: s_mov_b32 m0, s024; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y25; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 326; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v127; GFX8-16BANK-NEXT: ; return to shader part epilog28 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0)29 ret float %res30}31 32define amdgpu_ps float @interp_f16_high(float %i, i32 inreg %m0) #0 {33; GFX9-32BANK-LABEL: interp_f16_high:34; GFX9-32BANK: ; %bb.0:35; GFX9-32BANK-NEXT: s_mov_b32 m0, s036; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 337; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high38; GFX9-32BANK-NEXT: ; return to shader part epilog39;40; GFX8-32BANK-LABEL: interp_f16_high:41; GFX8-32BANK: ; %bb.0:42; GFX8-32BANK-NEXT: s_mov_b32 m0, s043; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 344; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high45; GFX8-32BANK-NEXT: ; return to shader part epilog46;47; GFX8-16BANK-LABEL: interp_f16_high:48; GFX8-16BANK: ; %bb.0:49; GFX8-16BANK-NEXT: s_mov_b32 m0, s050; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y51; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 352; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1 high53; GFX8-16BANK-NEXT: ; return to shader part epilog54 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 true, i32 %m0)55 ret float %res56}57 58define amdgpu_ps float @interp_f16_0_0(float %i, i32 inreg %m0) #0 {59; GFX9-32BANK-LABEL: interp_f16_0_0:60; GFX9-32BANK: ; %bb.0:61; GFX9-32BANK-NEXT: s_mov_b32 m0, s062; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 363; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x64; GFX9-32BANK-NEXT: ; return to shader part epilog65;66; GFX8-32BANK-LABEL: interp_f16_0_0:67; GFX8-32BANK: ; %bb.0:68; GFX8-32BANK-NEXT: s_mov_b32 m0, s069; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 370; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x71; GFX8-32BANK-NEXT: ; return to shader part epilog72;73; GFX8-16BANK-LABEL: interp_f16_0_0:74; GFX8-16BANK: ; %bb.0:75; GFX8-16BANK-NEXT: s_mov_b32 m0, s076; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr0.x77; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 378; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr0.x, v179; GFX8-16BANK-NEXT: ; return to shader part epilog80 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 0, i32 0, i1 false, i32 %m0)81 ret float %res82}83 84; Copy needed to legalize %i85define amdgpu_ps float @interp_f16_sgpr_i(float inreg %i,i32 inreg %m0) #0 {86; GFX9-32BANK-LABEL: interp_f16_sgpr_i:87; GFX9-32BANK: ; %bb.0:88; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s089; GFX9-32BANK-NEXT: s_mov_b32 m0, s190; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 391; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y92; GFX9-32BANK-NEXT: ; return to shader part epilog93;94; GFX8-32BANK-LABEL: interp_f16_sgpr_i:95; GFX8-32BANK: ; %bb.0:96; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s097; GFX8-32BANK-NEXT: s_mov_b32 m0, s198; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 399; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y100; GFX8-32BANK-NEXT: ; return to shader part epilog101;102; GFX8-16BANK-LABEL: interp_f16_sgpr_i:103; GFX8-16BANK: ; %bb.0:104; GFX8-16BANK-NEXT: s_mov_b32 m0, s1105; GFX8-16BANK-NEXT: v_mov_b32_e32 v0, s0106; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y107; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3108; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1109; GFX8-16BANK-NEXT: ; return to shader part epilog110 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0)111 ret float %res112}113 114declare float @llvm.amdgcn.interp.p1.f16(float, i32 immarg, i32 immarg, i1 immarg, i32) #0115 116attributes #0 = { nounwind readnone speculatable }117