133 lines · plain
1; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=CO-V4,HSA,ALL %s2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -check-prefixes=CO-V4,OS-MESA3D,ALL %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-unknown -mcpu=hawaii -mattr=+flat-for-global < %s | FileCheck -check-prefixes=OS-UNKNOWN,ALL %s4 5; ALL-LABEL: {{^}}test:6; OS-MESA3D: enable_sgpr_kernarg_segment_ptr = 17; CO-V4: s_load_dword s{{[0-9]+}}, s[8:9], 0xa8 9; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[4:5], 0xa10 11; HSA: .amdhsa_kernarg_size 812; HSA: .amdhsa_user_sgpr_kernarg_segment_ptr 113define amdgpu_kernel void @test(ptr addrspace(1) %out) #1 {14 %kernarg.segment.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()15 %gep = getelementptr i32, ptr addrspace(4) %kernarg.segment.ptr, i64 1016 %value = load i32, ptr addrspace(4) %gep17 store i32 %value, ptr addrspace(1) %out18 ret void19}20 21; ALL-LABEL: {{^}}test_implicit:22; OS-MESA3D: kernarg_segment_byte_size = 2423; OS-MESA3D: kernarg_segment_alignment = 424 25; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x1526 27; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x1528 29; HSA: .amdhsa_kernarg_size 830define amdgpu_kernel void @test_implicit(ptr addrspace(1) %out) #1 {31 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()32 %gep = getelementptr i32, ptr addrspace(4) %implicitarg.ptr, i64 1033 %value = load i32, ptr addrspace(4) %gep34 store i32 %value, ptr addrspace(1) %out35 ret void36}37 38; ALL-LABEL: {{^}}test_implicit_alignment:39; OS-MESA3D: kernarg_segment_byte_size = 2840; OS-MESA3D: kernarg_segment_alignment = 441 42; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc43; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x444; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x345; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]46; ALL: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]47 48; HSA: .amdhsa_kernarg_size 1249define amdgpu_kernel void @test_implicit_alignment(ptr addrspace(1) %out, <2 x i8> %in) #1 {50 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()51 %val = load i32, ptr addrspace(4) %implicitarg.ptr52 store i32 %val, ptr addrspace(1) %out53 ret void54}55 56; ALL-LABEL: {{^}}opencl_test_implicit_alignment57; OS-MESA3D: kernarg_segment_byte_size = 2858; OS-MESA3D: kernarg_segment_alignment = 459 60; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc61; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x462; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x363; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]64; ALL: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]65 66; HSA: .amdhsa_kernarg_size 6467define amdgpu_kernel void @opencl_test_implicit_alignment(ptr addrspace(1) %out, <2 x i8> %in) #2 {68 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()69 %val = load i32, ptr addrspace(4) %implicitarg.ptr70 store i32 %val, ptr addrspace(1) %out71 ret void72}73 74; ALL-LABEL: {{^}}test_no_kernargs:75; OS-MESA3D: enable_sgpr_kernarg_segment_ptr = 076; OS-MESA3D: kernarg_segment_byte_size = 077; OS-MESA3D: kernarg_segment_alignment = 478 79; HSA: s_mov_b64 [[OFFSET_NULL:s\[[0-9]+:[0-9]+\]]], 40{{$}}80; HSA: s_load_dword s{{[0-9]+}}, [[OFFSET_NULL]]81 82; HSA: .amdhsa_kernarg_size 083; HSA: .amdhsa_user_sgpr_kernarg_segment_ptr 084define amdgpu_kernel void @test_no_kernargs() #4 {85 %kernarg.segment.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()86 %gep = getelementptr i32, ptr addrspace(4) %kernarg.segment.ptr, i64 1087 %value = load i32, ptr addrspace(4) %gep88 store volatile i32 %value, ptr addrspace(1) poison89 ret void90}91 92; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs:93; OS-MESA3D: kernarg_segment_byte_size = 1694; OS-MESA3D: kernarg_segment_alignment = 495; HSA: .amdhsa_kernarg_size 4896define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs() #2 {97 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()98 %val = load volatile i32, ptr addrspace(4) %implicitarg.ptr99 store volatile i32 %val, ptr addrspace(1) null100 ret void101}102 103; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs_round_up:104; OS-MESA3D: kernarg_segment_byte_size = 16105; OS-MESA3D: kernarg_segment_alignment = 4106; HSA: .amdhsa_kernarg_size 40107define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs_round_up() #3 {108 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()109 %val = load volatile i32, ptr addrspace(4) %implicitarg.ptr110 store volatile i32 %val, ptr addrspace(1) null111 ret void112}113 114; ALL-LABEL: {{^}}func_kernarg_segment_ptr:115; ALL: v_mov_b32_e32 v0, 0{{$}}116; ALL: v_mov_b32_e32 v1, 0{{$}}117define ptr addrspace(4) @func_kernarg_segment_ptr() {118 %ptr = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()119 ret ptr addrspace(4) %ptr120}121 122declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0123declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0124 125attributes #0 = { nounwind readnone }126attributes #1 = { nounwind "amdgpu-implicitarg-num-bytes"="0" }127attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" }128attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" }129attributes #4 = { nounwind "amdgpu-implicitarg-num-bytes"="0" "amdgpu-no-implicitarg-ptr" }130 131!llvm.module.flags = !{!0}132!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}133