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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s5 6define float @v_rsq_clamp_f32(float %src) #0 {7; SI-LABEL: v_rsq_clamp_f32:8; SI: ; %bb.0:9; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10; SI-NEXT: v_rsq_clamp_f32_e32 v0, v011; SI-NEXT: s_setpc_b64 s[30:31]12;13; VI-LABEL: v_rsq_clamp_f32:14; VI: ; %bb.0:15; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; VI-NEXT: v_rsq_f32_e32 v0, v017; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v018; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v019; VI-NEXT: s_setpc_b64 s[30:31]20;21; GFX12-LABEL: v_rsq_clamp_f32:22; GFX12: ; %bb.0:23; GFX12-NEXT: s_wait_loadcnt_dscnt 0x024; GFX12-NEXT: s_wait_expcnt 0x025; GFX12-NEXT: s_wait_samplecnt 0x026; GFX12-NEXT: s_wait_bvhcnt 0x027; GFX12-NEXT: s_wait_kmcnt 0x028; GFX12-NEXT: v_rsq_f32_e32 v0, v029; GFX12-NEXT: v_mov_b32_e32 v1, 0xff7fffff30; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)31; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v132; GFX12-NEXT: s_setpc_b64 s[30:31]33 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src)34 ret float %rsq_clamp35}36 37define float @v_rsq_clamp_fabs_f32(float %src) #0 {38; SI-LABEL: v_rsq_clamp_fabs_f32:39; SI: ; %bb.0:40; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; SI-NEXT: v_rsq_clamp_f32_e64 v0, |v0|42; SI-NEXT: s_setpc_b64 s[30:31]43;44; VI-LABEL: v_rsq_clamp_fabs_f32:45; VI: ; %bb.0:46; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)47; VI-NEXT: v_rsq_f32_e64 v0, |v0|48; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v049; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v050; VI-NEXT: s_setpc_b64 s[30:31]51;52; GFX12-LABEL: v_rsq_clamp_fabs_f32:53; GFX12: ; %bb.0:54; GFX12-NEXT: s_wait_loadcnt_dscnt 0x055; GFX12-NEXT: s_wait_expcnt 0x056; GFX12-NEXT: s_wait_samplecnt 0x057; GFX12-NEXT: s_wait_bvhcnt 0x058; GFX12-NEXT: s_wait_kmcnt 0x059; GFX12-NEXT: v_rsq_f32_e64 v0, |v0|60; GFX12-NEXT: v_mov_b32_e32 v1, 0xff7fffff61; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)62; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v163; GFX12-NEXT: s_setpc_b64 s[30:31]64 %fabs.src = call float @llvm.fabs.f32(float %src)65 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %fabs.src)66 ret float %rsq_clamp67}68 69define double @v_rsq_clamp_f64(double %src) #0 {70; SI-LABEL: v_rsq_clamp_f64:71; SI: ; %bb.0:72; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)73; SI-NEXT: v_rsq_clamp_f64_e32 v[0:1], v[0:1]74; SI-NEXT: s_setpc_b64 s[30:31]75;76; VI-LABEL: v_rsq_clamp_f64:77; VI: ; %bb.0:78; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)79; VI-NEXT: v_rsq_f64_e32 v[0:1], v[0:1]80; VI-NEXT: v_mov_b32_e32 v2, -181; VI-NEXT: v_mov_b32_e32 v3, 0x7fefffff82; VI-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]83; VI-NEXT: v_mov_b32_e32 v2, -184; VI-NEXT: v_mov_b32_e32 v3, 0xffefffff85; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]86; VI-NEXT: s_setpc_b64 s[30:31]87;88; GFX12-LABEL: v_rsq_clamp_f64:89; GFX12: ; %bb.0:90; GFX12-NEXT: s_wait_loadcnt_dscnt 0x091; GFX12-NEXT: s_wait_expcnt 0x092; GFX12-NEXT: s_wait_samplecnt 0x093; GFX12-NEXT: s_wait_bvhcnt 0x094; GFX12-NEXT: s_wait_kmcnt 0x095; GFX12-NEXT: v_rsq_f64_e32 v[0:1], v[0:1]96; GFX12-NEXT: v_mov_b32_e32 v2, -197; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff98; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)99; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]100; GFX12-NEXT: v_mov_b32_e32 v2, -1101; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff102; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)103; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]104; GFX12-NEXT: s_setpc_b64 s[30:31]105 %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)106 ret double %rsq_clamp107}108 109define double @v_rsq_clamp_fabs_f64(double %src) #0 {110; SI-LABEL: v_rsq_clamp_fabs_f64:111; SI: ; %bb.0:112; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; SI-NEXT: v_rsq_clamp_f64_e64 v[0:1], |v[0:1]|114; SI-NEXT: s_setpc_b64 s[30:31]115;116; VI-LABEL: v_rsq_clamp_fabs_f64:117; VI: ; %bb.0:118; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)119; VI-NEXT: v_rsq_f64_e64 v[0:1], |v[0:1]|120; VI-NEXT: v_mov_b32_e32 v2, -1121; VI-NEXT: v_mov_b32_e32 v3, 0x7fefffff122; VI-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]123; VI-NEXT: v_mov_b32_e32 v2, -1124; VI-NEXT: v_mov_b32_e32 v3, 0xffefffff125; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]126; VI-NEXT: s_setpc_b64 s[30:31]127;128; GFX12-LABEL: v_rsq_clamp_fabs_f64:129; GFX12: ; %bb.0:130; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0131; GFX12-NEXT: s_wait_expcnt 0x0132; GFX12-NEXT: s_wait_samplecnt 0x0133; GFX12-NEXT: s_wait_bvhcnt 0x0134; GFX12-NEXT: s_wait_kmcnt 0x0135; GFX12-NEXT: v_rsq_f64_e64 v[0:1], |v[0:1]|136; GFX12-NEXT: v_mov_b32_e32 v2, -1137; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff138; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)139; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]140; GFX12-NEXT: v_mov_b32_e32 v2, -1141; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff142; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)143; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]144; GFX12-NEXT: s_setpc_b64 s[30:31]145 %fabs.src = call double @llvm.fabs.f64(double %src)146 %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %fabs.src)147 ret double %rsq_clamp148}149 150define float @v_rsq_clamp_undef_f32() #0 {151; SI-LABEL: v_rsq_clamp_undef_f32:152; SI: ; %bb.0:153; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)154; SI-NEXT: v_rsq_clamp_f32_e32 v0, s4155; SI-NEXT: s_setpc_b64 s[30:31]156;157; VI-LABEL: v_rsq_clamp_undef_f32:158; VI: ; %bb.0:159; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)160; VI-NEXT: v_rsq_f32_e32 v0, s4161; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0162; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v0163; VI-NEXT: s_setpc_b64 s[30:31]164;165; GFX12-LABEL: v_rsq_clamp_undef_f32:166; GFX12: ; %bb.0:167; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0168; GFX12-NEXT: s_wait_expcnt 0x0169; GFX12-NEXT: s_wait_samplecnt 0x0170; GFX12-NEXT: s_wait_bvhcnt 0x0171; GFX12-NEXT: s_wait_kmcnt 0x0172; GFX12-NEXT: v_s_rsq_f32 s0, s0173; GFX12-NEXT: v_mov_b32_e32 v0, 0xff7fffff174; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)175; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)176; GFX12-NEXT: v_minmax_num_f32 v0, s0, 0x7f7fffff, v0177; GFX12-NEXT: s_setpc_b64 s[30:31]178 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float poison)179 ret float %rsq_clamp180}181 182define double @v_rsq_clamp_undef_f64() #0 {183; SI-LABEL: v_rsq_clamp_undef_f64:184; SI: ; %bb.0:185; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)186; SI-NEXT: v_rsq_clamp_f64_e32 v[0:1], s[4:5]187; SI-NEXT: s_setpc_b64 s[30:31]188;189; VI-LABEL: v_rsq_clamp_undef_f64:190; VI: ; %bb.0:191; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)192; VI-NEXT: v_rsq_f64_e32 v[0:1], s[4:5]193; VI-NEXT: v_mov_b32_e32 v2, -1194; VI-NEXT: v_mov_b32_e32 v3, 0x7fefffff195; VI-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]196; VI-NEXT: v_mov_b32_e32 v2, -1197; VI-NEXT: v_mov_b32_e32 v3, 0xffefffff198; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]199; VI-NEXT: s_setpc_b64 s[30:31]200;201; GFX12-LABEL: v_rsq_clamp_undef_f64:202; GFX12: ; %bb.0:203; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0204; GFX12-NEXT: s_wait_expcnt 0x0205; GFX12-NEXT: s_wait_samplecnt 0x0206; GFX12-NEXT: s_wait_bvhcnt 0x0207; GFX12-NEXT: s_wait_kmcnt 0x0208; GFX12-NEXT: v_rsq_f64_e32 v[0:1], s[0:1]209; GFX12-NEXT: v_mov_b32_e32 v2, -1210; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff211; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)212; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]213; GFX12-NEXT: v_mov_b32_e32 v2, -1214; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff215; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)216; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]217; GFX12-NEXT: s_setpc_b64 s[30:31]218 %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double poison)219 ret double %rsq_clamp220}221 222define float @v_rsq_clamp_f32_non_ieee(float %src) #2 {223; SI-LABEL: v_rsq_clamp_f32_non_ieee:224; SI: ; %bb.0:225; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)226; SI-NEXT: v_rsq_clamp_f32_e32 v0, v0227; SI-NEXT: s_setpc_b64 s[30:31]228;229; VI-LABEL: v_rsq_clamp_f32_non_ieee:230; VI: ; %bb.0:231; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)232; VI-NEXT: v_rsq_f32_e32 v0, v0233; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0234; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v0235; VI-NEXT: s_setpc_b64 s[30:31]236;237; GFX12-LABEL: v_rsq_clamp_f32_non_ieee:238; GFX12: ; %bb.0:239; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0240; GFX12-NEXT: s_wait_expcnt 0x0241; GFX12-NEXT: s_wait_samplecnt 0x0242; GFX12-NEXT: s_wait_bvhcnt 0x0243; GFX12-NEXT: s_wait_kmcnt 0x0244; GFX12-NEXT: v_rsq_f32_e32 v0, v0245; GFX12-NEXT: v_mov_b32_e32 v1, 0xff7fffff246; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)247; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v1248; GFX12-NEXT: s_setpc_b64 s[30:31]249 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src)250 ret float %rsq_clamp251}252 253define double @v_rsq_clamp_f64_non_ieee(double %src) #2 {254; SI-LABEL: v_rsq_clamp_f64_non_ieee:255; SI: ; %bb.0:256; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)257; SI-NEXT: v_rsq_clamp_f64_e32 v[0:1], v[0:1]258; SI-NEXT: s_setpc_b64 s[30:31]259;260; VI-LABEL: v_rsq_clamp_f64_non_ieee:261; VI: ; %bb.0:262; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)263; VI-NEXT: v_rsq_f64_e32 v[0:1], v[0:1]264; VI-NEXT: v_mov_b32_e32 v2, -1265; VI-NEXT: v_mov_b32_e32 v3, 0x7fefffff266; VI-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]267; VI-NEXT: v_mov_b32_e32 v2, -1268; VI-NEXT: v_mov_b32_e32 v3, 0xffefffff269; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]270; VI-NEXT: s_setpc_b64 s[30:31]271;272; GFX12-LABEL: v_rsq_clamp_f64_non_ieee:273; GFX12: ; %bb.0:274; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0275; GFX12-NEXT: s_wait_expcnt 0x0276; GFX12-NEXT: s_wait_samplecnt 0x0277; GFX12-NEXT: s_wait_bvhcnt 0x0278; GFX12-NEXT: s_wait_kmcnt 0x0279; GFX12-NEXT: v_rsq_f64_e32 v[0:1], v[0:1]280; GFX12-NEXT: v_mov_b32_e32 v2, -1281; GFX12-NEXT: v_mov_b32_e32 v3, 0x7fefffff282; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)283; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]284; GFX12-NEXT: v_mov_b32_e32 v2, -1285; GFX12-NEXT: v_mov_b32_e32 v3, 0xffefffff286; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)287; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]288; GFX12-NEXT: s_setpc_b64 s[30:31]289 %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)290 ret double %rsq_clamp291}292 293declare float @llvm.fabs.f32(float) #1294declare float @llvm.amdgcn.rsq.clamp.f32(float) #1295declare double @llvm.fabs.f64(double) #1296declare double @llvm.amdgcn.rsq.clamp.f64(double) #1297 298attributes #0 = { nounwind }299attributes #1 = { nounwind readnone }300attributes #2 = { nounwind "amdgpu-ieee"="false" }301