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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @set_inactive(ptr addrspace(1) %out, i32 %in) {5; GCN-LABEL: set_inactive:6; GCN:       ; %bb.0:7; GCN-NEXT:    s_load_dword s3, s[4:5], 0x2c8; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x249; GCN-NEXT:    s_mov_b32 s2, -110; GCN-NEXT:    s_waitcnt lgkmcnt(0)11; GCN-NEXT:    v_mov_b32_e32 v1, s312; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -113; GCN-NEXT:    v_cndmask_b32_e64 v0, 42, v1, s[4:5]14; GCN-NEXT:    s_mov_b64 exec, s[4:5]15; GCN-NEXT:    v_mov_b32_e32 v1, v016; GCN-NEXT:    s_mov_b32 s3, 0xf00017; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 018; GCN-NEXT:    s_endpgm19  %tmp.0 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #020  %tmp = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp.0)21  store i32 %tmp, ptr addrspace(1) %out22  ret void23}24 25define amdgpu_kernel void @set_inactive_imm_poison(ptr addrspace(1) %out) {26; GCN-LABEL: set_inactive_imm_poison:27; GCN:       ; %bb.0:28; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2429; GCN-NEXT:    v_mov_b32_e32 v0, 130; GCN-NEXT:    v_mov_b32_e32 v1, v031; GCN-NEXT:    s_mov_b32 s2, -132; GCN-NEXT:    s_mov_b32 s3, 0xf00033; GCN-NEXT:    s_waitcnt lgkmcnt(0)34; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 035; GCN-NEXT:    s_endpgm36  %tmp.0 = call i32 @llvm.amdgcn.set.inactive.i32(i32 1, i32 poison) #037  %tmp = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp.0)38  store i32 %tmp, ptr addrspace(1) %out39  ret void40}41 42define amdgpu_kernel void @set_inactive_64(ptr addrspace(1) %out, i64 %in) {43; GCN-LABEL: set_inactive_64:44; GCN:       ; %bb.0:45; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2446; GCN-NEXT:    s_waitcnt lgkmcnt(0)47; GCN-NEXT:    v_mov_b32_e32 v2, s248; GCN-NEXT:    v_mov_b32_e32 v3, s349; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -150; GCN-NEXT:    s_mov_b32 s2, -151; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v2, s[4:5]52; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v3, s[4:5]53; GCN-NEXT:    s_mov_b64 exec, s[4:5]54; GCN-NEXT:    v_mov_b32_e32 v2, v055; GCN-NEXT:    v_mov_b32_e32 v3, v156; GCN-NEXT:    s_mov_b32 s3, 0xf00057; GCN-NEXT:    buffer_store_dwordx2 v[2:3], off, s[0:3], 058; GCN-NEXT:    s_endpgm59  %tmp.0 = call i64 @llvm.amdgcn.set.inactive.i64(i64 %in, i64 0) #060  %tmp = call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp.0)61  store i64 %tmp, ptr addrspace(1) %out62  ret void63}64 65define amdgpu_kernel void @set_inactive_imm_poison_64(ptr addrspace(1) %out) {66; GCN-LABEL: set_inactive_imm_poison_64:67; GCN:       ; %bb.0:68; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2469; GCN-NEXT:    v_mov_b32_e32 v0, 170; GCN-NEXT:    v_mov_b32_e32 v1, 071; GCN-NEXT:    v_mov_b32_e32 v2, v072; GCN-NEXT:    v_mov_b32_e32 v3, v173; GCN-NEXT:    s_mov_b32 s2, -174; GCN-NEXT:    s_mov_b32 s3, 0xf00075; GCN-NEXT:    s_waitcnt lgkmcnt(0)76; GCN-NEXT:    buffer_store_dwordx2 v[2:3], off, s[0:3], 077; GCN-NEXT:    s_endpgm78  %tmp.0 = call i64 @llvm.amdgcn.set.inactive.i64(i64 1, i64 poison) #079  %tmp = call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp.0)80  store i64 %tmp, ptr addrspace(1) %out81  ret void82}83 84define amdgpu_kernel void @set_inactive_scc(ptr addrspace(1) %out, i32 %in, <4 x i32> inreg %desc) {85; GCN-LABEL: set_inactive_scc:86; GCN:       ; %bb.0:87; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x3488; GCN-NEXT:    s_load_dword s6, s[4:5], 0x2c89; GCN-NEXT:    s_waitcnt lgkmcnt(0)90; GCN-NEXT:    s_buffer_load_dword s7, s[0:3], 0x091; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2492; GCN-NEXT:    v_mov_b32_e32 v1, s693; GCN-NEXT:    s_or_saveexec_b64 s[2:3], -194; GCN-NEXT:    v_cndmask_b32_e64 v0, 42, v1, s[2:3]95; GCN-NEXT:    s_mov_b64 exec, s[2:3]96; GCN-NEXT:    s_waitcnt lgkmcnt(0)97; GCN-NEXT:    s_cmp_lg_u32 s7, 5698; GCN-NEXT:    v_mov_b32_e32 v1, v099; GCN-NEXT:    s_mov_b32 s2, 1100; GCN-NEXT:    s_cbranch_scc0 .LBB4_2101; GCN-NEXT:  ; %bb.1: ; %.one102; GCN-NEXT:    v_add_u32_e32 v2, vcc, 1, v1103; GCN-NEXT:    s_mov_b32 s2, -1104; GCN-NEXT:    s_mov_b32 s3, 0xf000105; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], 0106; GCN-NEXT:    s_mov_b32 s2, 0107; GCN-NEXT:  .LBB4_2: ; %Flow108; GCN-NEXT:    s_xor_b32 s2, s2, 1109; GCN-NEXT:    s_cmp_lg_u32 s2, 0110; GCN-NEXT:    s_cbranch_scc1 .LBB4_4111; GCN-NEXT:  ; %bb.3: ; %.zero112; GCN-NEXT:    s_mov_b32 s2, -1113; GCN-NEXT:    s_mov_b32 s3, 0xf000114; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0115; GCN-NEXT:  .LBB4_4: ; %.exit116; GCN-NEXT:    s_endpgm117  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0)118  %cmp = icmp eq i32 %val, 56119  %tmp.0 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0120  %tmp = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp.0)121  br i1 %cmp, label %.zero, label %.one122 123.zero:124  store i32 %tmp, ptr addrspace(1) %out125  br label %.exit126 127.one:128  %tmp.1 = add i32 %tmp, 1129  store i32 %tmp.1, ptr addrspace(1) %out130  br label %.exit131 132.exit:133  ret void134}135 136define amdgpu_kernel void @set_inactive_f32(ptr addrspace(1) %out, float %in) {137; GCN-LABEL: set_inactive_f32:138; GCN:       ; %bb.0:139; GCN-NEXT:    s_load_dword s6, s[4:5], 0x2c140; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24141; GCN-NEXT:    s_or_saveexec_b64 s[2:3], -1142; GCN-NEXT:    v_mov_b32_e32 v0, 0x40400000143; GCN-NEXT:    s_mov_b64 exec, s[2:3]144; GCN-NEXT:    s_mov_b32 s2, -1145; GCN-NEXT:    s_waitcnt lgkmcnt(0)146; GCN-NEXT:    v_mov_b32_e32 v1, s6147; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1148; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]149; GCN-NEXT:    s_mov_b64 exec, s[4:5]150; GCN-NEXT:    v_mov_b32_e32 v1, v0151; GCN-NEXT:    s_mov_b32 s3, 0xf000152; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0153; GCN-NEXT:    s_endpgm154  %tmp.0 = call float @llvm.amdgcn.set.inactive.f32(float %in, float 3.0) #0155  %tmp = call float @llvm.amdgcn.strict.wwm.f32(float %tmp.0)156  store float %tmp, ptr addrspace(1) %out157  ret void158}159 160define amdgpu_kernel void @set_inactive_f64(ptr addrspace(1) %out, double %in) {161; GCN-LABEL: set_inactive_f64:162; GCN:       ; %bb.0:163; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24164; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1165; GCN-NEXT:    v_mov_b32_e32 v0, 0xcccccccd166; GCN-NEXT:    v_mov_b32_e32 v1, 0x4010cccc167; GCN-NEXT:    s_mov_b64 exec, s[4:5]168; GCN-NEXT:    s_waitcnt lgkmcnt(0)169; GCN-NEXT:    v_mov_b32_e32 v2, s2170; GCN-NEXT:    v_mov_b32_e32 v3, s3171; GCN-NEXT:    s_or_saveexec_b64 s[2:3], -1172; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[2:3]173; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[2:3]174; GCN-NEXT:    s_mov_b64 exec, s[2:3]175; GCN-NEXT:    v_mov_b32_e32 v2, v0176; GCN-NEXT:    v_mov_b32_e32 v3, v1177; GCN-NEXT:    s_mov_b32 s2, -1178; GCN-NEXT:    s_mov_b32 s3, 0xf000179; GCN-NEXT:    buffer_store_dwordx2 v[2:3], off, s[0:3], 0180; GCN-NEXT:    s_endpgm181  %tmp.0 = call double @llvm.amdgcn.set.inactive.f64(double %in, double 4.2) #0182  %tmp = call double @llvm.amdgcn.strict.wwm.f64(double %tmp.0)183  store double %tmp, ptr addrspace(1) %out184  ret void185}186 187define amdgpu_kernel void @set_inactive_v2i16(ptr addrspace(1) %out, <2 x i16> %in) {188; GCN-LABEL: set_inactive_v2i16:189; GCN:       ; %bb.0:190; GCN-NEXT:    s_load_dword s6, s[4:5], 0x2c191; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24192; GCN-NEXT:    s_or_saveexec_b64 s[2:3], -1193; GCN-NEXT:    v_mov_b32_e32 v0, 0x10001194; GCN-NEXT:    s_mov_b64 exec, s[2:3]195; GCN-NEXT:    s_mov_b32 s2, -1196; GCN-NEXT:    s_waitcnt lgkmcnt(0)197; GCN-NEXT:    v_mov_b32_e32 v1, s6198; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1199; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]200; GCN-NEXT:    s_mov_b64 exec, s[4:5]201; GCN-NEXT:    v_mov_b32_e32 v1, v0202; GCN-NEXT:    s_mov_b32 s3, 0xf000203; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0204; GCN-NEXT:    s_endpgm205  %tmp.0 = call <2 x i16> @llvm.amdgcn.set.inactive.v2i16(<2 x i16> %in, <2 x i16> <i16 1, i16 1>) #0206  %tmp = call <2 x i16> @llvm.amdgcn.strict.wwm.v2i16(<2 x i16> %tmp.0)207  store <2 x i16> %tmp, ptr addrspace(1) %out208  ret void209}210 211define amdgpu_kernel void @set_inactive_v2f16(ptr addrspace(1) %out, <2 x half> %in) {212; GCN-LABEL: set_inactive_v2f16:213; GCN:       ; %bb.0:214; GCN-NEXT:    s_load_dword s6, s[4:5], 0x2c215; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24216; GCN-NEXT:    s_or_saveexec_b64 s[2:3], -1217; GCN-NEXT:    v_mov_b32_e32 v0, 0x3c003c00218; GCN-NEXT:    s_mov_b64 exec, s[2:3]219; GCN-NEXT:    s_mov_b32 s2, -1220; GCN-NEXT:    s_waitcnt lgkmcnt(0)221; GCN-NEXT:    v_mov_b32_e32 v1, s6222; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1223; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]224; GCN-NEXT:    s_mov_b64 exec, s[4:5]225; GCN-NEXT:    v_mov_b32_e32 v1, v0226; GCN-NEXT:    s_mov_b32 s3, 0xf000227; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0228; GCN-NEXT:    s_endpgm229  %tmp.0 = call <2 x half> @llvm.amdgcn.set.inactive.v2f16(<2 x half> %in, <2 x half> <half 1.0, half 1.0>) #0230  %tmp = call <2 x half> @llvm.amdgcn.strict.wwm.v2i16(<2 x half> %tmp.0)231  store <2 x half> %tmp, ptr addrspace(1) %out232  ret void233}234 235define amdgpu_kernel void @set_inactive_v2i32(ptr addrspace(1) %out, <2 x i32> %in) {236; GCN-LABEL: set_inactive_v2i32:237; GCN:       ; %bb.0:238; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24239; GCN-NEXT:    s_waitcnt lgkmcnt(0)240; GCN-NEXT:    v_mov_b32_e32 v2, s2241; GCN-NEXT:    v_mov_b32_e32 v3, s3242; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1243; GCN-NEXT:    s_mov_b32 s2, -1244; GCN-NEXT:    v_cndmask_b32_e64 v0, 1, v2, s[4:5]245; GCN-NEXT:    v_cndmask_b32_e64 v1, 1, v3, s[4:5]246; GCN-NEXT:    s_mov_b64 exec, s[4:5]247; GCN-NEXT:    v_mov_b32_e32 v2, v0248; GCN-NEXT:    v_mov_b32_e32 v3, v1249; GCN-NEXT:    s_mov_b32 s3, 0xf000250; GCN-NEXT:    buffer_store_dwordx2 v[2:3], off, s[0:3], 0251; GCN-NEXT:    s_endpgm252  %tmp.0 = call <2 x i32> @llvm.amdgcn.set.inactive.v2i32(<2 x i32> %in, <2 x i32> <i32 1, i32 1>) #0253  %tmp = call <2 x i32> @llvm.amdgcn.strict.wwm.v2i32(<2 x i32> %tmp.0)254  store <2 x i32> %tmp, ptr addrspace(1) %out255  ret void256}257 258define amdgpu_kernel void @set_inactive_v2f32(ptr addrspace(1) %out, <2 x float> %in) {259; GCN-LABEL: set_inactive_v2f32:260; GCN:       ; %bb.0:261; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24262; GCN-NEXT:    s_waitcnt lgkmcnt(0)263; GCN-NEXT:    v_mov_b32_e32 v2, s2264; GCN-NEXT:    v_mov_b32_e32 v3, s3265; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1266; GCN-NEXT:    s_mov_b32 s2, -1267; GCN-NEXT:    v_cndmask_b32_e64 v0, 1.0, v2, s[4:5]268; GCN-NEXT:    v_cndmask_b32_e64 v1, 1.0, v3, s[4:5]269; GCN-NEXT:    s_mov_b64 exec, s[4:5]270; GCN-NEXT:    v_mov_b32_e32 v2, v0271; GCN-NEXT:    v_mov_b32_e32 v3, v1272; GCN-NEXT:    s_mov_b32 s3, 0xf000273; GCN-NEXT:    buffer_store_dwordx2 v[2:3], off, s[0:3], 0274; GCN-NEXT:    s_endpgm275  %tmp.0 = call <2 x float> @llvm.amdgcn.set.inactive.v2f32(<2 x float> %in, <2 x float> <float 1.0, float 1.0>) #0276  %tmp = call <2 x float> @llvm.amdgcn.strict.wwm.v2f32(<2 x float> %tmp.0)277  store <2 x float> %tmp, ptr addrspace(1) %out278  ret void279}280 281define amdgpu_kernel void @set_inactive_v2bf16(ptr addrspace(1) %out, <2 x bfloat> %in) {282; GCN-LABEL: set_inactive_v2bf16:283; GCN:       ; %bb.0:284; GCN-NEXT:    s_load_dword s6, s[4:5], 0x2c285; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24286; GCN-NEXT:    s_mov_b32 s3, 0xf000287; GCN-NEXT:    s_mov_b32 s2, -1288; GCN-NEXT:    s_waitcnt lgkmcnt(0)289; GCN-NEXT:    v_mov_b32_e32 v1, s6290; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1291; GCN-NEXT:    v_mov_b32_e32 v0, 0x3f803f80292; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]293; GCN-NEXT:    s_mov_b64 exec, s[4:5]294; GCN-NEXT:    v_mov_b32_e32 v1, v0295; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0296; GCN-NEXT:    s_endpgm297  %tmp.0 = call <2 x bfloat> @llvm.amdgcn.set.inactive.v2bf16(<2 x bfloat> %in, <2 x bfloat> <bfloat 1.0, bfloat 1.0>) #0298  %tmp = call <2 x bfloat> @llvm.amdgcn.strict.wwm.v2bf16(<2 x bfloat> %tmp.0)299  store <2 x bfloat> %tmp, ptr addrspace(1) %out300  ret void301}302 303define amdgpu_kernel void @set_inactive_v4i16(ptr addrspace(1) %out, <4 x i16> %in) {304; GCN-LABEL: set_inactive_v4i16:305; GCN:       ; %bb.0:306; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24307; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1308; GCN-NEXT:    v_mov_b32_e32 v0, 0x10001309; GCN-NEXT:    s_mov_b64 exec, s[4:5]310; GCN-NEXT:    s_waitcnt lgkmcnt(0)311; GCN-NEXT:    v_mov_b32_e32 v3, s2312; GCN-NEXT:    v_mov_b32_e32 v4, s3313; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1314; GCN-NEXT:    s_mov_b32 s2, -1315; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v3, s[4:5]316; GCN-NEXT:    v_cndmask_b32_e64 v2, v0, v4, s[4:5]317; GCN-NEXT:    s_mov_b64 exec, s[4:5]318; GCN-NEXT:    v_mov_b32_e32 v3, v1319; GCN-NEXT:    v_mov_b32_e32 v4, v2320; GCN-NEXT:    s_mov_b32 s3, 0xf000321; GCN-NEXT:    buffer_store_dwordx2 v[3:4], off, s[0:3], 0322; GCN-NEXT:    s_endpgm323  %tmp.0 = call <4 x i16> @llvm.amdgcn.set.inactive.v4i16(<4 x i16> %in, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) #0324  %tmp = call <4 x i16> @llvm.amdgcn.strict.wwm.v4i16(<4 x i16> %tmp.0)325  store <4 x i16> %tmp, ptr addrspace(1) %out326  ret void327}328 329define amdgpu_kernel void @set_inactive_v4f16(ptr addrspace(1) %out, <4 x half> %in) {330; GCN-LABEL: set_inactive_v4f16:331; GCN:       ; %bb.0:332; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24333; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1334; GCN-NEXT:    v_mov_b32_e32 v0, 0x3c003c00335; GCN-NEXT:    s_mov_b64 exec, s[4:5]336; GCN-NEXT:    s_waitcnt lgkmcnt(0)337; GCN-NEXT:    v_mov_b32_e32 v3, s2338; GCN-NEXT:    v_mov_b32_e32 v4, s3339; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1340; GCN-NEXT:    s_mov_b32 s2, -1341; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v3, s[4:5]342; GCN-NEXT:    v_cndmask_b32_e64 v2, v0, v4, s[4:5]343; GCN-NEXT:    s_mov_b64 exec, s[4:5]344; GCN-NEXT:    v_mov_b32_e32 v3, v1345; GCN-NEXT:    v_mov_b32_e32 v4, v2346; GCN-NEXT:    s_mov_b32 s3, 0xf000347; GCN-NEXT:    buffer_store_dwordx2 v[3:4], off, s[0:3], 0348; GCN-NEXT:    s_endpgm349  %tmp.0 = call <4 x half> @llvm.amdgcn.set.inactive.v4f16(<4 x half> %in, <4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>) #0350  %tmp = call <4 x half> @llvm.amdgcn.strict.wwm.v4f16(<4 x half> %tmp.0)351  store <4 x half> %tmp, ptr addrspace(1) %out352  ret void353}354 355define amdgpu_kernel void @set_inactive_v4bf16(ptr addrspace(1) %out, <4 x bfloat> %in) {356; GCN-LABEL: set_inactive_v4bf16:357; GCN:       ; %bb.0:358; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24359; GCN-NEXT:    s_mov_b32 s7, 0xf000360; GCN-NEXT:    s_mov_b32 s6, -1361; GCN-NEXT:    s_waitcnt lgkmcnt(0)362; GCN-NEXT:    s_mov_b32 s4, s0363; GCN-NEXT:    s_mov_b32 s5, s1364; GCN-NEXT:    v_mov_b32_e32 v2, s3365; GCN-NEXT:    s_or_saveexec_b64 s[0:1], -1366; GCN-NEXT:    v_mov_b32_e32 v0, 0x3f803f80367; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v2, s[0:1]368; GCN-NEXT:    s_mov_b64 exec, s[0:1]369; GCN-NEXT:    v_mov_b32_e32 v2, s2370; GCN-NEXT:    s_or_saveexec_b64 s[0:1], -1371; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]372; GCN-NEXT:    s_mov_b64 exec, s[0:1]373; GCN-NEXT:    v_mov_b32_e32 v2, v0374; GCN-NEXT:    v_mov_b32_e32 v3, v1375; GCN-NEXT:    buffer_store_dwordx2 v[2:3], off, s[4:7], 0376; GCN-NEXT:    s_endpgm377  %tmp.0 = call <4 x bfloat> @llvm.amdgcn.set.inactive.v4bf16(<4 x bfloat> %in, <4 x bfloat> <bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0>) #0378  %tmp = call <4 x bfloat> @llvm.amdgcn.strict.wwm.v4bf16(<4 x bfloat> %tmp.0)379  store <4 x bfloat> %tmp, ptr addrspace(1) %out380  ret void381}382 383define amdgpu_kernel void @set_inactive_p0(ptr addrspace(1) %out, ptr %in) {384; GCN-LABEL: set_inactive_p0:385; GCN:       ; %bb.0:386; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24387; GCN-NEXT:    s_waitcnt lgkmcnt(0)388; GCN-NEXT:    v_mov_b32_e32 v2, s2389; GCN-NEXT:    v_mov_b32_e32 v3, s3390; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1391; GCN-NEXT:    s_mov_b32 s2, -1392; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v2, s[4:5]393; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v3, s[4:5]394; GCN-NEXT:    s_mov_b64 exec, s[4:5]395; GCN-NEXT:    v_mov_b32_e32 v2, v0396; GCN-NEXT:    v_mov_b32_e32 v3, v1397; GCN-NEXT:    s_mov_b32 s3, 0xf000398; GCN-NEXT:    buffer_store_dwordx2 v[2:3], off, s[0:3], 0399; GCN-NEXT:    s_endpgm400  %tmp.0 = call ptr @llvm.amdgcn.set.inactive.p0(ptr %in, ptr null) #0401  %tmp = call ptr @llvm.amdgcn.strict.wwm.p0(ptr %tmp.0)402  store ptr %tmp, ptr addrspace(1) %out403  ret void404}405 406define amdgpu_kernel void @set_inactive_p2(ptr addrspace(1) %out, ptr addrspace(2) %in) {407; GCN-LABEL: set_inactive_p2:408; GCN:       ; %bb.0:409; GCN-NEXT:    s_load_dword s3, s[4:5], 0x2c410; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24411; GCN-NEXT:    s_mov_b32 s2, -1412; GCN-NEXT:    s_waitcnt lgkmcnt(0)413; GCN-NEXT:    v_mov_b32_e32 v1, s3414; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1415; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v1, s[4:5]416; GCN-NEXT:    s_mov_b64 exec, s[4:5]417; GCN-NEXT:    v_mov_b32_e32 v1, v0418; GCN-NEXT:    s_mov_b32 s3, 0xf000419; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0420; GCN-NEXT:    s_endpgm421  %tmp.0 = call ptr addrspace(2) @llvm.amdgcn.set.inactive.p2(ptr addrspace(2) %in, ptr addrspace(2) null) #0422  %tmp = call ptr addrspace(2) @llvm.amdgcn.strict.wwm.p2(ptr addrspace(2) %tmp.0)423  store ptr addrspace(2) %tmp, ptr addrspace(1) %out424  ret void425}426 427define amdgpu_kernel void @set_inactive_p3(ptr addrspace(1) %out, ptr addrspace(3) %in) {428; GCN-LABEL: set_inactive_p3:429; GCN:       ; %bb.0:430; GCN-NEXT:    s_load_dword s3, s[4:5], 0x2c431; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24432; GCN-NEXT:    s_mov_b32 s2, -1433; GCN-NEXT:    s_waitcnt lgkmcnt(0)434; GCN-NEXT:    v_mov_b32_e32 v1, s3435; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1436; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v1, s[4:5]437; GCN-NEXT:    s_mov_b64 exec, s[4:5]438; GCN-NEXT:    v_mov_b32_e32 v1, v0439; GCN-NEXT:    s_mov_b32 s3, 0xf000440; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0441; GCN-NEXT:    s_endpgm442  %tmp.0 = call ptr addrspace(3) @llvm.amdgcn.set.inactive.p3(ptr addrspace(3) %in, ptr addrspace(3) null) #0443  %tmp = call ptr addrspace(3) @llvm.amdgcn.strict.wwm.p3(ptr addrspace(3) %tmp.0)444  store ptr addrspace(3) %tmp, ptr addrspace(1) %out445  ret void446}447 448define amdgpu_kernel void @set_inactive_p5(ptr addrspace(1) %out, ptr addrspace(5) %in) {449; GCN-LABEL: set_inactive_p5:450; GCN:       ; %bb.0:451; GCN-NEXT:    s_load_dword s3, s[4:5], 0x2c452; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24453; GCN-NEXT:    s_mov_b32 s2, -1454; GCN-NEXT:    s_waitcnt lgkmcnt(0)455; GCN-NEXT:    v_mov_b32_e32 v1, s3456; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1457; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v1, s[4:5]458; GCN-NEXT:    s_mov_b64 exec, s[4:5]459; GCN-NEXT:    v_mov_b32_e32 v1, v0460; GCN-NEXT:    s_mov_b32 s3, 0xf000461; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0462; GCN-NEXT:    s_endpgm463  %tmp.0 = call ptr addrspace(5) @llvm.amdgcn.set.inactive.p5(ptr addrspace(5) %in, ptr addrspace(5) null) #0464  %tmp = call ptr addrspace(5) @llvm.amdgcn.strict.wwm.p5(ptr addrspace(5) %tmp.0)465  store ptr addrspace(5) %tmp, ptr addrspace(1) %out466  ret void467}468 469define amdgpu_kernel void @set_inactive_p6(ptr addrspace(1) %out, ptr addrspace(6) %in) {470; GCN-LABEL: set_inactive_p6:471; GCN:       ; %bb.0:472; GCN-NEXT:    s_load_dword s3, s[4:5], 0x2c473; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24474; GCN-NEXT:    s_mov_b32 s2, -1475; GCN-NEXT:    s_waitcnt lgkmcnt(0)476; GCN-NEXT:    v_mov_b32_e32 v1, s3477; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1478; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v1, s[4:5]479; GCN-NEXT:    s_mov_b64 exec, s[4:5]480; GCN-NEXT:    v_mov_b32_e32 v1, v0481; GCN-NEXT:    s_mov_b32 s3, 0xf000482; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0483; GCN-NEXT:    s_endpgm484  %tmp.0 = call ptr addrspace(6) @llvm.amdgcn.set.inactive.p6(ptr addrspace(6) %in, ptr addrspace(6) null) #0485  %tmp = call ptr addrspace(6) @llvm.amdgcn.strict.wwm.p6(ptr addrspace(6) %tmp.0)486  store ptr addrspace(6) %tmp, ptr addrspace(1) %out487  ret void488}489 490declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0491declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) #0492declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1493declare i64 @llvm.amdgcn.strict.wwm.i64(i64) #1494declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32)495 496attributes #0 = { convergent readnone }497attributes #1 = { convergent nounwind readnone speculatable willreturn }498