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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s7 8define double @v_trig_preop_f64(double %a, i32 %b) {9; GCN-LABEL: v_trig_preop_f64:10; GCN: ; %bb.0:11; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v213; GCN-NEXT: s_setpc_b64 s[30:31]14;15; GFX10PLUS-LABEL: v_trig_preop_f64:16; GFX10PLUS: ; %bb.0:17; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)18; GFX10PLUS-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v219; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]20 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)21 ret double %result22}23 24define double @v_trig_preop_f64_imm(double %a, i32 %b) {25; GCN-LABEL: v_trig_preop_f64_imm:26; GCN: ; %bb.0:27; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)28; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 729; GCN-NEXT: s_setpc_b64 s[30:31]30;31; GFX10PLUS-LABEL: v_trig_preop_f64_imm:32; GFX10PLUS: ; %bb.0:33; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)34; GFX10PLUS-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 735; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]36 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)37 ret double %result38}39 40define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) {41; CI-LABEL: s_trig_preop_f64:42; CI: ; %bb.0:43; CI-NEXT: s_load_dword s2, s[8:9], 0x244; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x045; CI-NEXT: s_add_i32 s12, s12, s1746; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 847; CI-NEXT: s_mov_b32 flat_scratch_lo, s1348; CI-NEXT: s_waitcnt lgkmcnt(0)49; CI-NEXT: v_mov_b32_e32 v0, s250; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v051; CI-NEXT: s_add_u32 s0, s0, 452; CI-NEXT: s_addc_u32 s1, s1, 053; CI-NEXT: v_mov_b32_e32 v3, s154; CI-NEXT: v_mov_b32_e32 v2, s055; CI-NEXT: flat_store_dword v[0:1], v056; CI-NEXT: s_waitcnt vmcnt(0)57; CI-NEXT: flat_store_dword v[2:3], v158; CI-NEXT: s_waitcnt vmcnt(0)59; CI-NEXT: s_endpgm60;61; VI-LABEL: s_trig_preop_f64:62; VI: ; %bb.0:63; VI-NEXT: s_load_dword s2, s[8:9], 0x864; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x065; VI-NEXT: s_add_i32 s12, s12, s1766; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 867; VI-NEXT: s_mov_b32 flat_scratch_lo, s1368; VI-NEXT: s_waitcnt lgkmcnt(0)69; VI-NEXT: v_mov_b32_e32 v0, s270; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v071; VI-NEXT: s_add_u32 s0, s0, 472; VI-NEXT: s_addc_u32 s1, s1, 073; VI-NEXT: v_mov_b32_e32 v3, s174; VI-NEXT: v_mov_b32_e32 v2, s075; VI-NEXT: flat_store_dword v[0:1], v076; VI-NEXT: s_waitcnt vmcnt(0)77; VI-NEXT: flat_store_dword v[2:3], v178; VI-NEXT: s_waitcnt vmcnt(0)79; VI-NEXT: s_endpgm80;81; GFX9-LABEL: s_trig_preop_f64:82; GFX9: ; %bb.0:83; GFX9-NEXT: s_load_dword s2, s[8:9], 0x884; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x085; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s1786; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 087; GFX9-NEXT: s_waitcnt lgkmcnt(0)88; GFX9-NEXT: v_mov_b32_e32 v0, s289; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v090; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1]91; GFX9-NEXT: s_waitcnt vmcnt(0)92; GFX9-NEXT: s_endpgm93;94; GFX10-LABEL: s_trig_preop_f64:95; GFX10: ; %bb.0:96; GFX10-NEXT: s_add_u32 s12, s12, s1797; GFX10-NEXT: s_addc_u32 s13, s13, 098; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s1299; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13100; GFX10-NEXT: s_clause 0x1101; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0102; GFX10-NEXT: s_load_dword s2, s[8:9], 0x8103; GFX10-NEXT: s_waitcnt lgkmcnt(0)104; GFX10-NEXT: v_trig_preop_f64 v[0:1], s[0:1], s2105; GFX10-NEXT: flat_store_dwordx2 v[0:1], v[0:1]106; GFX10-NEXT: s_waitcnt_vscnt null, 0x0107; GFX10-NEXT: s_endpgm108;109; GFX11-LABEL: s_trig_preop_f64:110; GFX11: ; %bb.0:111; GFX11-NEXT: s_clause 0x1112; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0113; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8114; GFX11-NEXT: s_waitcnt lgkmcnt(0)115; GFX11-NEXT: v_trig_preop_f64 v[0:1], s[0:1], s2116; GFX11-NEXT: flat_store_b64 v[0:1], v[0:1] dlc117; GFX11-NEXT: s_waitcnt_vscnt null, 0x0118; GFX11-NEXT: s_endpgm119 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)120 store volatile double %result, ptr poison121 ret void122}123 124define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) {125; CI-LABEL: s_trig_preop_f64_imm:126; CI: ; %bb.0:127; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0128; CI-NEXT: s_add_i32 s12, s12, s17129; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8130; CI-NEXT: s_mov_b32 flat_scratch_lo, s13131; CI-NEXT: s_waitcnt lgkmcnt(0)132; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7133; CI-NEXT: s_add_u32 s0, s0, 4134; CI-NEXT: s_addc_u32 s1, s1, 0135; CI-NEXT: v_mov_b32_e32 v3, s1136; CI-NEXT: v_mov_b32_e32 v2, s0137; CI-NEXT: flat_store_dword v[0:1], v0138; CI-NEXT: s_waitcnt vmcnt(0)139; CI-NEXT: flat_store_dword v[2:3], v1140; CI-NEXT: s_waitcnt vmcnt(0)141; CI-NEXT: s_endpgm142;143; VI-LABEL: s_trig_preop_f64_imm:144; VI: ; %bb.0:145; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0146; VI-NEXT: s_add_i32 s12, s12, s17147; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8148; VI-NEXT: s_mov_b32 flat_scratch_lo, s13149; VI-NEXT: s_waitcnt lgkmcnt(0)150; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7151; VI-NEXT: s_add_u32 s0, s0, 4152; VI-NEXT: s_addc_u32 s1, s1, 0153; VI-NEXT: v_mov_b32_e32 v3, s1154; VI-NEXT: v_mov_b32_e32 v2, s0155; VI-NEXT: flat_store_dword v[0:1], v0156; VI-NEXT: s_waitcnt vmcnt(0)157; VI-NEXT: flat_store_dword v[2:3], v1158; VI-NEXT: s_waitcnt vmcnt(0)159; VI-NEXT: s_endpgm160;161; GFX9-LABEL: s_trig_preop_f64_imm:162; GFX9: ; %bb.0:163; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0164; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17165; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0166; GFX9-NEXT: s_waitcnt lgkmcnt(0)167; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7168; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1]169; GFX9-NEXT: s_waitcnt vmcnt(0)170; GFX9-NEXT: s_endpgm171;172; GFX10-LABEL: s_trig_preop_f64_imm:173; GFX10: ; %bb.0:174; GFX10-NEXT: s_add_u32 s12, s12, s17175; GFX10-NEXT: s_addc_u32 s13, s13, 0176; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12177; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13178; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0179; GFX10-NEXT: s_waitcnt lgkmcnt(0)180; GFX10-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7181; GFX10-NEXT: flat_store_dwordx2 v[0:1], v[0:1]182; GFX10-NEXT: s_waitcnt_vscnt null, 0x0183; GFX10-NEXT: s_endpgm184;185; GFX11-LABEL: s_trig_preop_f64_imm:186; GFX11: ; %bb.0:187; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0188; GFX11-NEXT: s_waitcnt lgkmcnt(0)189; GFX11-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7190; GFX11-NEXT: flat_store_b64 v[0:1], v[0:1] dlc191; GFX11-NEXT: s_waitcnt_vscnt null, 0x0192; GFX11-NEXT: s_endpgm193 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)194 store volatile double %result, ptr poison195 ret void196}197 198declare double @llvm.amdgcn.trig.preop.f64(double, i32) #0199 200attributes #0 = { nounwind readnone speculatable }201