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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefix=GFX906 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11 %s6 7define i32 @v_udot4(i32 %a, i32 %b, i32 %c) {8; GFX906-LABEL: v_udot4:9; GFX906: ; %bb.0:10; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v212; GFX906-NEXT: s_setpc_b64 s[30:31]13;14; GFX10PLUS-LABEL: v_udot4:15; GFX10PLUS: ; %bb.0:16; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v218; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]19 %r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 false)20 ret i32 %r21}22 23define i32 @v_udot4_clamp(i32 %a, i32 %b, i32 %c) {24; GFX906-LABEL: v_udot4_clamp:25; GFX906: ; %bb.0:26; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp28; GFX906-NEXT: s_setpc_b64 s[30:31]29;30; GFX10PLUS-LABEL: v_udot4_clamp:31; GFX10PLUS: ; %bb.0:32; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp34; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]35 %r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 true)36 ret i32 %r37}38 39; FIXME: bitcast should not expand40define i32 @v_udot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) {41; GFX906-LABEL: v_udot4_cast_v4i8:42; GFX906: ; %bb.0:43; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; GFX906-NEXT: v_mov_b32_e32 v10, 845; GFX906-NEXT: v_mov_b32_e32 v9, 0xff46; GFX906-NEXT: v_lshlrev_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_047; GFX906-NEXT: v_and_or_b32 v0, v0, v9, v148; GFX906-NEXT: v_and_b32_e32 v1, 0xff, v249; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v350; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v151; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v252; GFX906-NEXT: v_or3_b32 v0, v0, v1, v253; GFX906-NEXT: v_lshlrev_b32_sdwa v1, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_054; GFX906-NEXT: v_and_b32_e32 v2, 0xff, v655; GFX906-NEXT: v_and_b32_e32 v3, 0xff, v756; GFX906-NEXT: v_and_or_b32 v1, v4, v9, v157; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v258; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v359; GFX906-NEXT: v_or3_b32 v1, v1, v2, v360; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v861; GFX906-NEXT: s_setpc_b64 s[30:31]62;63; GFX10-LABEL: v_udot4_cast_v4i8:64; GFX10: ; %bb.0:65; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)66; GFX10-NEXT: v_mov_b32_e32 v9, 867; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_068; GFX10-NEXT: v_and_or_b32 v0, 0xff, v0, v169; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v270; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v371; GFX10-NEXT: v_lshlrev_b32_sdwa v3, v9, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_072; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v673; GFX10-NEXT: v_and_b32_e32 v6, 0xff, v774; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v175; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v276; GFX10-NEXT: v_and_or_b32 v3, 0xff, v4, v377; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v578; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v679; GFX10-NEXT: v_or3_b32 v0, v0, v1, v280; GFX10-NEXT: v_or3_b32 v1, v3, v4, v581; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v882; GFX10-NEXT: s_setpc_b64 s[30:31]83;84; GFX11-LABEL: v_udot4_cast_v4i8:85; GFX11: ; %bb.0:86; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v188; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v589; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v290; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v391; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v192; GFX11-NEXT: v_lshlrev_b32_e32 v5, 8, v593; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v294; GFX11-NEXT: v_lshlrev_b32_e32 v3, 24, v395; GFX11-NEXT: v_and_or_b32 v0, 0xff, v0, v196; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v697; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v798; GFX11-NEXT: v_and_or_b32 v4, 0xff, v4, v599; GFX11-NEXT: v_or3_b32 v0, v0, v2, v3100; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1101; GFX11-NEXT: v_lshlrev_b32_e32 v5, 24, v6102; GFX11-NEXT: v_or3_b32 v1, v4, v1, v5103; GFX11-NEXT: v_dot4_u32_u8 v0, v0, v1, v8104; GFX11-NEXT: s_setpc_b64 s[30:31]105 %a.cast = bitcast <4 x i8> %a to i32106 %b.cast = bitcast <4 x i8> %b to i32107 %r = call i32 @llvm.amdgcn.udot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)108 ret i32 %r109}110 111define i32 @v_udot4_fnegf32_a(float %a, i32 %b, i32 %c) {112; GFX906-LABEL: v_udot4_fnegf32_a:113; GFX906: ; %bb.0:114; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)115; GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0116; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2117; GFX906-NEXT: s_setpc_b64 s[30:31]118;119; GFX10PLUS-LABEL: v_udot4_fnegf32_a:120; GFX10PLUS: ; %bb.0:121; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80000000, v0123; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2124; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]125 %neg.a = fneg float %a126 %cast.neg.a = bitcast float %neg.a to i32127 %r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)128 ret i32 %r129}130 131define i32 @v_udot4_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {132; GFX906-LABEL: v_udot4_fnegv2f16_a:133; GFX906: ; %bb.0:134; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)135; GFX906-NEXT: v_xor_b32_e32 v0, 0x80008000, v0136; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2137; GFX906-NEXT: s_setpc_b64 s[30:31]138;139; GFX10PLUS-LABEL: v_udot4_fnegv2f16_a:140; GFX10PLUS: ; %bb.0:141; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80008000, v0143; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2144; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]145 %neg.a = fneg <2 x half> %a146 %cast.neg.a = bitcast <2 x half> %neg.a to i32147 %r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)148 ret i32 %r149}150 151declare i32 @llvm.amdgcn.udot4(i32, i32, i32, i1 immarg) #0152 153attributes #0 = { nounwind readnone speculatable }154