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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefix=GFX906 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck --check-prefix=GFX10PLUS %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck --check-prefix=GFX10PLUS %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefix=GFX10PLUS %s6 7define i32 @v_udot8(i32 %a, i32 %b, i32 %c) {8; GFX906-LABEL: v_udot8:9; GFX906: ; %bb.0:10; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v212; GFX906-NEXT: s_setpc_b64 s[30:31]13;14; GFX10PLUS-LABEL: v_udot8:15; GFX10PLUS: ; %bb.0:16; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v218; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]19 %r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 false)20 ret i32 %r21}22 23define i32 @v_udot8_clamp(i32 %a, i32 %b, i32 %c) {24; GFX906-LABEL: v_udot8_clamp:25; GFX906: ; %bb.0:26; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp28; GFX906-NEXT: s_setpc_b64 s[30:31]29;30; GFX10PLUS-LABEL: v_udot8_clamp:31; GFX10PLUS: ; %bb.0:32; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp34; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]35 %r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 true)36 ret i32 %r37}38 39; FIXME: Fix argument do not let these casts expand40; define i32 @v_udot8_cast_v8i4(<8 x i4> %a, <8 x i4> %b, i32 %c) {41; %a.cast = bitcast <8 x i4> %a to i3242; %b.cast = bitcast <8 x i4> %b to i3243; %r = call i32 @llvm.amdgcn.udot8(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)44; ret i32 %r45; }46 47define i32 @v_udot8_fnegf32_a(float %a, i32 %b, i32 %c) {48; GFX906-LABEL: v_udot8_fnegf32_a:49; GFX906: ; %bb.0:50; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v052; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v253; GFX906-NEXT: s_setpc_b64 s[30:31]54;55; GFX10PLUS-LABEL: v_udot8_fnegf32_a:56; GFX10PLUS: ; %bb.0:57; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80000000, v059; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v260; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]61 %neg.a = fneg float %a62 %cast.neg.a = bitcast float %neg.a to i3263 %r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)64 ret i32 %r65}66 67define i32 @v_udot8_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {68; GFX906-LABEL: v_udot8_fnegv2f16_a:69; GFX906: ; %bb.0:70; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)71; GFX906-NEXT: v_xor_b32_e32 v0, 0x80008000, v072; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v273; GFX906-NEXT: s_setpc_b64 s[30:31]74;75; GFX10PLUS-LABEL: v_udot8_fnegv2f16_a:76; GFX10PLUS: ; %bb.0:77; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)78; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80008000, v079; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v280; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]81 %neg.a = fneg <2 x half> %a82 %cast.neg.a = bitcast <2 x half> %neg.a to i3283 %r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)84 ret i32 %r85}86 87declare i32 @llvm.amdgcn.udot8(i32, i32, i32, i1 immarg) #088 89attributes #0 = { nounwind readnone speculatable }90