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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga -amdgpu-dpp-combine=false < %s | FileCheck -check-prefix=GFX8 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-dpp-combine=false < %s | FileCheck -check-prefix=GFX10 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -amdgpu-dpp-combine=false < %s | FileCheck -check-prefix=GFX11 %s5 6define amdgpu_kernel void @dpp_test(ptr addrspace(1) %out, i32 %in1, i32 %in2) {7; GFX8-LABEL: dpp_test:8; GFX8: ; %bb.0:9; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2410; GFX8-NEXT: s_waitcnt lgkmcnt(0)11; GFX8-NEXT: v_mov_b32_e32 v2, s212; GFX8-NEXT: v_mov_b32_e32 v0, s313; GFX8-NEXT: s_nop 114; GFX8-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x115; GFX8-NEXT: v_mov_b32_e32 v0, s016; GFX8-NEXT: v_mov_b32_e32 v1, s117; GFX8-NEXT: flat_store_dword v[0:1], v218; GFX8-NEXT: s_endpgm19;20; GFX10-LABEL: dpp_test:21; GFX10: ; %bb.0:22; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2423; GFX10-NEXT: s_waitcnt lgkmcnt(0)24; GFX10-NEXT: v_mov_b32_e32 v0, s225; GFX10-NEXT: v_mov_b32_e32 v1, s326; GFX10-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x127; GFX10-NEXT: v_mov_b32_e32 v1, 028; GFX10-NEXT: global_store_dword v1, v0, s[0:1]29; GFX10-NEXT: s_endpgm30;31; GFX11-LABEL: dpp_test:32; GFX11: ; %bb.0:33; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2434; GFX11-NEXT: s_waitcnt lgkmcnt(0)35; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s336; GFX11-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x137; GFX11-NEXT: v_mov_b32_e32 v1, 038; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]39; GFX11-NEXT: s_endpgm40 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false)41 store i32 %tmp0, ptr addrspace(1) %out42 ret void43}44define amdgpu_kernel void @update_dppi64_test(ptr addrspace(1) %arg, i64 %in1, i64 %in2) {45; GFX8-LABEL: update_dppi64_test:46; GFX8: ; %bb.0:47; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2448; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v049; GFX8-NEXT: s_waitcnt lgkmcnt(0)50; GFX8-NEXT: v_mov_b32_e32 v0, s051; GFX8-NEXT: v_mov_b32_e32 v1, s152; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v253; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc54; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]55; GFX8-NEXT: v_mov_b32_e32 v4, s256; GFX8-NEXT: v_mov_b32_e32 v5, s357; GFX8-NEXT: s_waitcnt vmcnt(0)58; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x159; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x160; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]61; GFX8-NEXT: s_endpgm62;63; GFX10-LABEL: update_dppi64_test:64; GFX10: ; %bb.0:65; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2466; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v067; GFX10-NEXT: s_waitcnt lgkmcnt(0)68; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]69; GFX10-NEXT: v_mov_b32_e32 v2, s270; GFX10-NEXT: v_mov_b32_e32 v3, s371; GFX10-NEXT: s_waitcnt vmcnt(0)72; GFX10-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x173; GFX10-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x174; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]75; GFX10-NEXT: s_endpgm76;77; GFX11-LABEL: update_dppi64_test:78; GFX11: ; %bb.0:79; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2480; GFX11-NEXT: s_waitcnt lgkmcnt(0)81; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v082; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v083; GFX11-NEXT: v_mov_b32_e32 v2, s284; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]85; GFX11-NEXT: s_waitcnt vmcnt(0)86; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x187; GFX11-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x188; GFX11-NEXT: global_store_b64 v4, v[2:3], s[0:1]89; GFX11-NEXT: s_endpgm90 %id = tail call i32 @llvm.amdgcn.workitem.id.x()91 %gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id92 %load = load i64, ptr addrspace(1) %gep93 %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 1, i32 1, i1 false) #194 store i64 %tmp0, ptr addrspace(1) %gep95 ret void96}97 98define amdgpu_kernel void @update_dppf64_test(ptr addrspace(1) %arg, double %in1, double %in2) {99; GFX8-LABEL: update_dppf64_test:100; GFX8: ; %bb.0:101; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24102; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0103; GFX8-NEXT: s_waitcnt lgkmcnt(0)104; GFX8-NEXT: v_mov_b32_e32 v0, s0105; GFX8-NEXT: v_mov_b32_e32 v1, s1106; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2107; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc108; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]109; GFX8-NEXT: v_mov_b32_e32 v4, s2110; GFX8-NEXT: v_mov_b32_e32 v5, s3111; GFX8-NEXT: s_waitcnt vmcnt(0)112; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1113; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1114; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]115; GFX8-NEXT: s_endpgm116;117; GFX10-LABEL: update_dppf64_test:118; GFX10: ; %bb.0:119; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24120; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0121; GFX10-NEXT: s_waitcnt lgkmcnt(0)122; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]123; GFX10-NEXT: v_mov_b32_e32 v2, s2124; GFX10-NEXT: v_mov_b32_e32 v3, s3125; GFX10-NEXT: s_waitcnt vmcnt(0)126; GFX10-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1127; GFX10-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1128; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]129; GFX10-NEXT: s_endpgm130;131; GFX11-LABEL: update_dppf64_test:132; GFX11: ; %bb.0:133; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24134; GFX11-NEXT: s_waitcnt lgkmcnt(0)135; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0136; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0137; GFX11-NEXT: v_mov_b32_e32 v2, s2138; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]139; GFX11-NEXT: s_waitcnt vmcnt(0)140; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1141; GFX11-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1142; GFX11-NEXT: global_store_b64 v4, v[2:3], s[0:1]143; GFX11-NEXT: s_endpgm144 %id = tail call i32 @llvm.amdgcn.workitem.id.x()145 %gep = getelementptr inbounds double, ptr addrspace(1) %arg, i32 %id146 %load = load double, ptr addrspace(1) %gep147 %tmp0 = call double @llvm.amdgcn.update.dpp.f64(double %in1, double %load, i32 1, i32 1, i32 1, i1 false) #1148 store double %tmp0, ptr addrspace(1) %gep149 ret void150}151 152define amdgpu_kernel void @update_dppv2i32_test(ptr addrspace(1) %arg, <2 x i32> %in1, <2 x i32> %in2) {153; GFX8-LABEL: update_dppv2i32_test:154; GFX8: ; %bb.0:155; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24156; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0157; GFX8-NEXT: s_waitcnt lgkmcnt(0)158; GFX8-NEXT: v_mov_b32_e32 v0, s0159; GFX8-NEXT: v_mov_b32_e32 v1, s1160; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2161; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc162; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]163; GFX8-NEXT: v_mov_b32_e32 v4, s2164; GFX8-NEXT: v_mov_b32_e32 v5, s3165; GFX8-NEXT: s_waitcnt vmcnt(0)166; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1167; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1168; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]169; GFX8-NEXT: s_endpgm170;171; GFX10-LABEL: update_dppv2i32_test:172; GFX10: ; %bb.0:173; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24174; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0175; GFX10-NEXT: s_waitcnt lgkmcnt(0)176; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]177; GFX10-NEXT: v_mov_b32_e32 v2, s2178; GFX10-NEXT: v_mov_b32_e32 v3, s3179; GFX10-NEXT: s_waitcnt vmcnt(0)180; GFX10-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1181; GFX10-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1182; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]183; GFX10-NEXT: s_endpgm184;185; GFX11-LABEL: update_dppv2i32_test:186; GFX11: ; %bb.0:187; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24188; GFX11-NEXT: s_waitcnt lgkmcnt(0)189; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0190; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0191; GFX11-NEXT: v_mov_b32_e32 v2, s2192; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]193; GFX11-NEXT: s_waitcnt vmcnt(0)194; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1195; GFX11-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1196; GFX11-NEXT: global_store_b64 v4, v[2:3], s[0:1]197; GFX11-NEXT: s_endpgm198 %id = tail call i32 @llvm.amdgcn.workitem.id.x()199 %gep = getelementptr inbounds <2 x i32>, ptr addrspace(1) %arg, i32 %id200 %load = load <2 x i32>, ptr addrspace(1) %gep201 %tmp0 = call <2 x i32> @llvm.amdgcn.update.dpp.v2i32(<2 x i32> %in1, <2 x i32> %load, i32 1, i32 1, i32 1, i1 false) #1202 store <2 x i32> %tmp0, ptr addrspace(1) %gep203 ret void204}205 206define amdgpu_kernel void @update_dppv2f32_test(ptr addrspace(1) %arg, <2 x float> %in1, <2 x float> %in2) {207; GFX8-LABEL: update_dppv2f32_test:208; GFX8: ; %bb.0:209; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24210; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0211; GFX8-NEXT: s_waitcnt lgkmcnt(0)212; GFX8-NEXT: v_mov_b32_e32 v0, s0213; GFX8-NEXT: v_mov_b32_e32 v1, s1214; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2215; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc216; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]217; GFX8-NEXT: v_mov_b32_e32 v4, s2218; GFX8-NEXT: v_mov_b32_e32 v5, s3219; GFX8-NEXT: s_waitcnt vmcnt(0)220; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1221; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1222; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]223; GFX8-NEXT: s_endpgm224;225; GFX10-LABEL: update_dppv2f32_test:226; GFX10: ; %bb.0:227; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24228; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0229; GFX10-NEXT: s_waitcnt lgkmcnt(0)230; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]231; GFX10-NEXT: v_mov_b32_e32 v2, s2232; GFX10-NEXT: v_mov_b32_e32 v3, s3233; GFX10-NEXT: s_waitcnt vmcnt(0)234; GFX10-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1235; GFX10-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1236; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]237; GFX10-NEXT: s_endpgm238;239; GFX11-LABEL: update_dppv2f32_test:240; GFX11: ; %bb.0:241; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24242; GFX11-NEXT: s_waitcnt lgkmcnt(0)243; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0244; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0245; GFX11-NEXT: v_mov_b32_e32 v2, s2246; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]247; GFX11-NEXT: s_waitcnt vmcnt(0)248; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1249; GFX11-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1250; GFX11-NEXT: global_store_b64 v4, v[2:3], s[0:1]251; GFX11-NEXT: s_endpgm252 %id = tail call i32 @llvm.amdgcn.workitem.id.x()253 %gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %arg, i32 %id254 %load = load <2 x float>, ptr addrspace(1) %gep255 %tmp0 = call <2 x float> @llvm.amdgcn.update.dpp.v2f32(<2 x float> %in1, <2 x float> %load, i32 1, i32 1, i32 1, i1 false) #1256 store <2 x float> %tmp0, ptr addrspace(1) %gep257 ret void258}259 260define amdgpu_kernel void @update_dpp_p0_test(ptr addrspace(1) %arg, ptr %in1, ptr %in2) {261; GFX8-LABEL: update_dpp_p0_test:262; GFX8: ; %bb.0:263; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24264; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0265; GFX8-NEXT: s_waitcnt lgkmcnt(0)266; GFX8-NEXT: v_mov_b32_e32 v0, s0267; GFX8-NEXT: v_mov_b32_e32 v1, s1268; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2269; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc270; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]271; GFX8-NEXT: v_mov_b32_e32 v4, s2272; GFX8-NEXT: v_mov_b32_e32 v5, s3273; GFX8-NEXT: s_waitcnt vmcnt(0)274; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1275; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1276; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]277; GFX8-NEXT: s_endpgm278;279; GFX10-LABEL: update_dpp_p0_test:280; GFX10: ; %bb.0:281; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24282; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0283; GFX10-NEXT: s_waitcnt lgkmcnt(0)284; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]285; GFX10-NEXT: v_mov_b32_e32 v2, s2286; GFX10-NEXT: v_mov_b32_e32 v3, s3287; GFX10-NEXT: s_waitcnt vmcnt(0)288; GFX10-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1289; GFX10-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1290; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]291; GFX10-NEXT: s_endpgm292;293; GFX11-LABEL: update_dpp_p0_test:294; GFX11: ; %bb.0:295; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24296; GFX11-NEXT: s_waitcnt lgkmcnt(0)297; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_and_b32 v0, 0x3ff, v0298; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0299; GFX11-NEXT: v_mov_b32_e32 v2, s2300; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]301; GFX11-NEXT: s_waitcnt vmcnt(0)302; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1303; GFX11-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1304; GFX11-NEXT: global_store_b64 v4, v[2:3], s[0:1]305; GFX11-NEXT: s_endpgm306 %id = tail call i32 @llvm.amdgcn.workitem.id.x()307 %gep = getelementptr inbounds ptr, ptr addrspace(1) %arg, i32 %id308 %load = load ptr, ptr addrspace(1) %gep309 %tmp0 = call ptr @llvm.amdgcn.update.dpp.v2f32(ptr %in1, ptr %load, i32 1, i32 1, i32 1, i1 false) #1310 store ptr %tmp0, ptr addrspace(1) %gep311 ret void312}313 314define amdgpu_kernel void @update_dpp_p3_test(ptr addrspace(3) %arg, ptr addrspace(3) %in1, ptr %in2) {315; GFX8-LABEL: update_dpp_p3_test:316; GFX8: ; %bb.0:317; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24318; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0319; GFX8-NEXT: s_mov_b32 m0, -1320; GFX8-NEXT: s_waitcnt lgkmcnt(0)321; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0322; GFX8-NEXT: ds_read_b32 v1, v0323; GFX8-NEXT: v_mov_b32_e32 v2, s1324; GFX8-NEXT: s_waitcnt lgkmcnt(0)325; GFX8-NEXT: s_nop 0326; GFX8-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1327; GFX8-NEXT: ds_write_b32 v0, v2328; GFX8-NEXT: s_endpgm329;330; GFX10-LABEL: update_dpp_p3_test:331; GFX10: ; %bb.0:332; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24333; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0334; GFX10-NEXT: s_waitcnt lgkmcnt(0)335; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0336; GFX10-NEXT: v_mov_b32_e32 v2, s1337; GFX10-NEXT: ds_read_b32 v1, v0338; GFX10-NEXT: s_waitcnt lgkmcnt(0)339; GFX10-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1340; GFX10-NEXT: ds_write_b32 v0, v2341; GFX10-NEXT: s_endpgm342;343; GFX11-LABEL: update_dpp_p3_test:344; GFX11: ; %bb.0:345; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24346; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0347; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0348; GFX11-NEXT: s_waitcnt lgkmcnt(0)349; GFX11-NEXT: v_add_nc_u32_e32 v0, s0, v0350; GFX11-NEXT: v_mov_b32_e32 v2, s1351; GFX11-NEXT: ds_load_b32 v1, v0352; GFX11-NEXT: s_waitcnt lgkmcnt(0)353; GFX11-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1354; GFX11-NEXT: ds_store_b32 v0, v2355; GFX11-NEXT: s_endpgm356 %id = tail call i32 @llvm.amdgcn.workitem.id.x()357 %gep = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %arg, i32 %id358 %load = load ptr addrspace(3), ptr addrspace(3) %gep359 %tmp0 = call ptr addrspace(3) @llvm.amdgcn.update.dpp.p3(ptr addrspace(3) %in1, ptr addrspace(3) %load, i32 1, i32 1, i32 1, i1 false) #1360 store ptr addrspace(3) %tmp0, ptr addrspace(3) %gep361 ret void362}363 364define amdgpu_kernel void @update_dpp_p5_test(ptr addrspace(5) %arg, ptr addrspace(5) %in1, ptr %in2) {365; GFX8-LABEL: update_dpp_p5_test:366; GFX8: ; %bb.0:367; GFX8-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0368; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24369; GFX8-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1370; GFX8-NEXT: s_mov_b32 s90, -1371; GFX8-NEXT: s_mov_b32 s91, 0xe80000372; GFX8-NEXT: s_add_u32 s88, s88, s11373; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0374; GFX8-NEXT: s_addc_u32 s89, s89, 0375; GFX8-NEXT: s_waitcnt lgkmcnt(0)376; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0377; GFX8-NEXT: buffer_load_dword v1, v0, s[88:91], 0 offen378; GFX8-NEXT: v_mov_b32_e32 v2, s1379; GFX8-NEXT: s_waitcnt vmcnt(0)380; GFX8-NEXT: s_nop 0381; GFX8-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1382; GFX8-NEXT: buffer_store_dword v2, v0, s[88:91], 0 offen383; GFX8-NEXT: s_endpgm384;385; GFX10-LABEL: update_dpp_p5_test:386; GFX10: ; %bb.0:387; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24388; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0389; GFX10-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0390; GFX10-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1391; GFX10-NEXT: s_mov_b32 s14, -1392; GFX10-NEXT: s_mov_b32 s15, 0x31c16000393; GFX10-NEXT: s_add_u32 s12, s12, s11394; GFX10-NEXT: s_addc_u32 s13, s13, 0395; GFX10-NEXT: s_waitcnt lgkmcnt(0)396; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0397; GFX10-NEXT: v_mov_b32_e32 v2, s1398; GFX10-NEXT: buffer_load_dword v1, v0, s[12:15], 0 offen399; GFX10-NEXT: s_waitcnt vmcnt(0)400; GFX10-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1401; GFX10-NEXT: buffer_store_dword v2, v0, s[12:15], 0 offen402; GFX10-NEXT: s_endpgm403;404; GFX11-LABEL: update_dpp_p5_test:405; GFX11: ; %bb.0:406; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24407; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0408; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0409; GFX11-NEXT: s_waitcnt lgkmcnt(0)410; GFX11-NEXT: v_add_nc_u32_e32 v0, s0, v0411; GFX11-NEXT: v_mov_b32_e32 v2, s1412; GFX11-NEXT: scratch_load_b32 v1, v0, off413; GFX11-NEXT: s_waitcnt vmcnt(0)414; GFX11-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1415; GFX11-NEXT: scratch_store_b32 v0, v2, off416; GFX11-NEXT: s_endpgm417 %id = tail call i32 @llvm.amdgcn.workitem.id.x()418 %gep = getelementptr inbounds ptr addrspace(5), ptr addrspace(5) %arg, i32 %id419 %load = load ptr addrspace(5), ptr addrspace(5) %gep420 %tmp0 = call ptr addrspace(5) @llvm.amdgcn.update.dpp.p5(ptr addrspace(5) %in1, ptr addrspace(5) %load, i32 1, i32 1, i32 1, i1 false) #1421 store ptr addrspace(5) %tmp0, ptr addrspace(5) %gep422 ret void423}424 425declare i32 @llvm.amdgcn.workitem.id.x() #0426declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #1427declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #1428 429attributes #0 = { nounwind readnone speculatable }430attributes #1 = { convergent nounwind readnone }431