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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10-32 %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=GFX10-64 %s6 7define amdgpu_ps void @static_exact(float %arg0, float %arg1) {8; SI-LABEL: static_exact:9; SI: ; %bb.0: ; %.entry10; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v011; SI-NEXT: s_andn2_b64 exec, exec, exec12; SI-NEXT: s_cbranch_scc0 .LBB0_213; SI-NEXT: ; %bb.1: ; %.entry14; SI-NEXT: s_mov_b64 exec, 015; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc16; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm17; SI-NEXT: s_endpgm18; SI-NEXT: .LBB0_2:19; SI-NEXT: s_mov_b64 exec, 020; SI-NEXT: exp null off, off, off, off done vm21; SI-NEXT: s_endpgm22;23; GFX9-LABEL: static_exact:24; GFX9: ; %bb.0: ; %.entry25; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v026; GFX9-NEXT: s_andn2_b64 exec, exec, exec27; GFX9-NEXT: s_cbranch_scc0 .LBB0_228; GFX9-NEXT: ; %bb.1: ; %.entry29; GFX9-NEXT: s_mov_b64 exec, 030; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc31; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm32; GFX9-NEXT: s_endpgm33; GFX9-NEXT: .LBB0_2:34; GFX9-NEXT: s_mov_b64 exec, 035; GFX9-NEXT: exp null off, off, off, off done vm36; GFX9-NEXT: s_endpgm37;38; GFX10-32-LABEL: static_exact:39; GFX10-32: ; %bb.0: ; %.entry40; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v041; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo42; GFX10-32-NEXT: s_cbranch_scc0 .LBB0_243; GFX10-32-NEXT: ; %bb.1: ; %.entry44; GFX10-32-NEXT: s_mov_b32 exec_lo, 045; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo46; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm47; GFX10-32-NEXT: s_endpgm48; GFX10-32-NEXT: .LBB0_2:49; GFX10-32-NEXT: s_mov_b32 exec_lo, 050; GFX10-32-NEXT: exp null off, off, off, off done vm51; GFX10-32-NEXT: s_endpgm52;53; GFX10-64-LABEL: static_exact:54; GFX10-64: ; %bb.0: ; %.entry55; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v056; GFX10-64-NEXT: s_andn2_b64 exec, exec, exec57; GFX10-64-NEXT: s_cbranch_scc0 .LBB0_258; GFX10-64-NEXT: ; %bb.1: ; %.entry59; GFX10-64-NEXT: s_mov_b64 exec, 060; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc61; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm62; GFX10-64-NEXT: s_endpgm63; GFX10-64-NEXT: .LBB0_2:64; GFX10-64-NEXT: s_mov_b64 exec, 065; GFX10-64-NEXT: exp null off, off, off, off done vm66; GFX10-64-NEXT: s_endpgm67.entry:68 %c0 = fcmp olt float %arg0, 0.000000e+0069 %c1 = fcmp oge float %arg1, 0.070 call void @llvm.amdgcn.wqm.demote(i1 false)71 %tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+0072 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #073 ret void74}75 76define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) {77; SI-LABEL: dynamic_exact:78; SI: ; %bb.0: ; %.entry79; SI-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v180; SI-NEXT: s_mov_b64 s[2:3], exec81; SI-NEXT: s_andn2_b64 s[0:1], exec, s[0:1]82; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]83; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v084; SI-NEXT: s_cbranch_scc0 .LBB1_285; SI-NEXT: ; %bb.1: ; %.entry86; SI-NEXT: s_and_b64 exec, exec, s[2:3]87; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc88; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm89; SI-NEXT: s_endpgm90; SI-NEXT: .LBB1_2:91; SI-NEXT: s_mov_b64 exec, 092; SI-NEXT: exp null off, off, off, off done vm93; SI-NEXT: s_endpgm94;95; GFX9-LABEL: dynamic_exact:96; GFX9: ; %bb.0: ; %.entry97; GFX9-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v198; GFX9-NEXT: s_mov_b64 s[2:3], exec99; GFX9-NEXT: s_andn2_b64 s[0:1], exec, s[0:1]100; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]101; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0102; GFX9-NEXT: s_cbranch_scc0 .LBB1_2103; GFX9-NEXT: ; %bb.1: ; %.entry104; GFX9-NEXT: s_and_b64 exec, exec, s[2:3]105; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc106; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm107; GFX9-NEXT: s_endpgm108; GFX9-NEXT: .LBB1_2:109; GFX9-NEXT: s_mov_b64 exec, 0110; GFX9-NEXT: exp null off, off, off, off done vm111; GFX9-NEXT: s_endpgm112;113; GFX10-32-LABEL: dynamic_exact:114; GFX10-32: ; %bb.0: ; %.entry115; GFX10-32-NEXT: v_cmp_le_f32_e64 s0, 0, v1116; GFX10-32-NEXT: s_mov_b32 s1, exec_lo117; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0118; GFX10-32-NEXT: s_andn2_b32 s0, exec_lo, s0119; GFX10-32-NEXT: s_andn2_b32 s1, s1, s0120; GFX10-32-NEXT: s_cbranch_scc0 .LBB1_2121; GFX10-32-NEXT: ; %bb.1: ; %.entry122; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s1123; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo124; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm125; GFX10-32-NEXT: s_endpgm126; GFX10-32-NEXT: .LBB1_2:127; GFX10-32-NEXT: s_mov_b32 exec_lo, 0128; GFX10-32-NEXT: exp null off, off, off, off done vm129; GFX10-32-NEXT: s_endpgm130;131; GFX10-64-LABEL: dynamic_exact:132; GFX10-64: ; %bb.0: ; %.entry133; GFX10-64-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1134; GFX10-64-NEXT: s_mov_b64 s[2:3], exec135; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0136; GFX10-64-NEXT: s_andn2_b64 s[0:1], exec, s[0:1]137; GFX10-64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]138; GFX10-64-NEXT: s_cbranch_scc0 .LBB1_2139; GFX10-64-NEXT: ; %bb.1: ; %.entry140; GFX10-64-NEXT: s_and_b64 exec, exec, s[2:3]141; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc142; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm143; GFX10-64-NEXT: s_endpgm144; GFX10-64-NEXT: .LBB1_2:145; GFX10-64-NEXT: s_mov_b64 exec, 0146; GFX10-64-NEXT: exp null off, off, off, off done vm147; GFX10-64-NEXT: s_endpgm148.entry:149 %c0 = fcmp olt float %arg0, 0.000000e+00150 %c1 = fcmp oge float %arg1, 0.0151 call void @llvm.amdgcn.wqm.demote(i1 %c1)152 %tmp1 = select i1 %c0, float 1.000000e+00, float 0.000000e+00153 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0154 ret void155}156 157define amdgpu_ps void @branch(float %arg0, float %arg1) {158; SI-LABEL: branch:159; SI: ; %bb.0: ; %.entry160; SI-NEXT: v_cvt_i32_f32_e32 v0, v0161; SI-NEXT: v_cvt_i32_f32_e32 v1, v1162; SI-NEXT: s_mov_b64 s[0:1], exec163; SI-NEXT: v_or_b32_e32 v0, v0, v1164; SI-NEXT: v_and_b32_e32 v0, 1, v0165; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0166; SI-NEXT: s_xor_b64 s[2:3], vcc, -1167; SI-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]168; SI-NEXT: s_xor_b64 s[2:3], exec, s[4:5]169; SI-NEXT: s_cbranch_execz .LBB2_3170; SI-NEXT: ; %bb.1: ; %.demote171; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec172; SI-NEXT: s_cbranch_scc0 .LBB2_4173; SI-NEXT: ; %bb.2: ; %.demote174; SI-NEXT: s_mov_b64 exec, 0175; SI-NEXT: .LBB2_3: ; %.continue176; SI-NEXT: s_or_b64 exec, exec, s[2:3]177; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc178; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm179; SI-NEXT: s_endpgm180; SI-NEXT: .LBB2_4:181; SI-NEXT: s_mov_b64 exec, 0182; SI-NEXT: exp null off, off, off, off done vm183; SI-NEXT: s_endpgm184;185; GFX9-LABEL: branch:186; GFX9: ; %bb.0: ; %.entry187; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0188; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1189; GFX9-NEXT: s_mov_b64 s[0:1], exec190; GFX9-NEXT: v_or_b32_e32 v0, v0, v1191; GFX9-NEXT: v_and_b32_e32 v0, 1, v0192; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0193; GFX9-NEXT: s_xor_b64 s[2:3], vcc, -1194; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]195; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5]196; GFX9-NEXT: s_cbranch_execz .LBB2_3197; GFX9-NEXT: ; %bb.1: ; %.demote198; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec199; GFX9-NEXT: s_cbranch_scc0 .LBB2_4200; GFX9-NEXT: ; %bb.2: ; %.demote201; GFX9-NEXT: s_mov_b64 exec, 0202; GFX9-NEXT: .LBB2_3: ; %.continue203; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]204; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc205; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm206; GFX9-NEXT: s_endpgm207; GFX9-NEXT: .LBB2_4:208; GFX9-NEXT: s_mov_b64 exec, 0209; GFX9-NEXT: exp null off, off, off, off done vm210; GFX9-NEXT: s_endpgm211;212; GFX10-32-LABEL: branch:213; GFX10-32: ; %bb.0: ; %.entry214; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0215; GFX10-32-NEXT: v_cvt_i32_f32_e32 v1, v1216; GFX10-32-NEXT: s_mov_b32 s0, exec_lo217; GFX10-32-NEXT: v_or_b32_e32 v0, v0, v1218; GFX10-32-NEXT: v_and_b32_e32 v0, 1, v0219; GFX10-32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0220; GFX10-32-NEXT: s_xor_b32 s1, vcc_lo, -1221; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1222; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2223; GFX10-32-NEXT: s_cbranch_execz .LBB2_3224; GFX10-32-NEXT: ; %bb.1: ; %.demote225; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo226; GFX10-32-NEXT: s_cbranch_scc0 .LBB2_4227; GFX10-32-NEXT: ; %bb.2: ; %.demote228; GFX10-32-NEXT: s_mov_b32 exec_lo, 0229; GFX10-32-NEXT: .LBB2_3: ; %.continue230; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1231; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo232; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm233; GFX10-32-NEXT: s_endpgm234; GFX10-32-NEXT: .LBB2_4:235; GFX10-32-NEXT: s_mov_b32 exec_lo, 0236; GFX10-32-NEXT: exp null off, off, off, off done vm237; GFX10-32-NEXT: s_endpgm238;239; GFX10-64-LABEL: branch:240; GFX10-64: ; %bb.0: ; %.entry241; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0242; GFX10-64-NEXT: v_cvt_i32_f32_e32 v1, v1243; GFX10-64-NEXT: s_mov_b64 s[0:1], exec244; GFX10-64-NEXT: v_or_b32_e32 v0, v0, v1245; GFX10-64-NEXT: v_and_b32_e32 v0, 1, v0246; GFX10-64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0247; GFX10-64-NEXT: s_xor_b64 s[2:3], vcc, -1248; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]249; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5]250; GFX10-64-NEXT: s_cbranch_execz .LBB2_3251; GFX10-64-NEXT: ; %bb.1: ; %.demote252; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec253; GFX10-64-NEXT: s_cbranch_scc0 .LBB2_4254; GFX10-64-NEXT: ; %bb.2: ; %.demote255; GFX10-64-NEXT: s_mov_b64 exec, 0256; GFX10-64-NEXT: .LBB2_3: ; %.continue257; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]258; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc259; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm260; GFX10-64-NEXT: s_endpgm261; GFX10-64-NEXT: .LBB2_4:262; GFX10-64-NEXT: s_mov_b64 exec, 0263; GFX10-64-NEXT: exp null off, off, off, off done vm264; GFX10-64-NEXT: s_endpgm265.entry:266 %i0 = fptosi float %arg0 to i32267 %i1 = fptosi float %arg1 to i32268 %c0 = or i32 %i0, %i1269 %c1 = and i32 %c0, 1270 %c2 = icmp eq i32 %c1, 0271 br i1 %c2, label %.continue, label %.demote272 273.demote:274 call void @llvm.amdgcn.wqm.demote(i1 false)275 br label %.continue276 277.continue:278 %tmp1 = select i1 %c2, float 1.000000e+00, float 0.000000e+00279 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0280 ret void281}282 283define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) {284; SI-LABEL: wqm_demote_1:285; SI: ; %bb.0: ; %.entry286; SI-NEXT: s_mov_b64 s[12:13], exec287; SI-NEXT: s_wqm_b64 exec, exec288; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1289; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc290; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15]291; SI-NEXT: s_cbranch_execz .LBB3_3292; SI-NEXT: ; %bb.1: ; %.demote293; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec294; SI-NEXT: s_cbranch_scc0 .LBB3_4295; SI-NEXT: ; %bb.2: ; %.demote296; SI-NEXT: s_wqm_b64 s[16:17], s[12:13]297; SI-NEXT: s_and_b64 exec, exec, s[16:17]298; SI-NEXT: .LBB3_3: ; %.continue299; SI-NEXT: s_or_b64 exec, exec, s[14:15]300; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf301; SI-NEXT: s_waitcnt vmcnt(0)302; SI-NEXT: v_add_f32_e32 v0, v0, v0303; SI-NEXT: s_and_b64 exec, exec, s[12:13]304; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf305; SI-NEXT: s_waitcnt vmcnt(0)306; SI-NEXT: s_branch .LBB3_5307; SI-NEXT: .LBB3_4:308; SI-NEXT: s_mov_b64 exec, 0309; SI-NEXT: exp null off, off, off, off done vm310; SI-NEXT: s_endpgm311; SI-NEXT: .LBB3_5:312;313; GFX9-LABEL: wqm_demote_1:314; GFX9: ; %bb.0: ; %.entry315; GFX9-NEXT: s_mov_b64 s[12:13], exec316; GFX9-NEXT: s_wqm_b64 exec, exec317; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1318; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc319; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15]320; GFX9-NEXT: s_cbranch_execz .LBB3_3321; GFX9-NEXT: ; %bb.1: ; %.demote322; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec323; GFX9-NEXT: s_cbranch_scc0 .LBB3_4324; GFX9-NEXT: ; %bb.2: ; %.demote325; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13]326; GFX9-NEXT: s_and_b64 exec, exec, s[16:17]327; GFX9-NEXT: .LBB3_3: ; %.continue328; GFX9-NEXT: s_or_b64 exec, exec, s[14:15]329; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf330; GFX9-NEXT: s_waitcnt vmcnt(0)331; GFX9-NEXT: v_add_f32_e32 v0, v0, v0332; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]333; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf334; GFX9-NEXT: s_waitcnt vmcnt(0)335; GFX9-NEXT: s_branch .LBB3_5336; GFX9-NEXT: .LBB3_4:337; GFX9-NEXT: s_mov_b64 exec, 0338; GFX9-NEXT: exp null off, off, off, off done vm339; GFX9-NEXT: s_endpgm340; GFX9-NEXT: .LBB3_5:341;342; GFX10-32-LABEL: wqm_demote_1:343; GFX10-32: ; %bb.0: ; %.entry344; GFX10-32-NEXT: s_mov_b32 s12, exec_lo345; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo346; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1347; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo348; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13349; GFX10-32-NEXT: s_cbranch_execz .LBB3_3350; GFX10-32-NEXT: ; %bb.1: ; %.demote351; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo352; GFX10-32-NEXT: s_cbranch_scc0 .LBB3_4353; GFX10-32-NEXT: ; %bb.2: ; %.demote354; GFX10-32-NEXT: s_wqm_b32 s14, s12355; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14356; GFX10-32-NEXT: .LBB3_3: ; %.continue357; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13358; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D359; GFX10-32-NEXT: s_waitcnt vmcnt(0)360; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0361; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12362; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D363; GFX10-32-NEXT: s_waitcnt vmcnt(0)364; GFX10-32-NEXT: s_branch .LBB3_5365; GFX10-32-NEXT: .LBB3_4:366; GFX10-32-NEXT: s_mov_b32 exec_lo, 0367; GFX10-32-NEXT: exp null off, off, off, off done vm368; GFX10-32-NEXT: s_endpgm369; GFX10-32-NEXT: .LBB3_5:370;371; GFX10-64-LABEL: wqm_demote_1:372; GFX10-64: ; %bb.0: ; %.entry373; GFX10-64-NEXT: s_mov_b64 s[12:13], exec374; GFX10-64-NEXT: s_wqm_b64 exec, exec375; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1376; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc377; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15]378; GFX10-64-NEXT: s_cbranch_execz .LBB3_3379; GFX10-64-NEXT: ; %bb.1: ; %.demote380; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec381; GFX10-64-NEXT: s_cbranch_scc0 .LBB3_4382; GFX10-64-NEXT: ; %bb.2: ; %.demote383; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13]384; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17]385; GFX10-64-NEXT: .LBB3_3: ; %.continue386; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15]387; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D388; GFX10-64-NEXT: s_waitcnt vmcnt(0)389; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0390; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]391; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D392; GFX10-64-NEXT: s_waitcnt vmcnt(0)393; GFX10-64-NEXT: s_branch .LBB3_5394; GFX10-64-NEXT: .LBB3_4:395; GFX10-64-NEXT: s_mov_b64 exec, 0396; GFX10-64-NEXT: exp null off, off, off, off done vm397; GFX10-64-NEXT: s_endpgm398; GFX10-64-NEXT: .LBB3_5:399.entry:400 %z.cmp = fcmp olt float %z, 0.0401 br i1 %z.cmp, label %.continue, label %.demote402 403.demote:404 call void @llvm.amdgcn.wqm.demote(i1 false)405 br label %.continue406 407.continue:408 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0409 %tex0 = extractelement <4 x float> %tex, i32 0410 %tex1 = extractelement <4 x float> %tex, i32 0411 %coord1 = fadd float %tex0, %tex1412 %rtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord1, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0413 414 ret <4 x float> %rtex415}416 417define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) {418; SI-LABEL: wqm_demote_2:419; SI: ; %bb.0: ; %.entry420; SI-NEXT: s_mov_b64 s[12:13], exec421; SI-NEXT: s_wqm_b64 exec, exec422; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf423; SI-NEXT: s_waitcnt vmcnt(0)424; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0425; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc426; SI-NEXT: s_xor_b64 s[14:15], exec, s[14:15]427; SI-NEXT: s_cbranch_execz .LBB4_3428; SI-NEXT: ; %bb.1: ; %.demote429; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], exec430; SI-NEXT: s_cbranch_scc0 .LBB4_4431; SI-NEXT: ; %bb.2: ; %.demote432; SI-NEXT: s_wqm_b64 s[16:17], s[12:13]433; SI-NEXT: s_and_b64 exec, exec, s[16:17]434; SI-NEXT: .LBB4_3: ; %.continue435; SI-NEXT: s_or_b64 exec, exec, s[14:15]436; SI-NEXT: v_add_f32_e32 v0, v0, v0437; SI-NEXT: s_and_b64 exec, exec, s[12:13]438; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf439; SI-NEXT: s_waitcnt vmcnt(0)440; SI-NEXT: s_branch .LBB4_5441; SI-NEXT: .LBB4_4:442; SI-NEXT: s_mov_b64 exec, 0443; SI-NEXT: exp null off, off, off, off done vm444; SI-NEXT: s_endpgm445; SI-NEXT: .LBB4_5:446;447; GFX9-LABEL: wqm_demote_2:448; GFX9: ; %bb.0: ; %.entry449; GFX9-NEXT: s_mov_b64 s[12:13], exec450; GFX9-NEXT: s_wqm_b64 exec, exec451; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf452; GFX9-NEXT: s_waitcnt vmcnt(0)453; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0454; GFX9-NEXT: s_and_saveexec_b64 s[14:15], vcc455; GFX9-NEXT: s_xor_b64 s[14:15], exec, s[14:15]456; GFX9-NEXT: s_cbranch_execz .LBB4_3457; GFX9-NEXT: ; %bb.1: ; %.demote458; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], exec459; GFX9-NEXT: s_cbranch_scc0 .LBB4_4460; GFX9-NEXT: ; %bb.2: ; %.demote461; GFX9-NEXT: s_wqm_b64 s[16:17], s[12:13]462; GFX9-NEXT: s_and_b64 exec, exec, s[16:17]463; GFX9-NEXT: .LBB4_3: ; %.continue464; GFX9-NEXT: s_or_b64 exec, exec, s[14:15]465; GFX9-NEXT: v_add_f32_e32 v0, v0, v0466; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]467; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf468; GFX9-NEXT: s_waitcnt vmcnt(0)469; GFX9-NEXT: s_branch .LBB4_5470; GFX9-NEXT: .LBB4_4:471; GFX9-NEXT: s_mov_b64 exec, 0472; GFX9-NEXT: exp null off, off, off, off done vm473; GFX9-NEXT: s_endpgm474; GFX9-NEXT: .LBB4_5:475;476; GFX10-32-LABEL: wqm_demote_2:477; GFX10-32: ; %bb.0: ; %.entry478; GFX10-32-NEXT: s_mov_b32 s12, exec_lo479; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo480; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D481; GFX10-32-NEXT: s_waitcnt vmcnt(0)482; GFX10-32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0483; GFX10-32-NEXT: s_and_saveexec_b32 s13, vcc_lo484; GFX10-32-NEXT: s_xor_b32 s13, exec_lo, s13485; GFX10-32-NEXT: s_cbranch_execz .LBB4_3486; GFX10-32-NEXT: ; %bb.1: ; %.demote487; GFX10-32-NEXT: s_andn2_b32 s12, s12, exec_lo488; GFX10-32-NEXT: s_cbranch_scc0 .LBB4_4489; GFX10-32-NEXT: ; %bb.2: ; %.demote490; GFX10-32-NEXT: s_wqm_b32 s14, s12491; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s14492; GFX10-32-NEXT: .LBB4_3: ; %.continue493; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s13494; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0495; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12496; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D497; GFX10-32-NEXT: s_waitcnt vmcnt(0)498; GFX10-32-NEXT: s_branch .LBB4_5499; GFX10-32-NEXT: .LBB4_4:500; GFX10-32-NEXT: s_mov_b32 exec_lo, 0501; GFX10-32-NEXT: exp null off, off, off, off done vm502; GFX10-32-NEXT: s_endpgm503; GFX10-32-NEXT: .LBB4_5:504;505; GFX10-64-LABEL: wqm_demote_2:506; GFX10-64: ; %bb.0: ; %.entry507; GFX10-64-NEXT: s_mov_b64 s[12:13], exec508; GFX10-64-NEXT: s_wqm_b64 exec, exec509; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D510; GFX10-64-NEXT: s_waitcnt vmcnt(0)511; GFX10-64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0512; GFX10-64-NEXT: s_and_saveexec_b64 s[14:15], vcc513; GFX10-64-NEXT: s_xor_b64 s[14:15], exec, s[14:15]514; GFX10-64-NEXT: s_cbranch_execz .LBB4_3515; GFX10-64-NEXT: ; %bb.1: ; %.demote516; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], exec517; GFX10-64-NEXT: s_cbranch_scc0 .LBB4_4518; GFX10-64-NEXT: ; %bb.2: ; %.demote519; GFX10-64-NEXT: s_wqm_b64 s[16:17], s[12:13]520; GFX10-64-NEXT: s_and_b64 exec, exec, s[16:17]521; GFX10-64-NEXT: .LBB4_3: ; %.continue522; GFX10-64-NEXT: s_or_b64 exec, exec, s[14:15]523; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0524; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]525; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D526; GFX10-64-NEXT: s_waitcnt vmcnt(0)527; GFX10-64-NEXT: s_branch .LBB4_5528; GFX10-64-NEXT: .LBB4_4:529; GFX10-64-NEXT: s_mov_b64 exec, 0530; GFX10-64-NEXT: exp null off, off, off, off done vm531; GFX10-64-NEXT: s_endpgm532; GFX10-64-NEXT: .LBB4_5:533.entry:534 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0535 %tex0 = extractelement <4 x float> %tex, i32 0536 %tex1 = extractelement <4 x float> %tex, i32 0537 %z.cmp = fcmp olt float %tex0, 0.0538 br i1 %z.cmp, label %.continue, label %.demote539 540.demote:541 call void @llvm.amdgcn.wqm.demote(i1 false)542 br label %.continue543 544.continue:545 %coord1 = fadd float %tex0, %tex1546 %rtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord1, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0547 548 ret <4 x float> %rtex549}550 551define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) {552; SI-LABEL: wqm_demote_dynamic:553; SI: ; %bb.0: ; %.entry554; SI-NEXT: s_mov_b64 s[12:13], exec555; SI-NEXT: s_wqm_b64 exec, exec556; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf557; SI-NEXT: s_waitcnt vmcnt(0)558; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0559; SI-NEXT: s_andn2_b64 s[14:15], exec, vcc560; SI-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]561; SI-NEXT: s_cbranch_scc0 .LBB5_2562; SI-NEXT: ; %bb.1: ; %.entry563; SI-NEXT: s_wqm_b64 s[14:15], s[12:13]564; SI-NEXT: s_and_b64 exec, exec, s[14:15]565; SI-NEXT: v_add_f32_e32 v0, v0, v0566; SI-NEXT: s_and_b64 exec, exec, s[12:13]567; SI-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf568; SI-NEXT: s_waitcnt vmcnt(0)569; SI-NEXT: s_branch .LBB5_3570; SI-NEXT: .LBB5_2:571; SI-NEXT: s_mov_b64 exec, 0572; SI-NEXT: exp null off, off, off, off done vm573; SI-NEXT: s_endpgm574; SI-NEXT: .LBB5_3:575;576; GFX9-LABEL: wqm_demote_dynamic:577; GFX9: ; %bb.0: ; %.entry578; GFX9-NEXT: s_mov_b64 s[12:13], exec579; GFX9-NEXT: s_wqm_b64 exec, exec580; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf581; GFX9-NEXT: s_waitcnt vmcnt(0)582; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0583; GFX9-NEXT: s_andn2_b64 s[14:15], exec, vcc584; GFX9-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]585; GFX9-NEXT: s_cbranch_scc0 .LBB5_2586; GFX9-NEXT: ; %bb.1: ; %.entry587; GFX9-NEXT: s_wqm_b64 s[14:15], s[12:13]588; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]589; GFX9-NEXT: v_add_f32_e32 v0, v0, v0590; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]591; GFX9-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf592; GFX9-NEXT: s_waitcnt vmcnt(0)593; GFX9-NEXT: s_branch .LBB5_3594; GFX9-NEXT: .LBB5_2:595; GFX9-NEXT: s_mov_b64 exec, 0596; GFX9-NEXT: exp null off, off, off, off done vm597; GFX9-NEXT: s_endpgm598; GFX9-NEXT: .LBB5_3:599;600; GFX10-32-LABEL: wqm_demote_dynamic:601; GFX10-32: ; %bb.0: ; %.entry602; GFX10-32-NEXT: s_mov_b32 s12, exec_lo603; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo604; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D605; GFX10-32-NEXT: s_waitcnt vmcnt(0)606; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0607; GFX10-32-NEXT: s_andn2_b32 s13, exec_lo, vcc_lo608; GFX10-32-NEXT: s_andn2_b32 s12, s12, s13609; GFX10-32-NEXT: s_cbranch_scc0 .LBB5_2610; GFX10-32-NEXT: ; %bb.1: ; %.entry611; GFX10-32-NEXT: s_wqm_b32 s13, s12612; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s13613; GFX10-32-NEXT: v_add_f32_e32 v0, v0, v0614; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s12615; GFX10-32-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D616; GFX10-32-NEXT: s_waitcnt vmcnt(0)617; GFX10-32-NEXT: s_branch .LBB5_3618; GFX10-32-NEXT: .LBB5_2:619; GFX10-32-NEXT: s_mov_b32 exec_lo, 0620; GFX10-32-NEXT: exp null off, off, off, off done vm621; GFX10-32-NEXT: s_endpgm622; GFX10-32-NEXT: .LBB5_3:623;624; GFX10-64-LABEL: wqm_demote_dynamic:625; GFX10-64: ; %bb.0: ; %.entry626; GFX10-64-NEXT: s_mov_b64 s[12:13], exec627; GFX10-64-NEXT: s_wqm_b64 exec, exec628; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D629; GFX10-64-NEXT: s_waitcnt vmcnt(0)630; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0631; GFX10-64-NEXT: s_andn2_b64 s[14:15], exec, vcc632; GFX10-64-NEXT: s_andn2_b64 s[12:13], s[12:13], s[14:15]633; GFX10-64-NEXT: s_cbranch_scc0 .LBB5_2634; GFX10-64-NEXT: ; %bb.1: ; %.entry635; GFX10-64-NEXT: s_wqm_b64 s[14:15], s[12:13]636; GFX10-64-NEXT: s_and_b64 exec, exec, s[14:15]637; GFX10-64-NEXT: v_add_f32_e32 v0, v0, v0638; GFX10-64-NEXT: s_and_b64 exec, exec, s[12:13]639; GFX10-64-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D640; GFX10-64-NEXT: s_waitcnt vmcnt(0)641; GFX10-64-NEXT: s_branch .LBB5_3642; GFX10-64-NEXT: .LBB5_2:643; GFX10-64-NEXT: s_mov_b64 exec, 0644; GFX10-64-NEXT: exp null off, off, off, off done vm645; GFX10-64-NEXT: s_endpgm646; GFX10-64-NEXT: .LBB5_3:647.entry:648 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0649 %tex0 = extractelement <4 x float> %tex, i32 0650 %tex1 = extractelement <4 x float> %tex, i32 0651 %z.cmp = fcmp olt float %tex0, 0.0652 call void @llvm.amdgcn.wqm.demote(i1 %z.cmp)653 %coord1 = fadd float %tex0, %tex1654 %rtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord1, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0655 656 ret <4 x float> %rtex657}658 659define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) {660; SI-LABEL: wqm_deriv:661; SI: ; %bb.0: ; %.entry662; SI-NEXT: s_mov_b64 s[0:1], exec663; SI-NEXT: s_wqm_b64 exec, exec664; SI-NEXT: v_cvt_i32_f32_e32 v0, v0665; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0666; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc667; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]668; SI-NEXT: s_cbranch_execz .LBB6_3669; SI-NEXT: ; %bb.1: ; %.demote0670; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec671; SI-NEXT: s_cbranch_scc0 .LBB6_7672; SI-NEXT: ; %bb.2: ; %.demote0673; SI-NEXT: s_wqm_b64 s[4:5], s[0:1]674; SI-NEXT: s_and_b64 exec, exec, s[4:5]675; SI-NEXT: .LBB6_3: ; %.continue0676; SI-NEXT: s_or_b64 exec, exec, s[2:3]677; SI-NEXT: s_mov_b64 s[2:3], s[0:1]678; SI-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]679; SI-NEXT: v_mov_b32_e32 v1, v0680; SI-NEXT: s_nop 1681; SI-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1682; SI-NEXT: s_nop 1683; SI-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1684; SI-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec685; SI-NEXT: s_and_b64 exec, exec, s[0:1]686; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0687; SI-NEXT: s_and_b64 s[2:3], s[0:1], vcc688; SI-NEXT: s_xor_b64 s[2:3], s[2:3], -1689; SI-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]690; SI-NEXT: s_xor_b64 s[2:3], exec, s[4:5]691; SI-NEXT: s_cbranch_execz .LBB6_6692; SI-NEXT: ; %bb.4: ; %.demote1693; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec694; SI-NEXT: s_cbranch_scc0 .LBB6_7695; SI-NEXT: ; %bb.5: ; %.demote1696; SI-NEXT: s_mov_b64 exec, 0697; SI-NEXT: .LBB6_6: ; %.continue1698; SI-NEXT: s_or_b64 exec, exec, s[2:3]699; SI-NEXT: v_mov_b32_e32 v0, 0x3c00700; SI-NEXT: v_bfrev_b32_e32 v1, 60701; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm702; SI-NEXT: s_endpgm703; SI-NEXT: .LBB6_7:704; SI-NEXT: s_mov_b64 exec, 0705; SI-NEXT: exp null off, off, off, off done vm706; SI-NEXT: s_endpgm707;708; GFX9-LABEL: wqm_deriv:709; GFX9: ; %bb.0: ; %.entry710; GFX9-NEXT: s_mov_b64 s[0:1], exec711; GFX9-NEXT: s_wqm_b64 exec, exec712; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0713; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0714; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc715; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3]716; GFX9-NEXT: s_cbranch_execz .LBB6_3717; GFX9-NEXT: ; %bb.1: ; %.demote0718; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec719; GFX9-NEXT: s_cbranch_scc0 .LBB6_7720; GFX9-NEXT: ; %bb.2: ; %.demote0721; GFX9-NEXT: s_wqm_b64 s[4:5], s[0:1]722; GFX9-NEXT: s_and_b64 exec, exec, s[4:5]723; GFX9-NEXT: .LBB6_3: ; %.continue0724; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]725; GFX9-NEXT: s_mov_b64 s[2:3], s[0:1]726; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]727; GFX9-NEXT: v_mov_b32_e32 v1, v0728; GFX9-NEXT: s_nop 1729; GFX9-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1730; GFX9-NEXT: s_nop 1731; GFX9-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1732; GFX9-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec733; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]734; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0735; GFX9-NEXT: s_and_b64 s[2:3], s[0:1], vcc736; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], -1737; GFX9-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]738; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[4:5]739; GFX9-NEXT: s_cbranch_execz .LBB6_6740; GFX9-NEXT: ; %bb.4: ; %.demote1741; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec742; GFX9-NEXT: s_cbranch_scc0 .LBB6_7743; GFX9-NEXT: ; %bb.5: ; %.demote1744; GFX9-NEXT: s_mov_b64 exec, 0745; GFX9-NEXT: .LBB6_6: ; %.continue1746; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]747; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00748; GFX9-NEXT: v_bfrev_b32_e32 v1, 60749; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm750; GFX9-NEXT: s_endpgm751; GFX9-NEXT: .LBB6_7:752; GFX9-NEXT: s_mov_b64 exec, 0753; GFX9-NEXT: exp null off, off, off, off done vm754; GFX9-NEXT: s_endpgm755;756; GFX10-32-LABEL: wqm_deriv:757; GFX10-32: ; %bb.0: ; %.entry758; GFX10-32-NEXT: s_mov_b32 s0, exec_lo759; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo760; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v0761; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0762; GFX10-32-NEXT: s_and_saveexec_b32 s1, vcc_lo763; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s1764; GFX10-32-NEXT: s_cbranch_execz .LBB6_3765; GFX10-32-NEXT: ; %bb.1: ; %.demote0766; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo767; GFX10-32-NEXT: s_cbranch_scc0 .LBB6_7768; GFX10-32-NEXT: ; %bb.2: ; %.demote0769; GFX10-32-NEXT: s_wqm_b32 s2, s0770; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s2771; GFX10-32-NEXT: .LBB6_3: ; %.continue0772; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1773; GFX10-32-NEXT: s_mov_b32 s1, s0774; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s1775; GFX10-32-NEXT: v_mov_b32_e32 v1, v0776; GFX10-32-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1777; GFX10-32-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1778; GFX10-32-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec779; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0780; GFX10-32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0781; GFX10-32-NEXT: s_and_b32 s1, s0, vcc_lo782; GFX10-32-NEXT: s_xor_b32 s1, s1, -1783; GFX10-32-NEXT: s_and_saveexec_b32 s2, s1784; GFX10-32-NEXT: s_xor_b32 s1, exec_lo, s2785; GFX10-32-NEXT: s_cbranch_execz .LBB6_6786; GFX10-32-NEXT: ; %bb.4: ; %.demote1787; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo788; GFX10-32-NEXT: s_cbranch_scc0 .LBB6_7789; GFX10-32-NEXT: ; %bb.5: ; %.demote1790; GFX10-32-NEXT: s_mov_b32 exec_lo, 0791; GFX10-32-NEXT: .LBB6_6: ; %.continue1792; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1793; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00794; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60795; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm796; GFX10-32-NEXT: s_endpgm797; GFX10-32-NEXT: .LBB6_7:798; GFX10-32-NEXT: s_mov_b32 exec_lo, 0799; GFX10-32-NEXT: exp null off, off, off, off done vm800; GFX10-32-NEXT: s_endpgm801;802; GFX10-64-LABEL: wqm_deriv:803; GFX10-64: ; %bb.0: ; %.entry804; GFX10-64-NEXT: s_mov_b64 s[0:1], exec805; GFX10-64-NEXT: s_wqm_b64 exec, exec806; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v0807; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0808; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc809; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]810; GFX10-64-NEXT: s_cbranch_execz .LBB6_3811; GFX10-64-NEXT: ; %bb.1: ; %.demote0812; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec813; GFX10-64-NEXT: s_cbranch_scc0 .LBB6_7814; GFX10-64-NEXT: ; %bb.2: ; %.demote0815; GFX10-64-NEXT: s_wqm_b64 s[4:5], s[0:1]816; GFX10-64-NEXT: s_and_b64 exec, exec, s[4:5]817; GFX10-64-NEXT: .LBB6_3: ; %.continue0818; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]819; GFX10-64-NEXT: s_mov_b64 s[2:3], s[0:1]820; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]821; GFX10-64-NEXT: v_mov_b32_e32 v1, v0822; GFX10-64-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1823; GFX10-64-NEXT: v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1824; GFX10-64-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec825; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1]826; GFX10-64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0827; GFX10-64-NEXT: s_and_b64 s[2:3], s[0:1], vcc828; GFX10-64-NEXT: s_xor_b64 s[2:3], s[2:3], -1829; GFX10-64-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]830; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[4:5]831; GFX10-64-NEXT: s_cbranch_execz .LBB6_6832; GFX10-64-NEXT: ; %bb.4: ; %.demote1833; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec834; GFX10-64-NEXT: s_cbranch_scc0 .LBB6_7835; GFX10-64-NEXT: ; %bb.5: ; %.demote1836; GFX10-64-NEXT: s_mov_b64 exec, 0837; GFX10-64-NEXT: .LBB6_6: ; %.continue1838; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]839; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00840; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60841; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm842; GFX10-64-NEXT: s_endpgm843; GFX10-64-NEXT: .LBB6_7:844; GFX10-64-NEXT: s_mov_b64 exec, 0845; GFX10-64-NEXT: exp null off, off, off, off done vm846; GFX10-64-NEXT: s_endpgm847.entry:848 %p0 = extractelement <2 x float> %input, i32 0849 %p1 = extractelement <2 x float> %input, i32 1850 %x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 0, i32 0, i32 %index) #2851 %x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 0, i32 0, i32 %index) #2852 %argi = fptosi float %arg to i32853 %cond0 = icmp eq i32 %argi, 0854 br i1 %cond0, label %.continue0, label %.demote0855 856.demote0:857 call void @llvm.amdgcn.wqm.demote(i1 false)858 br label %.continue0859 860.continue0:861 %live = call i1 @llvm.amdgcn.live.mask()862 %live.cond = select i1 %live, i32 0, i32 1065353216863 %live.v0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %live.cond, i32 85, i32 15, i32 15, i1 true)864 %live.v0f = bitcast i32 %live.v0 to float865 %live.v1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %live.cond, i32 0, i32 15, i32 15, i1 true)866 %live.v1f = bitcast i32 %live.v1 to float867 %v0 = fsub float %live.v0f, %live.v1f868 %v0.wqm = call float @llvm.amdgcn.wqm.f32(float %v0)869 %cond1 = fcmp oeq float %v0.wqm, 0.000000e+00870 %cond2 = and i1 %live, %cond1871 br i1 %cond2, label %.continue1, label %.demote1872 873.demote1:874 call void @llvm.amdgcn.wqm.demote(i1 false)875 br label %.continue1876 877.continue1:878 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> <half 0xH3C00, half 0xH0000>, <2 x half> <half 0xH0000, half 0xH3C00>, i1 true, i1 true) #3879 ret void880}881 882define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index, i32 %limit) {883; SI-LABEL: wqm_deriv_loop:884; SI: ; %bb.0: ; %.entry885; SI-NEXT: s_mov_b64 s[0:1], exec886; SI-NEXT: s_wqm_b64 exec, exec887; SI-NEXT: v_cvt_i32_f32_e32 v0, v0888; SI-NEXT: s_mov_b32 s4, 0889; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0890; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc891; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]892; SI-NEXT: s_cbranch_execz .LBB7_3893; SI-NEXT: ; %bb.1: ; %.demote0894; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec895; SI-NEXT: s_cbranch_scc0 .LBB7_9896; SI-NEXT: ; %bb.2: ; %.demote0897; SI-NEXT: s_wqm_b64 s[6:7], s[0:1]898; SI-NEXT: s_and_b64 exec, exec, s[6:7]899; SI-NEXT: .LBB7_3: ; %.continue0.preheader900; SI-NEXT: s_or_b64 exec, exec, s[2:3]901; SI-NEXT: s_mov_b64 s[2:3], 0902; SI-NEXT: v_mov_b32_e32 v0, s4903; SI-NEXT: s_branch .LBB7_5904; SI-NEXT: .LBB7_4: ; %.continue1905; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1906; SI-NEXT: s_or_b64 exec, exec, s[4:5]907; SI-NEXT: v_add_u32_e32 v0, vcc, 1, v0908; SI-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1909; SI-NEXT: s_or_b64 s[2:3], vcc, s[2:3]910; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]911; SI-NEXT: s_cbranch_execz .LBB7_8912; SI-NEXT: .LBB7_5: ; %.continue0913; SI-NEXT: ; =>This Inner Loop Header: Depth=1914; SI-NEXT: s_mov_b64 s[4:5], s[0:1]915; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5]916; SI-NEXT: v_mov_b32_e32 v3, v2917; SI-NEXT: s_nop 1918; SI-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1919; SI-NEXT: s_nop 1920; SI-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1921; SI-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec922; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2923; SI-NEXT: s_and_b64 s[4:5], s[0:1], vcc924; SI-NEXT: s_xor_b64 s[4:5], s[4:5], -1925; SI-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]926; SI-NEXT: s_xor_b64 s[4:5], exec, s[6:7]927; SI-NEXT: s_cbranch_execz .LBB7_4928; SI-NEXT: ; %bb.6: ; %.demote1929; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1930; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec931; SI-NEXT: s_cbranch_scc0 .LBB7_9932; SI-NEXT: ; %bb.7: ; %.demote1933; SI-NEXT: ; in Loop: Header=BB7_5 Depth=1934; SI-NEXT: s_wqm_b64 s[6:7], s[0:1]935; SI-NEXT: s_and_b64 exec, exec, s[6:7]936; SI-NEXT: s_branch .LBB7_4937; SI-NEXT: .LBB7_8: ; %.return938; SI-NEXT: s_or_b64 exec, exec, s[2:3]939; SI-NEXT: s_and_b64 exec, exec, s[0:1]940; SI-NEXT: v_mov_b32_e32 v0, 0x3c00941; SI-NEXT: v_bfrev_b32_e32 v1, 60942; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm943; SI-NEXT: s_endpgm944; SI-NEXT: .LBB7_9:945; SI-NEXT: s_mov_b64 exec, 0946; SI-NEXT: exp null off, off, off, off done vm947; SI-NEXT: s_endpgm948;949; GFX9-LABEL: wqm_deriv_loop:950; GFX9: ; %bb.0: ; %.entry951; GFX9-NEXT: s_mov_b64 s[0:1], exec952; GFX9-NEXT: s_wqm_b64 exec, exec953; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0954; GFX9-NEXT: s_mov_b32 s4, 0955; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0956; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc957; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3]958; GFX9-NEXT: s_cbranch_execz .LBB7_3959; GFX9-NEXT: ; %bb.1: ; %.demote0960; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec961; GFX9-NEXT: s_cbranch_scc0 .LBB7_9962; GFX9-NEXT: ; %bb.2: ; %.demote0963; GFX9-NEXT: s_wqm_b64 s[6:7], s[0:1]964; GFX9-NEXT: s_and_b64 exec, exec, s[6:7]965; GFX9-NEXT: .LBB7_3: ; %.continue0.preheader966; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]967; GFX9-NEXT: s_mov_b64 s[2:3], 0968; GFX9-NEXT: v_mov_b32_e32 v0, s4969; GFX9-NEXT: s_branch .LBB7_5970; GFX9-NEXT: .LBB7_4: ; %.continue1971; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1972; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]973; GFX9-NEXT: v_add_u32_e32 v0, 1, v0974; GFX9-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1975; GFX9-NEXT: s_or_b64 s[2:3], vcc, s[2:3]976; GFX9-NEXT: s_andn2_b64 exec, exec, s[2:3]977; GFX9-NEXT: s_cbranch_execz .LBB7_8978; GFX9-NEXT: .LBB7_5: ; %.continue0979; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1980; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]981; GFX9-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5]982; GFX9-NEXT: v_mov_b32_e32 v3, v2983; GFX9-NEXT: s_nop 1984; GFX9-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1985; GFX9-NEXT: s_nop 1986; GFX9-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1987; GFX9-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec988; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2989; GFX9-NEXT: s_and_b64 s[4:5], s[0:1], vcc990; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], -1991; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]992; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7]993; GFX9-NEXT: s_cbranch_execz .LBB7_4994; GFX9-NEXT: ; %bb.6: ; %.demote1995; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=1996; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], exec997; GFX9-NEXT: s_cbranch_scc0 .LBB7_9998; GFX9-NEXT: ; %bb.7: ; %.demote1999; GFX9-NEXT: ; in Loop: Header=BB7_5 Depth=11000; GFX9-NEXT: s_wqm_b64 s[6:7], s[0:1]1001; GFX9-NEXT: s_and_b64 exec, exec, s[6:7]1002; GFX9-NEXT: s_branch .LBB7_41003; GFX9-NEXT: .LBB7_8: ; %.return1004; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]1005; GFX9-NEXT: s_and_b64 exec, exec, s[0:1]1006; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c001007; GFX9-NEXT: v_bfrev_b32_e32 v1, 601008; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm1009; GFX9-NEXT: s_endpgm1010; GFX9-NEXT: .LBB7_9:1011; GFX9-NEXT: s_mov_b64 exec, 01012; GFX9-NEXT: exp null off, off, off, off done vm1013; GFX9-NEXT: s_endpgm1014;1015; GFX10-32-LABEL: wqm_deriv_loop:1016; GFX10-32: ; %bb.0: ; %.entry1017; GFX10-32-NEXT: s_mov_b32 s0, exec_lo1018; GFX10-32-NEXT: s_wqm_b32 exec_lo, exec_lo1019; GFX10-32-NEXT: v_cvt_i32_f32_e32 v0, v01020; GFX10-32-NEXT: s_mov_b32 s1, 01021; GFX10-32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v01022; GFX10-32-NEXT: s_and_saveexec_b32 s2, vcc_lo1023; GFX10-32-NEXT: s_xor_b32 s2, exec_lo, s21024; GFX10-32-NEXT: s_cbranch_execz .LBB7_31025; GFX10-32-NEXT: ; %bb.1: ; %.demote01026; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo1027; GFX10-32-NEXT: s_cbranch_scc0 .LBB7_91028; GFX10-32-NEXT: ; %bb.2: ; %.demote01029; GFX10-32-NEXT: s_wqm_b32 s3, s01030; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s31031; GFX10-32-NEXT: .LBB7_3: ; %.continue0.preheader1032; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s21033; GFX10-32-NEXT: v_mov_b32_e32 v0, s11034; GFX10-32-NEXT: s_branch .LBB7_51035; GFX10-32-NEXT: .LBB7_4: ; %.continue11036; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=11037; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s21038; GFX10-32-NEXT: v_add_nc_u32_e32 v0, 1, v01039; GFX10-32-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v11040; GFX10-32-NEXT: s_or_b32 s1, vcc_lo, s11041; GFX10-32-NEXT: s_andn2_b32 exec_lo, exec_lo, s11042; GFX10-32-NEXT: s_cbranch_execz .LBB7_81043; GFX10-32-NEXT: .LBB7_5: ; %.continue01044; GFX10-32-NEXT: ; =>This Inner Loop Header: Depth=11045; GFX10-32-NEXT: s_mov_b32 s2, s01046; GFX10-32-NEXT: v_cndmask_b32_e64 v2, v0, 0, s21047; GFX10-32-NEXT: v_mov_b32_e32 v3, v21048; GFX10-32-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:11049; GFX10-32-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:11050; GFX10-32-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec1051; GFX10-32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21052; GFX10-32-NEXT: s_and_b32 s2, s0, vcc_lo1053; GFX10-32-NEXT: s_xor_b32 s2, s2, -11054; GFX10-32-NEXT: s_and_saveexec_b32 s3, s21055; GFX10-32-NEXT: s_xor_b32 s2, exec_lo, s31056; GFX10-32-NEXT: s_cbranch_execz .LBB7_41057; GFX10-32-NEXT: ; %bb.6: ; %.demote11058; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=11059; GFX10-32-NEXT: s_andn2_b32 s0, s0, exec_lo1060; GFX10-32-NEXT: s_cbranch_scc0 .LBB7_91061; GFX10-32-NEXT: ; %bb.7: ; %.demote11062; GFX10-32-NEXT: ; in Loop: Header=BB7_5 Depth=11063; GFX10-32-NEXT: s_wqm_b32 s3, s01064; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s31065; GFX10-32-NEXT: s_branch .LBB7_41066; GFX10-32-NEXT: .LBB7_8: ; %.return1067; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s11068; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s01069; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c001070; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 601071; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm1072; GFX10-32-NEXT: s_endpgm1073; GFX10-32-NEXT: .LBB7_9:1074; GFX10-32-NEXT: s_mov_b32 exec_lo, 01075; GFX10-32-NEXT: exp null off, off, off, off done vm1076; GFX10-32-NEXT: s_endpgm1077;1078; GFX10-64-LABEL: wqm_deriv_loop:1079; GFX10-64: ; %bb.0: ; %.entry1080; GFX10-64-NEXT: s_mov_b64 s[0:1], exec1081; GFX10-64-NEXT: s_wqm_b64 exec, exec1082; GFX10-64-NEXT: v_cvt_i32_f32_e32 v0, v01083; GFX10-64-NEXT: s_mov_b32 s4, 01084; GFX10-64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01085; GFX10-64-NEXT: s_and_saveexec_b64 s[2:3], vcc1086; GFX10-64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1087; GFX10-64-NEXT: s_cbranch_execz .LBB7_31088; GFX10-64-NEXT: ; %bb.1: ; %.demote01089; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec1090; GFX10-64-NEXT: s_cbranch_scc0 .LBB7_91091; GFX10-64-NEXT: ; %bb.2: ; %.demote01092; GFX10-64-NEXT: s_wqm_b64 s[6:7], s[0:1]1093; GFX10-64-NEXT: s_and_b64 exec, exec, s[6:7]1094; GFX10-64-NEXT: .LBB7_3: ; %.continue0.preheader1095; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]1096; GFX10-64-NEXT: v_mov_b32_e32 v0, s41097; GFX10-64-NEXT: s_mov_b64 s[2:3], 01098; GFX10-64-NEXT: s_branch .LBB7_51099; GFX10-64-NEXT: .LBB7_4: ; %.continue11100; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=11101; GFX10-64-NEXT: s_or_b64 exec, exec, s[4:5]1102; GFX10-64-NEXT: v_add_nc_u32_e32 v0, 1, v01103; GFX10-64-NEXT: v_cmp_ge_i32_e32 vcc, v0, v11104; GFX10-64-NEXT: s_or_b64 s[2:3], vcc, s[2:3]1105; GFX10-64-NEXT: s_andn2_b64 exec, exec, s[2:3]1106; GFX10-64-NEXT: s_cbranch_execz .LBB7_81107; GFX10-64-NEXT: .LBB7_5: ; %.continue01108; GFX10-64-NEXT: ; =>This Inner Loop Header: Depth=11109; GFX10-64-NEXT: s_mov_b64 s[4:5], s[0:1]1110; GFX10-64-NEXT: v_cndmask_b32_e64 v2, v0, 0, s[4:5]1111; GFX10-64-NEXT: v_mov_b32_e32 v3, v21112; GFX10-64-NEXT: v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:11113; GFX10-64-NEXT: v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:11114; GFX10-64-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec1115; GFX10-64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21116; GFX10-64-NEXT: s_and_b64 s[4:5], s[0:1], vcc1117; GFX10-64-NEXT: s_xor_b64 s[4:5], s[4:5], -11118; GFX10-64-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]1119; GFX10-64-NEXT: s_xor_b64 s[4:5], exec, s[6:7]1120; GFX10-64-NEXT: s_cbranch_execz .LBB7_41121; GFX10-64-NEXT: ; %bb.6: ; %.demote11122; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=11123; GFX10-64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec1124; GFX10-64-NEXT: s_cbranch_scc0 .LBB7_91125; GFX10-64-NEXT: ; %bb.7: ; %.demote11126; GFX10-64-NEXT: ; in Loop: Header=BB7_5 Depth=11127; GFX10-64-NEXT: s_wqm_b64 s[6:7], s[0:1]1128; GFX10-64-NEXT: s_and_b64 exec, exec, s[6:7]1129; GFX10-64-NEXT: s_branch .LBB7_41130; GFX10-64-NEXT: .LBB7_8: ; %.return1131; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3]1132; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1]1133; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c001134; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 601135; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm1136; GFX10-64-NEXT: s_endpgm1137; GFX10-64-NEXT: .LBB7_9:1138; GFX10-64-NEXT: s_mov_b64 exec, 01139; GFX10-64-NEXT: exp null off, off, off, off done vm1140; GFX10-64-NEXT: s_endpgm1141.entry:1142 %p0 = extractelement <2 x float> %input, i32 01143 %p1 = extractelement <2 x float> %input, i32 11144 %x0 = call float @llvm.amdgcn.interp.p1(float %p0, i32 0, i32 0, i32 %index) #21145 %x1 = call float @llvm.amdgcn.interp.p2(float %x0, float %p1, i32 0, i32 0, i32 %index) #21146 %argi = fptosi float %arg to i321147 %cond0 = icmp eq i32 %argi, 01148 br i1 %cond0, label %.continue0, label %.demote01149 1150.demote0:1151 call void @llvm.amdgcn.wqm.demote(i1 false)1152 br label %.continue01153 1154.continue0:1155 %count = phi i32 [ 0, %.entry ], [ 0, %.demote0 ], [ %next, %.continue1 ]1156 %live = call i1 @llvm.amdgcn.live.mask()1157 %live.cond = select i1 %live, i32 0, i32 %count1158 %live.v0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %live.cond, i32 85, i32 15, i32 15, i1 true)1159 %live.v0f = bitcast i32 %live.v0 to float1160 %live.v1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %live.cond, i32 0, i32 15, i32 15, i1 true)1161 %live.v1f = bitcast i32 %live.v1 to float1162 %v0 = fsub float %live.v0f, %live.v1f1163 %v0.wqm = call float @llvm.amdgcn.wqm.f32(float %v0)1164 %cond1 = fcmp oeq float %v0.wqm, 0.000000e+001165 %cond2 = and i1 %live, %cond11166 br i1 %cond2, label %.continue1, label %.demote11167 1168.demote1:1169 call void @llvm.amdgcn.wqm.demote(i1 false)1170 br label %.continue11171 1172.continue1:1173 %next = add i32 %count, 11174 %loop.cond = icmp slt i32 %next, %limit1175 br i1 %loop.cond, label %.continue0, label %.return1176 1177.return:1178 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> <half 0xH3C00, half 0xH0000>, <2 x half> <half 0xH0000, half 0xH3C00>, i1 true, i1 true) #31179 ret void1180}1181 1182declare void @llvm.amdgcn.wqm.demote(i1) #01183declare i1 @llvm.amdgcn.live.mask() #01184declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #01185declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #11186declare float @llvm.amdgcn.wqm.f32(float) #11187declare float @llvm.amdgcn.interp.p1(float, i32 immarg, i32 immarg, i32) #21188declare float @llvm.amdgcn.interp.p2(float, float, i32 immarg, i32 immarg, i32) #21189declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg) #31190declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #41191 1192attributes #0 = { nounwind }1193attributes #1 = { nounwind readnone }1194attributes #2 = { nounwind readnone speculatable }1195attributes #3 = { inaccessiblememonly nounwind }1196attributes #4 = { convergent nounwind readnone }1197