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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii -stop-after=instruction-select < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_ps float @wqm_f32(float %val) {5 ; GCN-LABEL: name: wqm_f326 ; GCN: bb.1 (%ir-block.0):7 ; GCN-NEXT: liveins: $vgpr08 ; GCN-NEXT: {{ $}}9 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr010 ; GCN-NEXT: [[WQM:%[0-9]+]]:vgpr_32 = WQM [[COPY]], implicit $exec11 ; GCN-NEXT: $vgpr0 = COPY [[WQM]]12 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr013 %ret = call float @llvm.amdgcn.wqm.f32(float %val)14 ret float %ret15}16 17define amdgpu_ps float @wqm_v2f16(float %arg) {18 ; GCN-LABEL: name: wqm_v2f1619 ; GCN: bb.1 (%ir-block.0):20 ; GCN-NEXT: liveins: $vgpr021 ; GCN-NEXT: {{ $}}22 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr023 ; GCN-NEXT: [[WQM:%[0-9]+]]:vgpr_32 = WQM [[COPY]], implicit $exec24 ; GCN-NEXT: $vgpr0 = COPY [[WQM]]25 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr026 %val = bitcast float %arg to <2 x half>27 %ret = call <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half> %val)28 %bc = bitcast <2 x half> %ret to float29 ret float %bc30}31 32define amdgpu_ps <2 x float> @wqm_f64(double %val) {33 ; GCN-LABEL: name: wqm_f6434 ; GCN: bb.1 (%ir-block.0):35 ; GCN-NEXT: liveins: $vgpr0, $vgpr136 ; GCN-NEXT: {{ $}}37 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr038 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr139 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub140 ; GCN-NEXT: [[WQM:%[0-9]+]]:vreg_64 = WQM [[REG_SEQUENCE]], implicit $exec41 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub042 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub143 ; GCN-NEXT: $vgpr0 = COPY [[COPY2]]44 ; GCN-NEXT: $vgpr1 = COPY [[COPY3]]45 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr146 %ret = call double @llvm.amdgcn.wqm.f64(double %val)47 %bitcast = bitcast double %ret to <2 x float>48 ret <2 x float> %bitcast49}50 51; TODO52; define amdgpu_ps float @wqm_i1_vcc(float %val) {53; %vcc = fcmp oeq float %val, 0.054; %ret = call i1 @llvm.amdgcn.wqm.i1(i1 %vcc)55; %select = select i1 %ret, float 1.0, float 0.056; ret float %select57; }58 59define amdgpu_ps <3 x float> @wqm_v3f32(<3 x float> %val) {60 ; GCN-LABEL: name: wqm_v3f3261 ; GCN: bb.1 (%ir-block.0):62 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $vgpr263 ; GCN-NEXT: {{ $}}64 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr065 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr166 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr267 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub268 ; GCN-NEXT: [[WQM:%[0-9]+]]:vreg_96 = WQM [[REG_SEQUENCE]], implicit $exec69 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub070 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub171 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub272 ; GCN-NEXT: $vgpr0 = COPY [[COPY3]]73 ; GCN-NEXT: $vgpr1 = COPY [[COPY4]]74 ; GCN-NEXT: $vgpr2 = COPY [[COPY5]]75 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr276 %ret = call <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float> %val)77 ret <3 x float> %ret78}79 80declare i1 @llvm.amdgcn.wqm.i1(i1) #081declare float @llvm.amdgcn.wqm.f32(float) #082declare <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half>) #083declare <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float>) #084declare double @llvm.amdgcn.wqm.f64(double) #085 86attributes #0 = { nounwind readnone speculatable }87