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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s5; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s6 7define amdgpu_ps float @test_writelane_s_s_s(i32 inreg %data, i32 inreg %lane, i32 inreg %vdst.in) #0 {8; GFX7-LABEL: test_writelane_s_s_s:9; GFX7: ; %bb.0:10; GFX7-NEXT: v_mov_b32_e32 v0, s411; GFX7-NEXT: s_mov_b32 m0, s312; GFX7-NEXT: v_writelane_b32 v0, s2, m013; GFX7-NEXT: ; return to shader part epilog14;15; GFX8-LABEL: test_writelane_s_s_s:16; GFX8: ; %bb.0:17; GFX8-NEXT: v_mov_b32_e32 v0, s418; GFX8-NEXT: s_mov_b32 m0, s319; GFX8-NEXT: v_writelane_b32 v0, s2, m020; GFX8-NEXT: ; return to shader part epilog21;22; GFX10-LABEL: test_writelane_s_s_s:23; GFX10: ; %bb.0:24; GFX10-NEXT: v_mov_b32_e32 v0, s425; GFX10-NEXT: v_writelane_b32 v0, s2, s326; GFX10-NEXT: ; return to shader part epilog27 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 %vdst.in)28 %writelane.cast = bitcast i32 %writelane to float29 ret float %writelane.cast30}31 32define amdgpu_ps float @test_writelane_s_s_imm(i32 inreg %data, i32 inreg %lane) #0 {33; GFX7-LABEL: test_writelane_s_s_imm:34; GFX7: ; %bb.0:35; GFX7-NEXT: v_mov_b32_e32 v0, 4236; GFX7-NEXT: s_mov_b32 m0, s337; GFX7-NEXT: v_writelane_b32 v0, s2, m038; GFX7-NEXT: ; return to shader part epilog39;40; GFX8-LABEL: test_writelane_s_s_imm:41; GFX8: ; %bb.0:42; GFX8-NEXT: v_mov_b32_e32 v0, 4243; GFX8-NEXT: s_mov_b32 m0, s344; GFX8-NEXT: v_writelane_b32 v0, s2, m045; GFX8-NEXT: ; return to shader part epilog46;47; GFX10-LABEL: test_writelane_s_s_imm:48; GFX10: ; %bb.0:49; GFX10-NEXT: v_mov_b32_e32 v0, 4250; GFX10-NEXT: v_writelane_b32 v0, s2, s351; GFX10-NEXT: ; return to shader part epilog52 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 42)53 %writelane.cast = bitcast i32 %writelane to float54 ret float %writelane.cast55}56 57; data is not inline imm58define amdgpu_ps float @test_writelane_k_s_v(i32 inreg %lane, i32 %vdst.in) #0 {59; GFX7-LABEL: test_writelane_k_s_v:60; GFX7: ; %bb.0:61; GFX7-NEXT: s_movk_i32 s0, 0x3e762; GFX7-NEXT: s_mov_b32 m0, s263; GFX7-NEXT: v_writelane_b32 v0, s0, m064; GFX7-NEXT: ; return to shader part epilog65;66; GFX8-LABEL: test_writelane_k_s_v:67; GFX8: ; %bb.0:68; GFX8-NEXT: s_movk_i32 s0, 0x3e769; GFX8-NEXT: s_mov_b32 m0, s270; GFX8-NEXT: v_writelane_b32 v0, s0, m071; GFX8-NEXT: ; return to shader part epilog72;73; GFX10-LABEL: test_writelane_k_s_v:74; GFX10: ; %bb.0:75; GFX10-NEXT: s_movk_i32 s0, 0x3e776; GFX10-NEXT: v_writelane_b32 v0, s0, s277; GFX10-NEXT: ; return to shader part epilog78 %writelane = call i32 @llvm.amdgcn.writelane(i32 999, i32 %lane, i32 %vdst.in)79 %writelane.cast = bitcast i32 %writelane to float80 ret float %writelane.cast81}82 83; Data is inline imm84define amdgpu_ps float @test_writelane_imm_s_v(i32 inreg %lane, i32 %vdst.in) #0 {85; GFX7-LABEL: test_writelane_imm_s_v:86; GFX7: ; %bb.0:87; GFX7-NEXT: v_writelane_b32 v0, 42, s288; GFX7-NEXT: ; return to shader part epilog89;90; GFX8-LABEL: test_writelane_imm_s_v:91; GFX8: ; %bb.0:92; GFX8-NEXT: v_writelane_b32 v0, 42, s293; GFX8-NEXT: ; return to shader part epilog94;95; GFX10-LABEL: test_writelane_imm_s_v:96; GFX10: ; %bb.0:97; GFX10-NEXT: v_writelane_b32 v0, 42, s298; GFX10-NEXT: ; return to shader part epilog99 %writelane = call i32 @llvm.amdgcn.writelane(i32 42, i32 %lane, i32 %vdst.in)100 %writelane.cast = bitcast i32 %writelane to float101 ret float %writelane.cast102}103 104; Data is subtarget dependent inline imm105define amdgpu_ps float @test_writelane_imminv2pi_s_v(i32 inreg %lane, i32 %vdst.in) #0 {106; GFX7-LABEL: test_writelane_imminv2pi_s_v:107; GFX7: ; %bb.0:108; GFX7-NEXT: s_mov_b32 s0, 0x3e22f983109; GFX7-NEXT: s_mov_b32 m0, s2110; GFX7-NEXT: v_writelane_b32 v0, s0, m0111; GFX7-NEXT: ; return to shader part epilog112;113; GFX8-LABEL: test_writelane_imminv2pi_s_v:114; GFX8: ; %bb.0:115; GFX8-NEXT: v_writelane_b32 v0, 0.15915494, s2116; GFX8-NEXT: ; return to shader part epilog117;118; GFX10-LABEL: test_writelane_imminv2pi_s_v:119; GFX10: ; %bb.0:120; GFX10-NEXT: v_writelane_b32 v0, 0.15915494, s2121; GFX10-NEXT: ; return to shader part epilog122 %writelane = call i32 @llvm.amdgcn.writelane(i32 bitcast (float 0x3FC45F3060000000 to i32), i32 %lane, i32 %vdst.in)123 %writelane.cast = bitcast i32 %writelane to float124 ret float %writelane.cast125}126 127 128; Lane is inline imm129define amdgpu_ps float @test_writelane_s_imm_v(i32 inreg %data, i32 %vdst.in) #0 {130; GFX7-LABEL: test_writelane_s_imm_v:131; GFX7: ; %bb.0:132; GFX7-NEXT: v_writelane_b32 v0, s2, 23133; GFX7-NEXT: ; return to shader part epilog134;135; GFX8-LABEL: test_writelane_s_imm_v:136; GFX8: ; %bb.0:137; GFX8-NEXT: v_writelane_b32 v0, s2, 23138; GFX8-NEXT: ; return to shader part epilog139;140; GFX10-LABEL: test_writelane_s_imm_v:141; GFX10: ; %bb.0:142; GFX10-NEXT: v_writelane_b32 v0, s2, 23143; GFX10-NEXT: ; return to shader part epilog144 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 23, i32 %vdst.in)145 %writelane.cast = bitcast i32 %writelane to float146 ret float %writelane.cast147}148 149; Lane index is larger than the wavesize150define amdgpu_ps float @test_writelane_s_k0_v(i32 inreg %data, i32 %vdst.in) #0 {151; GFX7-LABEL: test_writelane_s_k0_v:152; GFX7: ; %bb.0:153; GFX7-NEXT: v_writelane_b32 v0, s2, 3154; GFX7-NEXT: ; return to shader part epilog155;156; GFX8-LABEL: test_writelane_s_k0_v:157; GFX8: ; %bb.0:158; GFX8-NEXT: v_writelane_b32 v0, s2, 3159; GFX8-NEXT: ; return to shader part epilog160;161; GFX10-LABEL: test_writelane_s_k0_v:162; GFX10: ; %bb.0:163; GFX10-NEXT: s_movk_i32 s0, 0x43164; GFX10-NEXT: v_writelane_b32 v0, s2, s0165; GFX10-NEXT: ; return to shader part epilog166 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 67, i32 %vdst.in)167 %writelane.cast = bitcast i32 %writelane to float168 ret float %writelane.cast169}170 171; Lane index is larger than the wavesize for wave32172define amdgpu_ps float @test_writelane_s_k1_v(i32 inreg %data, i32 %vdst.in) #0 {173; GFX7-LABEL: test_writelane_s_k1_v:174; GFX7: ; %bb.0:175; GFX7-NEXT: v_writelane_b32 v0, s2, 32176; GFX7-NEXT: ; return to shader part epilog177;178; GFX8-LABEL: test_writelane_s_k1_v:179; GFX8: ; %bb.0:180; GFX8-NEXT: v_writelane_b32 v0, s2, 32181; GFX8-NEXT: ; return to shader part epilog182;183; GFX10-LABEL: test_writelane_s_k1_v:184; GFX10: ; %bb.0:185; GFX10-NEXT: v_writelane_b32 v0, s2, 32186; GFX10-NEXT: ; return to shader part epilog187 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 32, i32 %vdst.in)188 %writelane.cast = bitcast i32 %writelane to float189 ret float %writelane.cast190}191 192define amdgpu_ps float @test_writelane_v_v_v(i32 %data, i32 %lane, i32 %vdst.in) #0 {193; GFX7-LABEL: test_writelane_v_v_v:194; GFX7: ; %bb.0:195; GFX7-NEXT: v_readfirstlane_b32 s1, v1196; GFX7-NEXT: v_readfirstlane_b32 s0, v0197; GFX7-NEXT: s_mov_b32 m0, s1198; GFX7-NEXT: v_writelane_b32 v2, s0, m0199; GFX7-NEXT: v_mov_b32_e32 v0, v2200; GFX7-NEXT: ; return to shader part epilog201;202; GFX8-LABEL: test_writelane_v_v_v:203; GFX8: ; %bb.0:204; GFX8-NEXT: v_readfirstlane_b32 s1, v1205; GFX8-NEXT: v_readfirstlane_b32 s0, v0206; GFX8-NEXT: s_mov_b32 m0, s1207; GFX8-NEXT: v_writelane_b32 v2, s0, m0208; GFX8-NEXT: v_mov_b32_e32 v0, v2209; GFX8-NEXT: ; return to shader part epilog210;211; GFX10-LABEL: test_writelane_v_v_v:212; GFX10: ; %bb.0:213; GFX10-NEXT: v_readfirstlane_b32 s0, v0214; GFX10-NEXT: v_readfirstlane_b32 s1, v1215; GFX10-NEXT: v_writelane_b32 v2, s0, s1216; GFX10-NEXT: v_mov_b32_e32 v0, v2217; GFX10-NEXT: ; return to shader part epilog218 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 %vdst.in)219 %writelane.cast = bitcast i32 %writelane to float220 ret float %writelane.cast221}222 223define amdgpu_ps float @test_writelane_v_s_v(i32 %data, i32 inreg %lane, i32 %vdst.in) #0 {224; GFX7-LABEL: test_writelane_v_s_v:225; GFX7: ; %bb.0:226; GFX7-NEXT: v_readfirstlane_b32 s0, v0227; GFX7-NEXT: s_mov_b32 m0, s2228; GFX7-NEXT: v_writelane_b32 v1, s0, m0229; GFX7-NEXT: v_mov_b32_e32 v0, v1230; GFX7-NEXT: ; return to shader part epilog231;232; GFX8-LABEL: test_writelane_v_s_v:233; GFX8: ; %bb.0:234; GFX8-NEXT: v_readfirstlane_b32 s0, v0235; GFX8-NEXT: s_mov_b32 m0, s2236; GFX8-NEXT: v_writelane_b32 v1, s0, m0237; GFX8-NEXT: v_mov_b32_e32 v0, v1238; GFX8-NEXT: ; return to shader part epilog239;240; GFX10-LABEL: test_writelane_v_s_v:241; GFX10: ; %bb.0:242; GFX10-NEXT: v_readfirstlane_b32 s0, v0243; GFX10-NEXT: v_writelane_b32 v1, s0, s2244; GFX10-NEXT: v_mov_b32_e32 v0, v1245; GFX10-NEXT: ; return to shader part epilog246 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 inreg %lane, i32 %vdst.in)247 %writelane.cast = bitcast i32 %writelane to float248 ret float %writelane.cast249}250 251; FIXME: This could theoretically use m0 directly as the data source,252; and another SGPR as the lane selector and avoid register swap.253define amdgpu_ps float @test_writelane_m0_s_v(i32 inreg %lane, i32 %vdst.in) #0 {254; GFX7-LABEL: test_writelane_m0_s_v:255; GFX7: ; %bb.0:256; GFX7-NEXT: ;;#ASMSTART257; GFX7-NEXT: s_mov_b32 m0, -1258; GFX7-NEXT: ;;#ASMEND259; GFX7-NEXT: s_mov_b32 s0, m0260; GFX7-NEXT: s_mov_b32 m0, s2261; GFX7-NEXT: v_writelane_b32 v0, s0, m0262; GFX7-NEXT: ; return to shader part epilog263;264; GFX8-LABEL: test_writelane_m0_s_v:265; GFX8: ; %bb.0:266; GFX8-NEXT: ;;#ASMSTART267; GFX8-NEXT: s_mov_b32 m0, -1268; GFX8-NEXT: ;;#ASMEND269; GFX8-NEXT: s_mov_b32 s0, m0270; GFX8-NEXT: s_mov_b32 m0, s2271; GFX8-NEXT: v_writelane_b32 v0, s0, m0272; GFX8-NEXT: ; return to shader part epilog273;274; GFX10-LABEL: test_writelane_m0_s_v:275; GFX10: ; %bb.0:276; GFX10-NEXT: ;;#ASMSTART277; GFX10-NEXT: s_mov_b32 m0, -1278; GFX10-NEXT: ;;#ASMEND279; GFX10-NEXT: v_writelane_b32 v0, m0, s2280; GFX10-NEXT: ; return to shader part epilog281 %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()282 %writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %lane, i32 %vdst.in)283 %writelane.cast = bitcast i32 %writelane to float284 ret float %writelane.cast285}286 287define amdgpu_ps float @test_writelane_s_m0_v(i32 inreg %data, i32 %vdst.in) #0 {288; GFX7-LABEL: test_writelane_s_m0_v:289; GFX7: ; %bb.0:290; GFX7-NEXT: ;;#ASMSTART291; GFX7-NEXT: s_mov_b32 m0, -1292; GFX7-NEXT: ;;#ASMEND293; GFX7-NEXT: v_writelane_b32 v0, s2, m0294; GFX7-NEXT: ; return to shader part epilog295;296; GFX8-LABEL: test_writelane_s_m0_v:297; GFX8: ; %bb.0:298; GFX8-NEXT: ;;#ASMSTART299; GFX8-NEXT: s_mov_b32 m0, -1300; GFX8-NEXT: ;;#ASMEND301; GFX8-NEXT: v_writelane_b32 v0, s2, m0302; GFX8-NEXT: ; return to shader part epilog303;304; GFX10-LABEL: test_writelane_s_m0_v:305; GFX10: ; %bb.0:306; GFX10-NEXT: ;;#ASMSTART307; GFX10-NEXT: s_mov_b32 m0, -1308; GFX10-NEXT: ;;#ASMEND309; GFX10-NEXT: v_writelane_b32 v0, s2, m0310; GFX10-NEXT: ; return to shader part epilog311 %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()312 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %m0, i32 %vdst.in)313 %writelane.cast = bitcast i32 %writelane to float314 ret float %writelane.cast315}316 317declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #1318declare i32 @llvm.amdgcn.workitem.id.x() #2319 320attributes #0 = { nounwind }321attributes #1 = { convergent nounwind readnone willreturn }322attributes #2 = { nounwind readnone speculatable willreturn }323