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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii -stop-after=instruction-select < %s | FileCheck -check-prefix=GCN %s3 4; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead.5 6define amdgpu_ps float @wwm_f32(float %val) {7 ; GCN-LABEL: name: wwm_f328 ; GCN: bb.1 (%ir-block.0):9 ; GCN-NEXT: liveins: $vgpr010 ; GCN-NEXT: {{ $}}11 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr012 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vgpr_32 = STRICT_WWM [[COPY]], implicit $exec13 ; GCN-NEXT: $vgpr0 = COPY [[STRICT_WWM]]14 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr015 %ret = call float @llvm.amdgcn.wwm.f32(float %val)16 ret float %ret17}18 19define amdgpu_ps float @wwm_v2f16(float %arg) {20 ; GCN-LABEL: name: wwm_v2f1621 ; GCN: bb.1 (%ir-block.0):22 ; GCN-NEXT: liveins: $vgpr023 ; GCN-NEXT: {{ $}}24 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr025 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vgpr_32 = STRICT_WWM [[COPY]], implicit $exec26 ; GCN-NEXT: $vgpr0 = COPY [[STRICT_WWM]]27 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr028 %val = bitcast float %arg to <2 x half>29 %ret = call <2 x half> @llvm.amdgcn.wwm.v2f16(<2 x half> %val)30 %bc = bitcast <2 x half> %ret to float31 ret float %bc32}33 34define amdgpu_ps <2 x float> @wwm_f64(double %val) {35 ; GCN-LABEL: name: wwm_f6436 ; GCN: bb.1 (%ir-block.0):37 ; GCN-NEXT: liveins: $vgpr0, $vgpr138 ; GCN-NEXT: {{ $}}39 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr040 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr141 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub142 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vreg_64 = STRICT_WWM [[REG_SEQUENCE]], implicit $exec43 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub044 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub145 ; GCN-NEXT: $vgpr0 = COPY [[COPY2]]46 ; GCN-NEXT: $vgpr1 = COPY [[COPY3]]47 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr148 %ret = call double @llvm.amdgcn.wwm.f64(double %val)49 %bitcast = bitcast double %ret to <2 x float>50 ret <2 x float> %bitcast51}52 53; TODO54; define amdgpu_ps float @wwm_i1_vcc(float %val) {55; %vcc = fcmp oeq float %val, 0.056; %ret = call i1 @llvm.amdgcn.wwm.i1(i1 %vcc)57; %select = select i1 %ret, float 1.0, float 0.058; ret float %select59; }60 61define amdgpu_ps <3 x float> @wwm_v3f32(<3 x float> %val) {62 ; GCN-LABEL: name: wwm_v3f3263 ; GCN: bb.1 (%ir-block.0):64 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $vgpr265 ; GCN-NEXT: {{ $}}66 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr067 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr168 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr269 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub270 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vreg_96 = STRICT_WWM [[REG_SEQUENCE]], implicit $exec71 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub072 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub173 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub274 ; GCN-NEXT: $vgpr0 = COPY [[COPY3]]75 ; GCN-NEXT: $vgpr1 = COPY [[COPY4]]76 ; GCN-NEXT: $vgpr2 = COPY [[COPY5]]77 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr278 %ret = call <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float> %val)79 ret <3 x float> %ret80}81 82define amdgpu_ps float @strict_wwm_f32(float %val) {83 ; GCN-LABEL: name: strict_wwm_f3284 ; GCN: bb.1 (%ir-block.0):85 ; GCN-NEXT: liveins: $vgpr086 ; GCN-NEXT: {{ $}}87 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr088 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vgpr_32 = STRICT_WWM [[COPY]], implicit $exec89 ; GCN-NEXT: $vgpr0 = COPY [[STRICT_WWM]]90 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr091 %ret = call float @llvm.amdgcn.strict.wwm.f32(float %val)92 ret float %ret93}94 95define amdgpu_ps float @strict_wwm_v2f16(float %arg) {96 ; GCN-LABEL: name: strict_wwm_v2f1697 ; GCN: bb.1 (%ir-block.0):98 ; GCN-NEXT: liveins: $vgpr099 ; GCN-NEXT: {{ $}}100 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0101 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vgpr_32 = STRICT_WWM [[COPY]], implicit $exec102 ; GCN-NEXT: $vgpr0 = COPY [[STRICT_WWM]]103 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0104 %val = bitcast float %arg to <2 x half>105 %ret = call <2 x half> @llvm.amdgcn.strict.wwm.v2f16(<2 x half> %val)106 %bc = bitcast <2 x half> %ret to float107 ret float %bc108}109 110define amdgpu_ps <2 x float> @strict_wwm_f64(double %val) {111 ; GCN-LABEL: name: strict_wwm_f64112 ; GCN: bb.1 (%ir-block.0):113 ; GCN-NEXT: liveins: $vgpr0, $vgpr1114 ; GCN-NEXT: {{ $}}115 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0116 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1117 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1118 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vreg_64 = STRICT_WWM [[REG_SEQUENCE]], implicit $exec119 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub0120 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub1121 ; GCN-NEXT: $vgpr0 = COPY [[COPY2]]122 ; GCN-NEXT: $vgpr1 = COPY [[COPY3]]123 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1124 %ret = call double @llvm.amdgcn.strict.wwm.f64(double %val)125 %bitcast = bitcast double %ret to <2 x float>126 ret <2 x float> %bitcast127}128 129; TODO130; define amdgpu_ps float @strict_wwm_i1_vcc(float %val) {131; %vcc = fcmp oeq float %val, 0.0132; %ret = call i1 @llvm.amdgcn.strict.wwm.i1(i1 %vcc)133; %select = select i1 %ret, float 1.0, float 0.0134; ret float %select135; }136 137define amdgpu_ps <3 x float> @strict_wwm_v3f32(<3 x float> %val) {138 ; GCN-LABEL: name: strict_wwm_v3f32139 ; GCN: bb.1 (%ir-block.0):140 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2141 ; GCN-NEXT: {{ $}}142 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0143 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1144 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2145 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2146 ; GCN-NEXT: [[STRICT_WWM:%[0-9]+]]:vreg_96 = STRICT_WWM [[REG_SEQUENCE]], implicit $exec147 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub0148 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub1149 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[STRICT_WWM]].sub2150 ; GCN-NEXT: $vgpr0 = COPY [[COPY3]]151 ; GCN-NEXT: $vgpr1 = COPY [[COPY4]]152 ; GCN-NEXT: $vgpr2 = COPY [[COPY5]]153 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2154 %ret = call <3 x float> @llvm.amdgcn.strict.wwm.v3f32(<3 x float> %val)155 ret <3 x float> %ret156}157 158declare i1 @llvm.amdgcn.wwm.i1(i1) #0159declare float @llvm.amdgcn.wwm.f32(float) #0160declare <2 x half> @llvm.amdgcn.wwm.v2f16(<2 x half>) #0161declare <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float>) #0162declare double @llvm.amdgcn.wwm.f64(double) #0163declare i1 @llvm.amdgcn.strict.wwm.i1(i1) #0164declare float @llvm.amdgcn.strict.wwm.f32(float) #0165declare <2 x half> @llvm.amdgcn.strict.wwm.v2f16(<2 x half>) #0166declare <3 x float> @llvm.amdgcn.strict.wwm.v3f32(<3 x float>) #0167declare double @llvm.amdgcn.strict.wwm.f64(double) #0168 169attributes #0 = { nounwind readnone speculatable }170