94 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; FIXME: Test should be redundant with constant-address-space-32bit.ll6 7; It's important to check with gfx8 and gfx9 to check access through global and flat.8 9; Custom lowering needs to swap out the MMO address space10define amdgpu_ps float @load_constant32bit_vgpr_offset(i32 %arg) {11; GFX6-LABEL: load_constant32bit_vgpr_offset:12; GFX6: ; %bb.0: ; %entry13; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v014; GFX6-NEXT: s_mov_b32 s2, 015; GFX6-NEXT: v_mov_b32_e32 v1, 016; GFX6-NEXT: s_mov_b32 s3, 0xf00017; GFX6-NEXT: s_mov_b64 s[0:1], 018; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr6419; GFX6-NEXT: s_waitcnt vmcnt(0)20; GFX6-NEXT: ; return to shader part epilog21;22; GFX8-LABEL: load_constant32bit_vgpr_offset:23; GFX8: ; %bb.0: ; %entry24; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v025; GFX8-NEXT: v_mov_b32_e32 v1, 026; GFX8-NEXT: flat_load_dword v0, v[0:1]27; GFX8-NEXT: s_waitcnt vmcnt(0)28; GFX8-NEXT: ; return to shader part epilog29;30; GFX9-LABEL: load_constant32bit_vgpr_offset:31; GFX9: ; %bb.0: ; %entry32; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v033; GFX9-NEXT: v_mov_b32_e32 v1, 034; GFX9-NEXT: global_load_dword v0, v[0:1], off35; GFX9-NEXT: s_waitcnt vmcnt(0)36; GFX9-NEXT: ; return to shader part epilog37entry:38 %gep = getelementptr <{ [4294967295 x float] }>, ptr addrspace(6) null, i32 0, i32 0, i32 %arg39 %load = load float, ptr addrspace(6) %gep, align 440 ret float %load41}42 43define amdgpu_ps i32 @load_constant32bit_sgpr_offset(i32 inreg %arg) {44; GCN-LABEL: load_constant32bit_sgpr_offset:45; GCN: ; %bb.0: ; %entry46; GCN-NEXT: s_lshl_b32 s0, s0, 247; GCN-NEXT: s_mov_b32 s1, 048; GCN-NEXT: s_load_dword s0, s[0:1], 0x049; GCN-NEXT: s_waitcnt lgkmcnt(0)50; GCN-NEXT: ; return to shader part epilog51entry:52 %gep = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(6) null, i32 0, i32 0, i32 %arg53 %load = load i32, ptr addrspace(6) %gep, align 454 ret i32 %load55}56 57; This gets split during regbankselect58define amdgpu_ps <8 x float> @load_constant32bit_vgpr_v8f32(ptr addrspace(6) %arg) {59; GFX6-LABEL: load_constant32bit_vgpr_v8f32:60; GFX6: ; %bb.0: ; %entry61; GFX6-NEXT: v_mov_b32_e32 v4, v062; GFX6-NEXT: s_mov_b32 s2, 063; GFX6-NEXT: v_mov_b32_e32 v5, 064; GFX6-NEXT: s_mov_b32 s3, 0xf00065; GFX6-NEXT: s_mov_b64 s[0:1], 066; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr6467; GFX6-NEXT: buffer_load_dwordx4 v[4:7], v[4:5], s[0:3], 0 addr64 offset:1668; GFX6-NEXT: s_waitcnt vmcnt(0)69; GFX6-NEXT: ; return to shader part epilog70;71; GFX8-LABEL: load_constant32bit_vgpr_v8f32:72; GFX8: ; %bb.0: ; %entry73; GFX8-NEXT: v_mov_b32_e32 v4, v074; GFX8-NEXT: v_mov_b32_e32 v5, 075; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[4:5]76; GFX8-NEXT: v_add_u32_e32 v4, vcc, 16, v477; GFX8-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, vcc78; GFX8-NEXT: flat_load_dwordx4 v[4:7], v[4:5]79; GFX8-NEXT: s_waitcnt vmcnt(0)80; GFX8-NEXT: ; return to shader part epilog81;82; GFX9-LABEL: load_constant32bit_vgpr_v8f32:83; GFX9: ; %bb.0: ; %entry84; GFX9-NEXT: v_mov_b32_e32 v8, v085; GFX9-NEXT: v_mov_b32_e32 v9, 086; GFX9-NEXT: global_load_dwordx4 v[0:3], v[8:9], off87; GFX9-NEXT: global_load_dwordx4 v[4:7], v[8:9], off offset:1688; GFX9-NEXT: s_waitcnt vmcnt(0)89; GFX9-NEXT: ; return to shader part epilog90entry:91 %load = load <8 x float>, ptr addrspace(6) %arg, align 3292 ret <8 x float> %load93}94