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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+unaligned-access-mode < %s | FileCheck --check-prefixes=GFX11 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+unaligned-access-mode -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX12,GFX12-True16 %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+unaligned-access-mode -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX12,GFX12-NoTrue16 %s5 6; global address space, addrspace(1)7 8; gfx12, true16 is S16 16-bit load9; gfx12, without true 16 is S32 16-bit any-extending load10define amdgpu_ps void @load_uniform_P1_i16_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {11; GFX11-LABEL: load_uniform_P1_i16_gfx12:12; GFX11: ; %bb.0:13; GFX11-NEXT: v_mov_b32_e32 v2, 014; GFX11-NEXT: global_load_d16_b16 v2, v2, s[0:1]15; GFX11-NEXT: s_waitcnt vmcnt(0)16; GFX11-NEXT: global_store_b16 v[0:1], v2, off17; GFX11-NEXT: s_endpgm18;19; GFX12-True16-LABEL: load_uniform_P1_i16_gfx12:20; GFX12-True16: ; %bb.0:21; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x022; GFX12-True16-NEXT: s_wait_kmcnt 0x023; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s024; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off25; GFX12-True16-NEXT: s_endpgm26;27; GFX12-NoTrue16-LABEL: load_uniform_P1_i16_gfx12:28; GFX12-NoTrue16: ; %bb.0:29; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x030; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x031; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s032; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off33; GFX12-NoTrue16-NEXT: s_endpgm34 %a = load i16, ptr addrspace(1) %ptra35 store i16 %a, ptr addrspace(1) %out36 ret void37}38 39; gfx11, and older true16 is S16 16-bit load40; gfx11, and older without true 16 is S32 16-bit any-extending load41; both cases require align 4 and uniform mmo to widen mmo to 32-bit load42define amdgpu_ps void @load_uniform_P1_i16_align4_widen_mmo_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {43; GFX11-LABEL: load_uniform_P1_i16_align4_widen_mmo_gfx11:44; GFX11: ; %bb.0:45; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x046; GFX11-NEXT: s_waitcnt lgkmcnt(0)47; GFX11-NEXT: v_mov_b16_e32 v2.l, s048; GFX11-NEXT: global_store_b16 v[0:1], v2, off49; GFX11-NEXT: s_endpgm50;51; GFX12-True16-LABEL: load_uniform_P1_i16_align4_widen_mmo_gfx11:52; GFX12-True16: ; %bb.0:53; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x054; GFX12-True16-NEXT: s_wait_kmcnt 0x055; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s056; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off57; GFX12-True16-NEXT: s_endpgm58;59; GFX12-NoTrue16-LABEL: load_uniform_P1_i16_align4_widen_mmo_gfx11:60; GFX12-NoTrue16: ; %bb.0:61; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x062; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x063; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s064; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off65; GFX12-NoTrue16-NEXT: s_endpgm66 %a = load i16, ptr addrspace(1) %ptra, align 467 store i16 %a, ptr addrspace(1) %out68 ret void69}70 71; gfx12, S32 8-bit anyextending load, no difference regarding true 1672define amdgpu_ps void @load_uniform_P1_i8_any_extending_load(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {73; GFX11-LABEL: load_uniform_P1_i8_any_extending_load:74; GFX11: ; %bb.0:75; GFX11-NEXT: v_mov_b32_e32 v2, 076; GFX11-NEXT: global_load_u8 v2, v2, s[0:1]77; GFX11-NEXT: s_waitcnt vmcnt(0)78; GFX11-NEXT: global_store_b8 v[0:1], v2, off79; GFX11-NEXT: s_endpgm80;81; GFX12-LABEL: load_uniform_P1_i8_any_extending_load:82; GFX12: ; %bb.0:83; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x084; GFX12-NEXT: s_wait_kmcnt 0x085; GFX12-NEXT: v_mov_b32_e32 v2, s086; GFX12-NEXT: global_store_b8 v[0:1], v2, off87; GFX12-NEXT: s_endpgm88 %a = load i8, ptr addrspace(1) %ptra89 store i8 %a, ptr addrspace(1) %out90 ret void91}92 93; gfx11 and older, S32 8-bit any-extending load, no difference regarding true 1694define amdgpu_ps void @load_uniform_P1_i8_any_extending_load_align4_widen_mmo_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {95; GFX11-LABEL: load_uniform_P1_i8_any_extending_load_align4_widen_mmo_gfx11:96; GFX11: ; %bb.0:97; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x098; GFX11-NEXT: s_waitcnt lgkmcnt(0)99; GFX11-NEXT: v_mov_b32_e32 v2, s0100; GFX11-NEXT: global_store_b8 v[0:1], v2, off101; GFX11-NEXT: s_endpgm102;103; GFX12-LABEL: load_uniform_P1_i8_any_extending_load_align4_widen_mmo_gfx11:104; GFX12: ; %bb.0:105; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0106; GFX12-NEXT: s_wait_kmcnt 0x0107; GFX12-NEXT: v_mov_b32_e32 v2, s0108; GFX12-NEXT: global_store_b8 v[0:1], v2, off109; GFX12-NEXT: s_endpgm110 %a = load i8, ptr addrspace(1) %ptra, align 4111 store i8 %a, ptr addrspace(1) %out112 ret void113}114 115define amdgpu_ps void @load_uniform_P1_i32(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {116; GFX11-LABEL: load_uniform_P1_i32:117; GFX11: ; %bb.0:118; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0119; GFX11-NEXT: s_waitcnt lgkmcnt(0)120; GFX11-NEXT: v_mov_b32_e32 v2, s0121; GFX11-NEXT: global_store_b32 v[0:1], v2, off122; GFX11-NEXT: s_endpgm123;124; GFX12-LABEL: load_uniform_P1_i32:125; GFX12: ; %bb.0:126; GFX12-NEXT: s_load_b32 s0, s[0:1], 0x0127; GFX12-NEXT: s_wait_kmcnt 0x0128; GFX12-NEXT: v_mov_b32_e32 v2, s0129; GFX12-NEXT: global_store_b32 v[0:1], v2, off130; GFX12-NEXT: s_endpgm131 %a = load i32, ptr addrspace(1) %ptra132 store i32 %a, ptr addrspace(1) %out133 ret void134}135 136define amdgpu_ps void @load_uniform_P1_v2i32(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {137; GFX11-LABEL: load_uniform_P1_v2i32:138; GFX11: ; %bb.0:139; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0140; GFX11-NEXT: s_waitcnt lgkmcnt(0)141; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0142; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off143; GFX11-NEXT: s_endpgm144;145; GFX12-LABEL: load_uniform_P1_v2i32:146; GFX12: ; %bb.0:147; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0148; GFX12-NEXT: s_wait_kmcnt 0x0149; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0150; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off151; GFX12-NEXT: s_endpgm152 %a = load <2 x i32>, ptr addrspace(1) %ptra153 store <2 x i32> %a, ptr addrspace(1) %out154 ret void155}156 157; gfx11, S96 load align 16(default) to load S128158define amdgpu_ps void @load_uniform_P1_v3i32(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {159; GFX11-LABEL: load_uniform_P1_v3i32:160; GFX11: ; %bb.0:161; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0162; GFX11-NEXT: s_waitcnt lgkmcnt(0)163; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1164; GFX11-NEXT: v_mov_b32_e32 v2, s0165; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off166; GFX11-NEXT: s_endpgm167;168; GFX12-LABEL: load_uniform_P1_v3i32:169; GFX12: ; %bb.0:170; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0171; GFX12-NEXT: s_wait_kmcnt 0x0172; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1173; GFX12-NEXT: v_mov_b32_e32 v2, s0174; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off175; GFX12-NEXT: s_endpgm176 %a = load <3 x i32>, ptr addrspace(1) %ptra177 store <3 x i32> %a, ptr addrspace(1) %out178 ret void179}180 181; gfx11, S96 load align 4 to load S64 + load S32182define amdgpu_ps void @load_uniform_P1_v3i32_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {183; GFX11-LABEL: load_uniform_P1_v3i32_align4_gfx11:184; GFX11: ; %bb.0:185; GFX11-NEXT: s_clause 0x1186; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0187; GFX11-NEXT: s_load_b32 s6, s[0:1], 0x8188; GFX11-NEXT: s_waitcnt lgkmcnt(0)189; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5190; GFX11-NEXT: v_mov_b32_e32 v4, s6191; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off192; GFX11-NEXT: s_endpgm193;194; GFX12-LABEL: load_uniform_P1_v3i32_align4_gfx11:195; GFX12: ; %bb.0:196; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0197; GFX12-NEXT: s_wait_kmcnt 0x0198; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1199; GFX12-NEXT: v_mov_b32_e32 v2, s0200; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off201; GFX12-NEXT: s_endpgm202 %a = load <3 x i32>, ptr addrspace(1) %ptra, align 4203 store <3 x i32> %a, ptr addrspace(1) %out204 ret void205}206 207define amdgpu_ps void @load_uniform_P1_v4i32(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {208; GFX11-LABEL: load_uniform_P1_v4i32:209; GFX11: ; %bb.0:210; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0211; GFX11-NEXT: s_waitcnt lgkmcnt(0)212; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2213; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0214; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off215; GFX11-NEXT: s_endpgm216;217; GFX12-LABEL: load_uniform_P1_v4i32:218; GFX12: ; %bb.0:219; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x0220; GFX12-NEXT: s_wait_kmcnt 0x0221; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2222; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0223; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off224; GFX12-NEXT: s_endpgm225 %a = load <4 x i32>, ptr addrspace(1) %ptra226 store <4 x i32> %a, ptr addrspace(1) %out227 ret void228}229 230define amdgpu_ps void @load_uniform_P1_v8i32(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {231; GFX11-LABEL: load_uniform_P1_v8i32:232; GFX11: ; %bb.0:233; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x0234; GFX11-NEXT: s_waitcnt lgkmcnt(0)235; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2236; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0237; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6238; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4239; GFX11-NEXT: s_clause 0x1240; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off241; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16242; GFX11-NEXT: s_endpgm243;244; GFX12-LABEL: load_uniform_P1_v8i32:245; GFX12: ; %bb.0:246; GFX12-NEXT: s_load_b256 s[0:7], s[0:1], 0x0247; GFX12-NEXT: s_wait_kmcnt 0x0248; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2249; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0250; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6251; GFX12-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4252; GFX12-NEXT: s_clause 0x1253; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off254; GFX12-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16255; GFX12-NEXT: s_endpgm256 %a = load <8 x i32>, ptr addrspace(1) %ptra257 store <8 x i32> %a, ptr addrspace(1) %out258 ret void259}260 261define amdgpu_ps void @load_uniform_P1_v16i32(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {262; GFX11-LABEL: load_uniform_P1_v16i32:263; GFX11: ; %bb.0:264; GFX11-NEXT: s_load_b512 s[0:15], s[0:1], 0x0265; GFX11-NEXT: s_waitcnt lgkmcnt(0)266; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2267; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0268; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6269; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4270; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10271; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8272; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14273; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12274; GFX11-NEXT: s_clause 0x3275; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off276; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16277; GFX11-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32278; GFX11-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48279; GFX11-NEXT: s_endpgm280;281; GFX12-LABEL: load_uniform_P1_v16i32:282; GFX12: ; %bb.0:283; GFX12-NEXT: s_load_b512 s[0:15], s[0:1], 0x0284; GFX12-NEXT: s_wait_kmcnt 0x0285; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2286; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0287; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6288; GFX12-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4289; GFX12-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10290; GFX12-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8291; GFX12-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14292; GFX12-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12293; GFX12-NEXT: s_clause 0x3294; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off295; GFX12-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16296; GFX12-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32297; GFX12-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48298; GFX12-NEXT: s_endpgm299 %a = load <16 x i32>, ptr addrspace(1) %ptra300 store <16 x i32> %a, ptr addrspace(1) %out301 ret void302}303 304; constant address space, addrspace(4)305 306define amdgpu_ps void @load_uniform_P4_i16_gfx12(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {307; GFX11-LABEL: load_uniform_P4_i16_gfx12:308; GFX11: ; %bb.0:309; GFX11-NEXT: v_mov_b32_e32 v2, 0310; GFX11-NEXT: global_load_d16_b16 v2, v2, s[0:1]311; GFX11-NEXT: s_waitcnt vmcnt(0)312; GFX11-NEXT: global_store_b16 v[0:1], v2, off313; GFX11-NEXT: s_endpgm314;315; GFX12-True16-LABEL: load_uniform_P4_i16_gfx12:316; GFX12-True16: ; %bb.0:317; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0318; GFX12-True16-NEXT: s_wait_kmcnt 0x0319; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0320; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off321; GFX12-True16-NEXT: s_endpgm322;323; GFX12-NoTrue16-LABEL: load_uniform_P4_i16_gfx12:324; GFX12-NoTrue16: ; %bb.0:325; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0326; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0327; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0328; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off329; GFX12-NoTrue16-NEXT: s_endpgm330 %a = load i16, ptr addrspace(4) %ptra331 store i16 %a, ptr addrspace(1) %out332 ret void333}334 335define amdgpu_ps void @load_uniform_P4_i16_align4_widen_mmo_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {336; GFX11-LABEL: load_uniform_P4_i16_align4_widen_mmo_gfx11:337; GFX11: ; %bb.0:338; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0339; GFX11-NEXT: s_waitcnt lgkmcnt(0)340; GFX11-NEXT: v_mov_b16_e32 v2.l, s0341; GFX11-NEXT: global_store_b16 v[0:1], v2, off342; GFX11-NEXT: s_endpgm343;344; GFX12-True16-LABEL: load_uniform_P4_i16_align4_widen_mmo_gfx11:345; GFX12-True16: ; %bb.0:346; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0347; GFX12-True16-NEXT: s_wait_kmcnt 0x0348; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0349; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off350; GFX12-True16-NEXT: s_endpgm351;352; GFX12-NoTrue16-LABEL: load_uniform_P4_i16_align4_widen_mmo_gfx11:353; GFX12-NoTrue16: ; %bb.0:354; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0355; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0356; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0357; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off358; GFX12-NoTrue16-NEXT: s_endpgm359 %a = load i16, ptr addrspace(4) %ptra, align 4360 store i16 %a, ptr addrspace(1) %out361 ret void362}363 364; gfx12, S32 8-bit anyextending load, no difference regarding true 16365define amdgpu_ps void @load_uniform_P4_i8_any_extending_load(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {366; GFX11-LABEL: load_uniform_P4_i8_any_extending_load:367; GFX11: ; %bb.0:368; GFX11-NEXT: v_mov_b32_e32 v2, 0369; GFX11-NEXT: global_load_u8 v2, v2, s[0:1]370; GFX11-NEXT: s_waitcnt vmcnt(0)371; GFX11-NEXT: global_store_b8 v[0:1], v2, off372; GFX11-NEXT: s_endpgm373;374; GFX12-LABEL: load_uniform_P4_i8_any_extending_load:375; GFX12: ; %bb.0:376; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0377; GFX12-NEXT: s_wait_kmcnt 0x0378; GFX12-NEXT: v_mov_b32_e32 v2, s0379; GFX12-NEXT: global_store_b8 v[0:1], v2, off380; GFX12-NEXT: s_endpgm381 %a = load i8, ptr addrspace(4) %ptra382 store i8 %a, ptr addrspace(1) %out383 ret void384}385 386; gfx11 and older, S32 8-bit any-extending load, no difference regarding true 16387define amdgpu_ps void @load_uniform_P4_i8_any_extending_load_align4_widen_mmo_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {388; GFX11-LABEL: load_uniform_P4_i8_any_extending_load_align4_widen_mmo_gfx11:389; GFX11: ; %bb.0:390; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0391; GFX11-NEXT: s_waitcnt lgkmcnt(0)392; GFX11-NEXT: v_mov_b32_e32 v2, s0393; GFX11-NEXT: global_store_b8 v[0:1], v2, off394; GFX11-NEXT: s_endpgm395;396; GFX12-LABEL: load_uniform_P4_i8_any_extending_load_align4_widen_mmo_gfx11:397; GFX12: ; %bb.0:398; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0399; GFX12-NEXT: s_wait_kmcnt 0x0400; GFX12-NEXT: v_mov_b32_e32 v2, s0401; GFX12-NEXT: global_store_b8 v[0:1], v2, off402; GFX12-NEXT: s_endpgm403 %a = load i8, ptr addrspace(4) %ptra, align 4404 store i8 %a, ptr addrspace(1) %out405 ret void406}407 408define amdgpu_ps void @load_uniform_P4_i32(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {409; GFX11-LABEL: load_uniform_P4_i32:410; GFX11: ; %bb.0:411; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0412; GFX11-NEXT: s_waitcnt lgkmcnt(0)413; GFX11-NEXT: v_mov_b32_e32 v2, s0414; GFX11-NEXT: global_store_b32 v[0:1], v2, off415; GFX11-NEXT: s_endpgm416;417; GFX12-LABEL: load_uniform_P4_i32:418; GFX12: ; %bb.0:419; GFX12-NEXT: s_load_b32 s0, s[0:1], 0x0420; GFX12-NEXT: s_wait_kmcnt 0x0421; GFX12-NEXT: v_mov_b32_e32 v2, s0422; GFX12-NEXT: global_store_b32 v[0:1], v2, off423; GFX12-NEXT: s_endpgm424 %a = load i32, ptr addrspace(4) %ptra425 store i32 %a, ptr addrspace(1) %out426 ret void427}428 429define amdgpu_ps void @load_uniform_P4_v2i32(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {430; GFX11-LABEL: load_uniform_P4_v2i32:431; GFX11: ; %bb.0:432; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0433; GFX11-NEXT: s_waitcnt lgkmcnt(0)434; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0435; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off436; GFX11-NEXT: s_endpgm437;438; GFX12-LABEL: load_uniform_P4_v2i32:439; GFX12: ; %bb.0:440; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0441; GFX12-NEXT: s_wait_kmcnt 0x0442; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0443; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off444; GFX12-NEXT: s_endpgm445 %a = load <2 x i32>, ptr addrspace(4) %ptra446 store <2 x i32> %a, ptr addrspace(1) %out447 ret void448}449 450; gfx11, S96 load align 16(default) to load S128451define amdgpu_ps void @load_uniform_P4_v3i32(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {452; GFX11-LABEL: load_uniform_P4_v3i32:453; GFX11: ; %bb.0:454; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0455; GFX11-NEXT: s_waitcnt lgkmcnt(0)456; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1457; GFX11-NEXT: v_mov_b32_e32 v2, s0458; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off459; GFX11-NEXT: s_endpgm460;461; GFX12-LABEL: load_uniform_P4_v3i32:462; GFX12: ; %bb.0:463; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0464; GFX12-NEXT: s_wait_kmcnt 0x0465; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1466; GFX12-NEXT: v_mov_b32_e32 v2, s0467; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off468; GFX12-NEXT: s_endpgm469 %a = load <3 x i32>, ptr addrspace(4) %ptra470 store <3 x i32> %a, ptr addrspace(1) %out471 ret void472}473 474; gfx11, S96 load align 4 to load S64 + load S32475define amdgpu_ps void @load_uniform_P4_v3i32_align4_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {476; GFX11-LABEL: load_uniform_P4_v3i32_align4_gfx11:477; GFX11: ; %bb.0:478; GFX11-NEXT: s_clause 0x1479; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0480; GFX11-NEXT: s_load_b32 s6, s[0:1], 0x8481; GFX11-NEXT: s_waitcnt lgkmcnt(0)482; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5483; GFX11-NEXT: v_mov_b32_e32 v4, s6484; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off485; GFX11-NEXT: s_endpgm486;487; GFX12-LABEL: load_uniform_P4_v3i32_align4_gfx11:488; GFX12: ; %bb.0:489; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0490; GFX12-NEXT: s_wait_kmcnt 0x0491; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1492; GFX12-NEXT: v_mov_b32_e32 v2, s0493; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off494; GFX12-NEXT: s_endpgm495 %a = load <3 x i32>, ptr addrspace(4) %ptra, align 4496 store <3 x i32> %a, ptr addrspace(1) %out497 ret void498}499 500 501define amdgpu_ps void @load_uniform_P4_v4i32(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {502; GFX11-LABEL: load_uniform_P4_v4i32:503; GFX11: ; %bb.0:504; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0505; GFX11-NEXT: s_waitcnt lgkmcnt(0)506; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2507; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0508; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off509; GFX11-NEXT: s_endpgm510;511; GFX12-LABEL: load_uniform_P4_v4i32:512; GFX12: ; %bb.0:513; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x0514; GFX12-NEXT: s_wait_kmcnt 0x0515; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2516; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0517; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off518; GFX12-NEXT: s_endpgm519 %a = load <4 x i32>, ptr addrspace(4) %ptra520 store <4 x i32> %a, ptr addrspace(1) %out521 ret void522}523 524define amdgpu_ps void @load_uniform_P4_v8i32(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {525; GFX11-LABEL: load_uniform_P4_v8i32:526; GFX11: ; %bb.0:527; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x0528; GFX11-NEXT: s_waitcnt lgkmcnt(0)529; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2530; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0531; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6532; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4533; GFX11-NEXT: s_clause 0x1534; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off535; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16536; GFX11-NEXT: s_endpgm537;538; GFX12-LABEL: load_uniform_P4_v8i32:539; GFX12: ; %bb.0:540; GFX12-NEXT: s_load_b256 s[0:7], s[0:1], 0x0541; GFX12-NEXT: s_wait_kmcnt 0x0542; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2543; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0544; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6545; GFX12-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4546; GFX12-NEXT: s_clause 0x1547; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off548; GFX12-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16549; GFX12-NEXT: s_endpgm550 %a = load <8 x i32>, ptr addrspace(4) %ptra551 store <8 x i32> %a, ptr addrspace(1) %out552 ret void553}554 555define amdgpu_ps void @load_uniform_P4_v16i32(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {556; GFX11-LABEL: load_uniform_P4_v16i32:557; GFX11: ; %bb.0:558; GFX11-NEXT: s_load_b512 s[0:15], s[0:1], 0x0559; GFX11-NEXT: s_waitcnt lgkmcnt(0)560; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2561; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0562; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6563; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4564; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10565; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8566; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14567; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12568; GFX11-NEXT: s_clause 0x3569; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off570; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16571; GFX11-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32572; GFX11-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48573; GFX11-NEXT: s_endpgm574;575; GFX12-LABEL: load_uniform_P4_v16i32:576; GFX12: ; %bb.0:577; GFX12-NEXT: s_load_b512 s[0:15], s[0:1], 0x0578; GFX12-NEXT: s_wait_kmcnt 0x0579; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2580; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0581; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6582; GFX12-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4583; GFX12-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10584; GFX12-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8585; GFX12-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14586; GFX12-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12587; GFX12-NEXT: s_clause 0x3588; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off589; GFX12-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16590; GFX12-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32591; GFX12-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48592; GFX12-NEXT: s_endpgm593 %a = load <16 x i32>, ptr addrspace(4) %ptra594 store <16 x i32> %a, ptr addrspace(1) %out595 ret void596}597