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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX11 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX12 %s4 5define amdgpu_ps void @sextload_and_zextload_P1_i8_not_uniform_mmo_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) inreg %ptrb, ptr addrspace(1) %out) {6; GFX11-LABEL: sextload_and_zextload_P1_i8_not_uniform_mmo_gfx12:7; GFX11: ; %bb.0:8; GFX11-NEXT: v_mov_b32_e32 v2, 09; GFX11-NEXT: global_load_i8 v3, v2, s[0:1] glc dlc10; GFX11-NEXT: s_waitcnt vmcnt(0)11; GFX11-NEXT: global_load_u8 v2, v2, s[2:3] glc dlc12; GFX11-NEXT: s_waitcnt vmcnt(0)13; GFX11-NEXT: v_readfirstlane_b32 s0, v314; GFX11-NEXT: v_readfirstlane_b32 s1, v215; GFX11-NEXT: s_add_i32 s0, s0, s116; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)17; GFX11-NEXT: v_mov_b32_e32 v2, s018; GFX11-NEXT: global_store_b32 v[0:1], v2, off19; GFX11-NEXT: s_endpgm20;21; GFX12-LABEL: sextload_and_zextload_P1_i8_not_uniform_mmo_gfx12:22; GFX12: ; %bb.0:23; GFX12-NEXT: v_mov_b32_e32 v2, 024; GFX12-NEXT: global_load_i8 v3, v2, s[0:1] scope:SCOPE_SYS25; GFX12-NEXT: s_wait_loadcnt 0x026; GFX12-NEXT: global_load_u8 v2, v2, s[2:3] scope:SCOPE_SYS27; GFX12-NEXT: s_wait_loadcnt 0x028; GFX12-NEXT: v_readfirstlane_b32 s0, v329; GFX12-NEXT: v_readfirstlane_b32 s1, v230; GFX12-NEXT: s_add_co_i32 s0, s0, s131; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)32; GFX12-NEXT: v_mov_b32_e32 v2, s033; GFX12-NEXT: global_store_b32 v[0:1], v2, off34; GFX12-NEXT: s_endpgm35 %a = load volatile i8, ptr addrspace(1) %ptra36 %a32 = sext i8 %a to i3237 %b = load volatile i8, ptr addrspace(1) %ptrb38 %b32 = zext i8 %b to i3239 %res = add i32 %a32, %b3240 store i32 %res, ptr addrspace(1) %out41 ret void42}43 44define amdgpu_ps void @sextload_P1_i8_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) inreg %ptrb, ptr addrspace(1) %out) {45; GFX11-LABEL: sextload_P1_i8_not_align4_or_not_uniform_mmo_gfx11:46; GFX11: ; %bb.0:47; GFX11-NEXT: v_mov_b32_e32 v2, 048; GFX11-NEXT: s_clause 0x149; GFX11-NEXT: global_load_i8 v3, v2, s[0:1]50; GFX11-NEXT: global_load_i8 v2, v2, s[2:3] glc dlc51; GFX11-NEXT: s_waitcnt vmcnt(0)52; GFX11-NEXT: v_readfirstlane_b32 s0, v353; GFX11-NEXT: v_readfirstlane_b32 s1, v254; GFX11-NEXT: s_add_i32 s0, s0, s155; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)56; GFX11-NEXT: v_mov_b32_e32 v2, s057; GFX11-NEXT: global_store_b32 v[0:1], v2, off58; GFX11-NEXT: s_endpgm59;60; GFX12-LABEL: sextload_P1_i8_not_align4_or_not_uniform_mmo_gfx11:61; GFX12: ; %bb.0:62; GFX12-NEXT: v_mov_b32_e32 v2, 063; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x064; GFX12-NEXT: global_load_i8 v2, v2, s[2:3] scope:SCOPE_SYS65; GFX12-NEXT: s_wait_loadcnt 0x066; GFX12-NEXT: v_readfirstlane_b32 s1, v267; GFX12-NEXT: s_wait_kmcnt 0x068; GFX12-NEXT: s_add_co_i32 s0, s0, s169; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)70; GFX12-NEXT: v_mov_b32_e32 v2, s071; GFX12-NEXT: global_store_b32 v[0:1], v2, off72; GFX12-NEXT: s_endpgm73 %a = load i8, ptr addrspace(1) %ptra74 %a32 = sext i8 %a to i3275 %b = load volatile i8, ptr addrspace(1) %ptrb, align 476 %b32 = sext i8 %b to i3277 %res = add i32 %a32, %b3278 store i32 %res, ptr addrspace(1) %out79 ret void80}81 82define amdgpu_ps void @zextload_P1_i8_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) inreg %ptrb, ptr addrspace(1) %out) {83; GFX11-LABEL: zextload_P1_i8_not_align4_or_not_uniform_mmo_gfx11:84; GFX11: ; %bb.0:85; GFX11-NEXT: v_mov_b32_e32 v2, 086; GFX11-NEXT: s_clause 0x187; GFX11-NEXT: global_load_u8 v3, v2, s[0:1]88; GFX11-NEXT: global_load_u8 v2, v2, s[2:3] glc dlc89; GFX11-NEXT: s_waitcnt vmcnt(0)90; GFX11-NEXT: v_readfirstlane_b32 s0, v391; GFX11-NEXT: v_readfirstlane_b32 s1, v292; GFX11-NEXT: s_add_i32 s0, s0, s193; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)94; GFX11-NEXT: v_mov_b32_e32 v2, s095; GFX11-NEXT: global_store_b32 v[0:1], v2, off96; GFX11-NEXT: s_endpgm97;98; GFX12-LABEL: zextload_P1_i8_not_align4_or_not_uniform_mmo_gfx11:99; GFX12: ; %bb.0:100; GFX12-NEXT: v_mov_b32_e32 v2, 0101; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0102; GFX12-NEXT: global_load_u8 v2, v2, s[2:3] scope:SCOPE_SYS103; GFX12-NEXT: s_wait_loadcnt 0x0104; GFX12-NEXT: v_readfirstlane_b32 s1, v2105; GFX12-NEXT: s_wait_kmcnt 0x0106; GFX12-NEXT: s_add_co_i32 s0, s0, s1107; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)108; GFX12-NEXT: v_mov_b32_e32 v2, s0109; GFX12-NEXT: global_store_b32 v[0:1], v2, off110; GFX12-NEXT: s_endpgm111 %a = load i8, ptr addrspace(1) %ptra112 %a32 = zext i8 %a to i32113 %b = load volatile i8, ptr addrspace(1) %ptrb, align 4114 %b32 = zext i8 %b to i32115 %res = add i32 %a32, %b32116 store i32 %res, ptr addrspace(1) %out117 ret void118}119 120define amdgpu_ps void @sextload_P1_i16_not_natural_align_or_not_uniform_mmo_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) inreg %ptrb, ptr addrspace(1) %out) {121; GFX11-LABEL: sextload_P1_i16_not_natural_align_or_not_uniform_mmo_gfx12:122; GFX11: ; %bb.0:123; GFX11-NEXT: v_mov_b32_e32 v2, 0124; GFX11-NEXT: s_clause 0x1125; GFX11-NEXT: global_load_i16 v3, v2, s[0:1]126; GFX11-NEXT: global_load_i16 v2, v2, s[2:3] glc dlc127; GFX11-NEXT: s_waitcnt vmcnt(0)128; GFX11-NEXT: v_readfirstlane_b32 s0, v3129; GFX11-NEXT: v_readfirstlane_b32 s1, v2130; GFX11-NEXT: s_add_i32 s0, s0, s1131; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)132; GFX11-NEXT: v_mov_b32_e32 v2, s0133; GFX11-NEXT: global_store_b32 v[0:1], v2, off134; GFX11-NEXT: s_endpgm135;136; GFX12-LABEL: sextload_P1_i16_not_natural_align_or_not_uniform_mmo_gfx12:137; GFX12: ; %bb.0:138; GFX12-NEXT: v_mov_b32_e32 v2, 0139; GFX12-NEXT: s_clause 0x1140; GFX12-NEXT: global_load_i16 v3, v2, s[0:1]141; GFX12-NEXT: global_load_i16 v2, v2, s[2:3] scope:SCOPE_SYS142; GFX12-NEXT: s_wait_loadcnt 0x0143; GFX12-NEXT: v_readfirstlane_b32 s0, v3144; GFX12-NEXT: v_readfirstlane_b32 s1, v2145; GFX12-NEXT: s_add_co_i32 s0, s0, s1146; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)147; GFX12-NEXT: v_mov_b32_e32 v2, s0148; GFX12-NEXT: global_store_b32 v[0:1], v2, off149; GFX12-NEXT: s_endpgm150 %a = load i16, ptr addrspace(1) %ptra, align 1151 %a32 = sext i16 %a to i32152 %b = load volatile i16, ptr addrspace(1) %ptrb153 %b32 = sext i16 %b to i32154 %res = add i32 %a32, %b32155 store i32 %res, ptr addrspace(1) %out156 ret void157}158 159define amdgpu_ps void @sextload_P1_i16_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) inreg %ptrb, ptr addrspace(1) %out) {160; GFX11-LABEL: sextload_P1_i16_not_align4_or_not_uniform_mmo_gfx11:161; GFX11: ; %bb.0:162; GFX11-NEXT: v_mov_b32_e32 v2, 0163; GFX11-NEXT: s_clause 0x1164; GFX11-NEXT: global_load_i16 v3, v2, s[0:1]165; GFX11-NEXT: global_load_i16 v2, v2, s[2:3] glc dlc166; GFX11-NEXT: s_waitcnt vmcnt(0)167; GFX11-NEXT: v_readfirstlane_b32 s0, v3168; GFX11-NEXT: v_readfirstlane_b32 s1, v2169; GFX11-NEXT: s_add_i32 s0, s0, s1170; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)171; GFX11-NEXT: v_mov_b32_e32 v2, s0172; GFX11-NEXT: global_store_b32 v[0:1], v2, off173; GFX11-NEXT: s_endpgm174;175; GFX12-LABEL: sextload_P1_i16_not_align4_or_not_uniform_mmo_gfx11:176; GFX12: ; %bb.0:177; GFX12-NEXT: v_mov_b32_e32 v2, 0178; GFX12-NEXT: s_load_i16 s0, s[0:1], 0x0179; GFX12-NEXT: global_load_i16 v2, v2, s[2:3] scope:SCOPE_SYS180; GFX12-NEXT: s_wait_loadcnt 0x0181; GFX12-NEXT: v_readfirstlane_b32 s1, v2182; GFX12-NEXT: s_wait_kmcnt 0x0183; GFX12-NEXT: s_add_co_i32 s0, s0, s1184; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)185; GFX12-NEXT: v_mov_b32_e32 v2, s0186; GFX12-NEXT: global_store_b32 v[0:1], v2, off187; GFX12-NEXT: s_endpgm188 %a = load i16, ptr addrspace(1) %ptra189 %a32 = sext i16 %a to i32190 %b = load volatile i16, ptr addrspace(1) %ptrb, align 4191 %b32 = sext i16 %b to i32192 %res = add i32 %a32, %b32193 store i32 %res, ptr addrspace(1) %out194 ret void195}196 197define amdgpu_ps void @zextload_P1_i16_not_natural_align_or_not_uniform_mmo_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) inreg %ptrb, ptr addrspace(1) %out) {198; GFX11-LABEL: zextload_P1_i16_not_natural_align_or_not_uniform_mmo_gfx12:199; GFX11: ; %bb.0:200; GFX11-NEXT: v_mov_b32_e32 v2, 0201; GFX11-NEXT: s_clause 0x1202; GFX11-NEXT: global_load_u16 v3, v2, s[0:1]203; GFX11-NEXT: global_load_u16 v2, v2, s[2:3] glc dlc204; GFX11-NEXT: s_waitcnt vmcnt(0)205; GFX11-NEXT: v_readfirstlane_b32 s0, v3206; GFX11-NEXT: v_readfirstlane_b32 s1, v2207; GFX11-NEXT: s_add_i32 s0, s0, s1208; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)209; GFX11-NEXT: v_mov_b32_e32 v2, s0210; GFX11-NEXT: global_store_b32 v[0:1], v2, off211; GFX11-NEXT: s_endpgm212;213; GFX12-LABEL: zextload_P1_i16_not_natural_align_or_not_uniform_mmo_gfx12:214; GFX12: ; %bb.0:215; GFX12-NEXT: v_mov_b32_e32 v2, 0216; GFX12-NEXT: s_clause 0x1217; GFX12-NEXT: global_load_u16 v3, v2, s[0:1]218; GFX12-NEXT: global_load_u16 v2, v2, s[2:3] scope:SCOPE_SYS219; GFX12-NEXT: s_wait_loadcnt 0x0220; GFX12-NEXT: v_readfirstlane_b32 s0, v3221; GFX12-NEXT: v_readfirstlane_b32 s1, v2222; GFX12-NEXT: s_add_co_i32 s0, s0, s1223; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)224; GFX12-NEXT: v_mov_b32_e32 v2, s0225; GFX12-NEXT: global_store_b32 v[0:1], v2, off226; GFX12-NEXT: s_endpgm227 %a = load i16, ptr addrspace(1) %ptra, align 1228 %a32 = zext i16 %a to i32229 %b = load volatile i16, ptr addrspace(1) %ptrb230 %b32 = zext i16 %b to i32231 %res = add i32 %a32, %b32232 store i32 %res, ptr addrspace(1) %out233 ret void234}235 236define amdgpu_ps void @zextload_P1_i16_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) inreg %ptrb, ptr addrspace(1) %out) {237; GFX11-LABEL: zextload_P1_i16_not_align4_or_not_uniform_mmo_gfx11:238; GFX11: ; %bb.0:239; GFX11-NEXT: v_mov_b32_e32 v2, 0240; GFX11-NEXT: s_clause 0x1241; GFX11-NEXT: global_load_u16 v3, v2, s[0:1]242; GFX11-NEXT: global_load_u16 v2, v2, s[2:3] glc dlc243; GFX11-NEXT: s_waitcnt vmcnt(0)244; GFX11-NEXT: v_readfirstlane_b32 s0, v3245; GFX11-NEXT: v_readfirstlane_b32 s1, v2246; GFX11-NEXT: s_add_i32 s0, s0, s1247; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)248; GFX11-NEXT: v_mov_b32_e32 v2, s0249; GFX11-NEXT: global_store_b32 v[0:1], v2, off250; GFX11-NEXT: s_endpgm251;252; GFX12-LABEL: zextload_P1_i16_not_align4_or_not_uniform_mmo_gfx11:253; GFX12: ; %bb.0:254; GFX12-NEXT: v_mov_b32_e32 v2, 0255; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0256; GFX12-NEXT: global_load_u16 v2, v2, s[2:3] scope:SCOPE_SYS257; GFX12-NEXT: s_wait_loadcnt 0x0258; GFX12-NEXT: v_readfirstlane_b32 s1, v2259; GFX12-NEXT: s_wait_kmcnt 0x0260; GFX12-NEXT: s_add_co_i32 s0, s0, s1261; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)262; GFX12-NEXT: v_mov_b32_e32 v2, s0263; GFX12-NEXT: global_store_b32 v[0:1], v2, off264; GFX12-NEXT: s_endpgm265 %a = load i16, ptr addrspace(1) %ptra266 %a32 = zext i16 %a to i32267 %b = load volatile i16, ptr addrspace(1) %ptrb, align 4268 %b32 = zext i16 %b to i32269 %res = add i32 %a32, %b32270 store i32 %res, ptr addrspace(1) %out271 ret void272}273 274 275 276define amdgpu_ps void @sextload_and_zextload_P3_i8(ptr addrspace(3) inreg %ptra, ptr addrspace(3) inreg %ptrb, ptr addrspace(3) %out) {277; GFX11-LABEL: sextload_and_zextload_P3_i8:278; GFX11: ; %bb.0:279; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1280; GFX11-NEXT: ds_load_i8 v1, v1281; GFX11-NEXT: ds_load_u8 v2, v2282; GFX11-NEXT: s_waitcnt lgkmcnt(1)283; GFX11-NEXT: v_readfirstlane_b32 s0, v1284; GFX11-NEXT: s_waitcnt lgkmcnt(0)285; GFX11-NEXT: v_readfirstlane_b32 s1, v2286; GFX11-NEXT: s_add_i32 s0, s0, s1287; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)288; GFX11-NEXT: v_mov_b32_e32 v1, s0289; GFX11-NEXT: ds_store_b32 v0, v1290; GFX11-NEXT: s_endpgm291;292; GFX12-LABEL: sextload_and_zextload_P3_i8:293; GFX12: ; %bb.0:294; GFX12-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1295; GFX12-NEXT: ds_load_i8 v1, v1296; GFX12-NEXT: ds_load_u8 v2, v2297; GFX12-NEXT: s_wait_dscnt 0x1298; GFX12-NEXT: v_readfirstlane_b32 s0, v1299; GFX12-NEXT: s_wait_dscnt 0x0300; GFX12-NEXT: v_readfirstlane_b32 s1, v2301; GFX12-NEXT: s_add_co_i32 s0, s0, s1302; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)303; GFX12-NEXT: v_mov_b32_e32 v1, s0304; GFX12-NEXT: ds_store_b32 v0, v1305; GFX12-NEXT: s_endpgm306 %a = load volatile i8, ptr addrspace(3) %ptra307 %a32 = sext i8 %a to i32308 %b = load volatile i8, ptr addrspace(3) %ptrb309 %b32 = zext i8 %b to i32310 %res = add i32 %a32, %b32311 store i32 %res, ptr addrspace(3) %out312 ret void313}314 315define amdgpu_ps void @sextload_and_zextload_P3_i16(ptr addrspace(3) inreg %ptra, ptr addrspace(3) inreg %ptrb, ptr addrspace(3) %out) {316; GFX11-LABEL: sextload_and_zextload_P3_i16:317; GFX11: ; %bb.0:318; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1319; GFX11-NEXT: ds_load_i16 v1, v1320; GFX11-NEXT: ds_load_u16 v2, v2321; GFX11-NEXT: s_waitcnt lgkmcnt(1)322; GFX11-NEXT: v_readfirstlane_b32 s0, v1323; GFX11-NEXT: s_waitcnt lgkmcnt(0)324; GFX11-NEXT: v_readfirstlane_b32 s1, v2325; GFX11-NEXT: s_add_i32 s0, s0, s1326; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)327; GFX11-NEXT: v_mov_b32_e32 v1, s0328; GFX11-NEXT: ds_store_b32 v0, v1329; GFX11-NEXT: s_endpgm330;331; GFX12-LABEL: sextload_and_zextload_P3_i16:332; GFX12: ; %bb.0:333; GFX12-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1334; GFX12-NEXT: ds_load_i16 v1, v1335; GFX12-NEXT: ds_load_u16 v2, v2336; GFX12-NEXT: s_wait_dscnt 0x1337; GFX12-NEXT: v_readfirstlane_b32 s0, v1338; GFX12-NEXT: s_wait_dscnt 0x0339; GFX12-NEXT: v_readfirstlane_b32 s1, v2340; GFX12-NEXT: s_add_co_i32 s0, s0, s1341; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)342; GFX12-NEXT: v_mov_b32_e32 v1, s0343; GFX12-NEXT: ds_store_b32 v0, v1344; GFX12-NEXT: s_endpgm345 %a = load volatile i16, ptr addrspace(3) %ptra346 %a32 = sext i16 %a to i32347 %b = load volatile i16, ptr addrspace(3) %ptrb348 %b32 = zext i16 %b to i32349 %res = add i32 %a32, %b32350 store i32 %res, ptr addrspace(3) %out351 ret void352}353 354 355 356define amdgpu_ps void @sextload_and_zextload_P4_i8_not_uniform_mmo_gfx12(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {357; GFX11-LABEL: sextload_and_zextload_P4_i8_not_uniform_mmo_gfx12:358; GFX11: ; %bb.0:359; GFX11-NEXT: v_mov_b32_e32 v2, 0360; GFX11-NEXT: s_clause 0x1361; GFX11-NEXT: global_load_i8 v3, v2, s[0:1] glc dlc362; GFX11-NEXT: global_load_u8 v2, v2, s[2:3] glc dlc363; GFX11-NEXT: s_waitcnt vmcnt(1)364; GFX11-NEXT: v_readfirstlane_b32 s0, v3365; GFX11-NEXT: s_waitcnt vmcnt(0)366; GFX11-NEXT: v_readfirstlane_b32 s1, v2367; GFX11-NEXT: s_add_i32 s0, s0, s1368; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)369; GFX11-NEXT: v_mov_b32_e32 v2, s0370; GFX11-NEXT: global_store_b32 v[0:1], v2, off371; GFX11-NEXT: s_endpgm372;373; GFX12-LABEL: sextload_and_zextload_P4_i8_not_uniform_mmo_gfx12:374; GFX12: ; %bb.0:375; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x0376; GFX12-NEXT: s_load_u8 s1, s[2:3], 0x0377; GFX12-NEXT: s_wait_kmcnt 0x0378; GFX12-NEXT: s_add_co_i32 s0, s0, s1379; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)380; GFX12-NEXT: v_mov_b32_e32 v2, s0381; GFX12-NEXT: global_store_b32 v[0:1], v2, off382; GFX12-NEXT: s_endpgm383 %a = load volatile i8, ptr addrspace(4) %ptra384 %a32 = sext i8 %a to i32385 %b = load volatile i8, ptr addrspace(4) %ptrb386 %b32 = zext i8 %b to i32387 %res = add i32 %a32, %b32388 store i32 %res, ptr addrspace(1) %out389 ret void390}391 392define amdgpu_ps void @sextload_P4_i8_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {393; GFX11-LABEL: sextload_P4_i8_not_align4_or_not_uniform_mmo_gfx11:394; GFX11: ; %bb.0:395; GFX11-NEXT: v_mov_b32_e32 v2, 0396; GFX11-NEXT: global_load_i8 v2, v2, s[0:1]397; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0398; GFX11-NEXT: s_waitcnt lgkmcnt(0)399; GFX11-NEXT: s_sext_i32_i8 s0, s0400; GFX11-NEXT: s_waitcnt vmcnt(0)401; GFX11-NEXT: v_readfirstlane_b32 s1, v2402; GFX11-NEXT: s_add_i32 s0, s1, s0403; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)404; GFX11-NEXT: v_mov_b32_e32 v2, s0405; GFX11-NEXT: global_store_b32 v[0:1], v2, off406; GFX11-NEXT: s_endpgm407;408; GFX12-LABEL: sextload_P4_i8_not_align4_or_not_uniform_mmo_gfx11:409; GFX12: ; %bb.0:410; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x0411; GFX12-NEXT: s_load_i8 s1, s[2:3], 0x0412; GFX12-NEXT: s_wait_kmcnt 0x0413; GFX12-NEXT: s_add_co_i32 s0, s0, s1414; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)415; GFX12-NEXT: v_mov_b32_e32 v2, s0416; GFX12-NEXT: global_store_b32 v[0:1], v2, off417; GFX12-NEXT: s_endpgm418 %a = load i8, ptr addrspace(4) %ptra419 %a32 = sext i8 %a to i32420 %b = load volatile i8, ptr addrspace(4) %ptrb, align 4421 %b32 = sext i8 %b to i32422 %res = add i32 %a32, %b32423 store i32 %res, ptr addrspace(1) %out424 ret void425}426 427define amdgpu_ps void @zextload_P4_i8_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {428; GFX11-LABEL: zextload_P4_i8_not_align4_or_not_uniform_mmo_gfx11:429; GFX11: ; %bb.0:430; GFX11-NEXT: v_mov_b32_e32 v2, 0431; GFX11-NEXT: global_load_u8 v2, v2, s[0:1]432; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0433; GFX11-NEXT: s_waitcnt lgkmcnt(0)434; GFX11-NEXT: s_and_b32 s0, s0, 0xff435; GFX11-NEXT: s_waitcnt vmcnt(0)436; GFX11-NEXT: v_readfirstlane_b32 s1, v2437; GFX11-NEXT: s_add_i32 s0, s1, s0438; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)439; GFX11-NEXT: v_mov_b32_e32 v2, s0440; GFX11-NEXT: global_store_b32 v[0:1], v2, off441; GFX11-NEXT: s_endpgm442;443; GFX12-LABEL: zextload_P4_i8_not_align4_or_not_uniform_mmo_gfx11:444; GFX12: ; %bb.0:445; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0446; GFX12-NEXT: s_load_u8 s1, s[2:3], 0x0447; GFX12-NEXT: s_wait_kmcnt 0x0448; GFX12-NEXT: s_add_co_i32 s0, s0, s1449; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)450; GFX12-NEXT: v_mov_b32_e32 v2, s0451; GFX12-NEXT: global_store_b32 v[0:1], v2, off452; GFX12-NEXT: s_endpgm453 %a = load i8, ptr addrspace(4) %ptra454 %a32 = zext i8 %a to i32455 %b = load volatile i8, ptr addrspace(4) %ptrb, align 4456 %b32 = zext i8 %b to i32457 %res = add i32 %a32, %b32458 store i32 %res, ptr addrspace(1) %out459 ret void460}461 462define amdgpu_ps void @sextload_P4_i16_not_natural_align_or_not_uniform_mmo_gfx12(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {463; GFX11-LABEL: sextload_P4_i16_not_natural_align_or_not_uniform_mmo_gfx12:464; GFX11: ; %bb.0:465; GFX11-NEXT: v_mov_b32_e32 v2, 0466; GFX11-NEXT: s_clause 0x1467; GFX11-NEXT: global_load_i16 v3, v2, s[0:1]468; GFX11-NEXT: global_load_i16 v2, v2, s[2:3] glc dlc469; GFX11-NEXT: s_waitcnt vmcnt(1)470; GFX11-NEXT: v_readfirstlane_b32 s0, v3471; GFX11-NEXT: s_waitcnt vmcnt(0)472; GFX11-NEXT: v_readfirstlane_b32 s1, v2473; GFX11-NEXT: s_add_i32 s0, s0, s1474; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)475; GFX11-NEXT: v_mov_b32_e32 v2, s0476; GFX11-NEXT: global_store_b32 v[0:1], v2, off477; GFX11-NEXT: s_endpgm478;479; GFX12-LABEL: sextload_P4_i16_not_natural_align_or_not_uniform_mmo_gfx12:480; GFX12: ; %bb.0:481; GFX12-NEXT: v_mov_b32_e32 v2, 0482; GFX12-NEXT: global_load_i16 v2, v2, s[0:1]483; GFX12-NEXT: s_load_i16 s0, s[2:3], 0x0484; GFX12-NEXT: s_wait_loadcnt 0x0485; GFX12-NEXT: v_readfirstlane_b32 s1, v2486; GFX12-NEXT: s_wait_kmcnt 0x0487; GFX12-NEXT: s_add_co_i32 s0, s1, s0488; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)489; GFX12-NEXT: v_mov_b32_e32 v2, s0490; GFX12-NEXT: global_store_b32 v[0:1], v2, off491; GFX12-NEXT: s_endpgm492 %a = load i16, ptr addrspace(4) %ptra, align 1493 %a32 = sext i16 %a to i32494 %b = load volatile i16, ptr addrspace(4) %ptrb495 %b32 = sext i16 %b to i32496 %res = add i32 %a32, %b32497 store i32 %res, ptr addrspace(1) %out498 ret void499}500 501define amdgpu_ps void @sextload_P4_i16_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {502; GFX11-LABEL: sextload_P4_i16_not_align4_or_not_uniform_mmo_gfx11:503; GFX11: ; %bb.0:504; GFX11-NEXT: v_mov_b32_e32 v2, 0505; GFX11-NEXT: global_load_i16 v2, v2, s[0:1]506; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0507; GFX11-NEXT: s_waitcnt lgkmcnt(0)508; GFX11-NEXT: s_sext_i32_i16 s0, s0509; GFX11-NEXT: s_waitcnt vmcnt(0)510; GFX11-NEXT: v_readfirstlane_b32 s1, v2511; GFX11-NEXT: s_add_i32 s0, s1, s0512; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)513; GFX11-NEXT: v_mov_b32_e32 v2, s0514; GFX11-NEXT: global_store_b32 v[0:1], v2, off515; GFX11-NEXT: s_endpgm516;517; GFX12-LABEL: sextload_P4_i16_not_align4_or_not_uniform_mmo_gfx11:518; GFX12: ; %bb.0:519; GFX12-NEXT: s_load_i16 s0, s[0:1], 0x0520; GFX12-NEXT: s_load_i16 s1, s[2:3], 0x0521; GFX12-NEXT: s_wait_kmcnt 0x0522; GFX12-NEXT: s_add_co_i32 s0, s0, s1523; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)524; GFX12-NEXT: v_mov_b32_e32 v2, s0525; GFX12-NEXT: global_store_b32 v[0:1], v2, off526; GFX12-NEXT: s_endpgm527 %a = load i16, ptr addrspace(4) %ptra528 %a32 = sext i16 %a to i32529 %b = load volatile i16, ptr addrspace(4) %ptrb, align 4530 %b32 = sext i16 %b to i32531 %res = add i32 %a32, %b32532 store i32 %res, ptr addrspace(1) %out533 ret void534}535 536define amdgpu_ps void @zextload_P4_i16_not_natural_align_or_not_uniform_mmo_gfx12(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {537; GFX11-LABEL: zextload_P4_i16_not_natural_align_or_not_uniform_mmo_gfx12:538; GFX11: ; %bb.0:539; GFX11-NEXT: v_mov_b32_e32 v2, 0540; GFX11-NEXT: s_clause 0x1541; GFX11-NEXT: global_load_u16 v3, v2, s[0:1]542; GFX11-NEXT: global_load_u16 v2, v2, s[2:3] glc dlc543; GFX11-NEXT: s_waitcnt vmcnt(1)544; GFX11-NEXT: v_readfirstlane_b32 s0, v3545; GFX11-NEXT: s_waitcnt vmcnt(0)546; GFX11-NEXT: v_readfirstlane_b32 s1, v2547; GFX11-NEXT: s_add_i32 s0, s0, s1548; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)549; GFX11-NEXT: v_mov_b32_e32 v2, s0550; GFX11-NEXT: global_store_b32 v[0:1], v2, off551; GFX11-NEXT: s_endpgm552;553; GFX12-LABEL: zextload_P4_i16_not_natural_align_or_not_uniform_mmo_gfx12:554; GFX12: ; %bb.0:555; GFX12-NEXT: v_mov_b32_e32 v2, 0556; GFX12-NEXT: global_load_u16 v2, v2, s[0:1]557; GFX12-NEXT: s_load_u16 s0, s[2:3], 0x0558; GFX12-NEXT: s_wait_loadcnt 0x0559; GFX12-NEXT: v_readfirstlane_b32 s1, v2560; GFX12-NEXT: s_wait_kmcnt 0x0561; GFX12-NEXT: s_add_co_i32 s0, s1, s0562; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)563; GFX12-NEXT: v_mov_b32_e32 v2, s0564; GFX12-NEXT: global_store_b32 v[0:1], v2, off565; GFX12-NEXT: s_endpgm566 %a = load i16, ptr addrspace(4) %ptra, align 1567 %a32 = zext i16 %a to i32568 %b = load volatile i16, ptr addrspace(4) %ptrb569 %b32 = zext i16 %b to i32570 %res = add i32 %a32, %b32571 store i32 %res, ptr addrspace(1) %out572 ret void573}574 575define amdgpu_ps void @zextload_P4_i16_not_align4_or_not_uniform_mmo_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {576; GFX11-LABEL: zextload_P4_i16_not_align4_or_not_uniform_mmo_gfx11:577; GFX11: ; %bb.0:578; GFX11-NEXT: v_mov_b32_e32 v2, 0579; GFX11-NEXT: global_load_u16 v2, v2, s[0:1]580; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0581; GFX11-NEXT: s_waitcnt lgkmcnt(0)582; GFX11-NEXT: s_and_b32 s0, s0, 0xffff583; GFX11-NEXT: s_waitcnt vmcnt(0)584; GFX11-NEXT: v_readfirstlane_b32 s1, v2585; GFX11-NEXT: s_add_i32 s0, s1, s0586; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)587; GFX11-NEXT: v_mov_b32_e32 v2, s0588; GFX11-NEXT: global_store_b32 v[0:1], v2, off589; GFX11-NEXT: s_endpgm590;591; GFX12-LABEL: zextload_P4_i16_not_align4_or_not_uniform_mmo_gfx11:592; GFX12: ; %bb.0:593; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0594; GFX12-NEXT: s_load_u16 s1, s[2:3], 0x0595; GFX12-NEXT: s_wait_kmcnt 0x0596; GFX12-NEXT: s_add_co_i32 s0, s0, s1597; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)598; GFX12-NEXT: v_mov_b32_e32 v2, s0599; GFX12-NEXT: global_store_b32 v[0:1], v2, off600; GFX12-NEXT: s_endpgm601 %a = load i16, ptr addrspace(4) %ptra602 %a32 = zext i16 %a to i32603 %b = load volatile i16, ptr addrspace(4) %ptrb, align 4604 %b32 = zext i16 %b to i32605 %res = add i32 %a32, %b32606 store i32 %res, ptr addrspace(1) %out607 ret void608}609