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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX12 %s4 5define amdgpu_ps void @sextload_P1_i8_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {6; GFX11-LABEL: sextload_P1_i8_gfx12:7; GFX11: ; %bb.0:8; GFX11-NEXT: v_mov_b32_e32 v2, 09; GFX11-NEXT: global_load_i8 v2, v2, s[0:1]10; GFX11-NEXT: s_waitcnt vmcnt(0)11; GFX11-NEXT: v_readfirstlane_b32 s0, v212; GFX11-NEXT: s_add_i32 s0, s0, s013; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)14; GFX11-NEXT: v_mov_b32_e32 v2, s015; GFX11-NEXT: global_store_b32 v[0:1], v2, off16; GFX11-NEXT: s_endpgm17;18; GFX12-LABEL: sextload_P1_i8_gfx12:19; GFX12: ; %bb.0:20; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x021; GFX12-NEXT: s_wait_kmcnt 0x022; GFX12-NEXT: s_add_co_i32 s0, s0, s023; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)24; GFX12-NEXT: v_mov_b32_e32 v2, s025; GFX12-NEXT: global_store_b32 v[0:1], v2, off26; GFX12-NEXT: s_endpgm27 %a = load i8, ptr addrspace(1) %ptra28 %a32 = sext i8 %a to i3229 %res = add i32 %a32, %a3230 store i32 %res, ptr addrspace(1) %out31 ret void32}33 34define amdgpu_ps void @sextload_P1_i8_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {35; GFX11-LABEL: sextload_P1_i8_align4_gfx11:36; GFX11: ; %bb.0:37; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x038; GFX11-NEXT: s_waitcnt lgkmcnt(0)39; GFX11-NEXT: s_sext_i32_i8 s0, s040; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)41; GFX11-NEXT: s_add_i32 s0, s0, s042; GFX11-NEXT: v_mov_b32_e32 v2, s043; GFX11-NEXT: global_store_b32 v[0:1], v2, off44; GFX11-NEXT: s_endpgm45;46; GFX12-LABEL: sextload_P1_i8_align4_gfx11:47; GFX12: ; %bb.0:48; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x049; GFX12-NEXT: s_wait_kmcnt 0x050; GFX12-NEXT: s_add_co_i32 s0, s0, s051; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)52; GFX12-NEXT: v_mov_b32_e32 v2, s053; GFX12-NEXT: global_store_b32 v[0:1], v2, off54; GFX12-NEXT: s_endpgm55 %a = load i8, ptr addrspace(1) %ptra, align 456 %a32 = sext i8 %a to i3257 %res = add i32 %a32, %a3258 store i32 %res, ptr addrspace(1) %out59 ret void60}61 62define amdgpu_ps void @sextload_P1_i16_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {63; GFX11-LABEL: sextload_P1_i16_gfx12:64; GFX11: ; %bb.0:65; GFX11-NEXT: v_mov_b32_e32 v2, 066; GFX11-NEXT: global_load_i16 v2, v2, s[0:1]67; GFX11-NEXT: s_waitcnt vmcnt(0)68; GFX11-NEXT: v_readfirstlane_b32 s0, v269; GFX11-NEXT: s_add_i32 s0, s0, s070; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)71; GFX11-NEXT: v_mov_b32_e32 v2, s072; GFX11-NEXT: global_store_b32 v[0:1], v2, off73; GFX11-NEXT: s_endpgm74;75; GFX12-LABEL: sextload_P1_i16_gfx12:76; GFX12: ; %bb.0:77; GFX12-NEXT: s_load_i16 s0, s[0:1], 0x078; GFX12-NEXT: s_wait_kmcnt 0x079; GFX12-NEXT: s_add_co_i32 s0, s0, s080; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)81; GFX12-NEXT: v_mov_b32_e32 v2, s082; GFX12-NEXT: global_store_b32 v[0:1], v2, off83; GFX12-NEXT: s_endpgm84 %a = load i16, ptr addrspace(1) %ptra85 %a32 = sext i16 %a to i3286 %res = add i32 %a32, %a3287 store i32 %res, ptr addrspace(1) %out88 ret void89}90 91define amdgpu_ps void @sextload_P1_i16_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {92; GFX11-LABEL: sextload_P1_i16_align4_gfx11:93; GFX11: ; %bb.0:94; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x095; GFX11-NEXT: s_waitcnt lgkmcnt(0)96; GFX11-NEXT: s_sext_i32_i16 s0, s097; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)98; GFX11-NEXT: s_add_i32 s0, s0, s099; GFX11-NEXT: v_mov_b32_e32 v2, s0100; GFX11-NEXT: global_store_b32 v[0:1], v2, off101; GFX11-NEXT: s_endpgm102;103; GFX12-LABEL: sextload_P1_i16_align4_gfx11:104; GFX12: ; %bb.0:105; GFX12-NEXT: s_load_i16 s0, s[0:1], 0x0106; GFX12-NEXT: s_wait_kmcnt 0x0107; GFX12-NEXT: s_add_co_i32 s0, s0, s0108; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)109; GFX12-NEXT: v_mov_b32_e32 v2, s0110; GFX12-NEXT: global_store_b32 v[0:1], v2, off111; GFX12-NEXT: s_endpgm112 %a = load i16, ptr addrspace(1) %ptra, align 4113 %a32 = sext i16 %a to i32114 %res = add i32 %a32, %a32115 store i32 %res, ptr addrspace(1) %out116 ret void117}118 119define amdgpu_ps void @zextload_P1_i8_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {120; GFX11-LABEL: zextload_P1_i8_gfx12:121; GFX11: ; %bb.0:122; GFX11-NEXT: v_mov_b32_e32 v2, 0123; GFX11-NEXT: global_load_u8 v2, v2, s[0:1]124; GFX11-NEXT: s_waitcnt vmcnt(0)125; GFX11-NEXT: v_readfirstlane_b32 s0, v2126; GFX11-NEXT: s_add_i32 s0, s0, s0127; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)128; GFX11-NEXT: v_mov_b32_e32 v2, s0129; GFX11-NEXT: global_store_b32 v[0:1], v2, off130; GFX11-NEXT: s_endpgm131;132; GFX12-LABEL: zextload_P1_i8_gfx12:133; GFX12: ; %bb.0:134; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0135; GFX12-NEXT: s_wait_kmcnt 0x0136; GFX12-NEXT: s_add_co_i32 s0, s0, s0137; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)138; GFX12-NEXT: v_mov_b32_e32 v2, s0139; GFX12-NEXT: global_store_b32 v[0:1], v2, off140; GFX12-NEXT: s_endpgm141 %a = load i8, ptr addrspace(1) %ptra142 %a32 = zext i8 %a to i32143 %res = add i32 %a32, %a32144 store i32 %res, ptr addrspace(1) %out145 ret void146}147 148define amdgpu_ps void @zextload_P1_i8_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {149; GFX11-LABEL: zextload_P1_i8_align4_gfx11:150; GFX11: ; %bb.0:151; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0152; GFX11-NEXT: s_waitcnt lgkmcnt(0)153; GFX11-NEXT: s_and_b32 s0, s0, 0xff154; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)155; GFX11-NEXT: s_add_i32 s0, s0, s0156; GFX11-NEXT: v_mov_b32_e32 v2, s0157; GFX11-NEXT: global_store_b32 v[0:1], v2, off158; GFX11-NEXT: s_endpgm159;160; GFX12-LABEL: zextload_P1_i8_align4_gfx11:161; GFX12: ; %bb.0:162; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0163; GFX12-NEXT: s_wait_kmcnt 0x0164; GFX12-NEXT: s_add_co_i32 s0, s0, s0165; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)166; GFX12-NEXT: v_mov_b32_e32 v2, s0167; GFX12-NEXT: global_store_b32 v[0:1], v2, off168; GFX12-NEXT: s_endpgm169 %a = load i8, ptr addrspace(1) %ptra, align 4170 %a32 = zext i8 %a to i32171 %res = add i32 %a32, %a32172 store i32 %res, ptr addrspace(1) %out173 ret void174}175 176define amdgpu_ps void @zextload_P1_i16_gfx12(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {177; GFX11-LABEL: zextload_P1_i16_gfx12:178; GFX11: ; %bb.0:179; GFX11-NEXT: v_mov_b32_e32 v2, 0180; GFX11-NEXT: global_load_u16 v2, v2, s[0:1]181; GFX11-NEXT: s_waitcnt vmcnt(0)182; GFX11-NEXT: v_readfirstlane_b32 s0, v2183; GFX11-NEXT: s_add_i32 s0, s0, s0184; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)185; GFX11-NEXT: v_mov_b32_e32 v2, s0186; GFX11-NEXT: global_store_b32 v[0:1], v2, off187; GFX11-NEXT: s_endpgm188;189; GFX12-LABEL: zextload_P1_i16_gfx12:190; GFX12: ; %bb.0:191; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0192; GFX12-NEXT: s_wait_kmcnt 0x0193; GFX12-NEXT: s_add_co_i32 s0, s0, s0194; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)195; GFX12-NEXT: v_mov_b32_e32 v2, s0196; GFX12-NEXT: global_store_b32 v[0:1], v2, off197; GFX12-NEXT: s_endpgm198 %a = load i16, ptr addrspace(1) %ptra199 %a32 = zext i16 %a to i32200 %res = add i32 %a32, %a32201 store i32 %res, ptr addrspace(1) %out202 ret void203}204 205define amdgpu_ps void @zextload_P1_i16_align4_gfx11(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {206; GFX11-LABEL: zextload_P1_i16_align4_gfx11:207; GFX11: ; %bb.0:208; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0209; GFX11-NEXT: s_waitcnt lgkmcnt(0)210; GFX11-NEXT: s_and_b32 s0, s0, 0xffff211; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)212; GFX11-NEXT: s_add_i32 s0, s0, s0213; GFX11-NEXT: v_mov_b32_e32 v2, s0214; GFX11-NEXT: global_store_b32 v[0:1], v2, off215; GFX11-NEXT: s_endpgm216;217; GFX12-LABEL: zextload_P1_i16_align4_gfx11:218; GFX12: ; %bb.0:219; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0220; GFX12-NEXT: s_wait_kmcnt 0x0221; GFX12-NEXT: s_add_co_i32 s0, s0, s0222; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)223; GFX12-NEXT: v_mov_b32_e32 v2, s0224; GFX12-NEXT: global_store_b32 v[0:1], v2, off225; GFX12-NEXT: s_endpgm226 %a = load i16, ptr addrspace(1) %ptra, align 4227 %a32 = zext i16 %a to i32228 %res = add i32 %a32, %a32229 store i32 %res, ptr addrspace(1) %out230 ret void231}232