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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s7 8define i8 @v_lshr_i8(i8 %value, i8 %amount) {9; GFX6-LABEL: v_lshr_i8:10; GFX6: ; %bb.0:11; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v113; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v014; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v015; GFX6-NEXT: s_setpc_b64 s[30:31]16;17; GFX8-LABEL: v_lshr_i8:18; GFX8: ; %bb.0:19; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)20; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_021; GFX8-NEXT: s_setpc_b64 s[30:31]22;23; GFX9-LABEL: v_lshr_i8:24; GFX9: ; %bb.0:25; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)26; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_027; GFX9-NEXT: s_setpc_b64 s[30:31]28;29; GFX10PLUS-LABEL: v_lshr_i8:30; GFX10PLUS: ; %bb.0:31; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xff, v133; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xff, v034; GFX10PLUS-NEXT: v_lshrrev_b16 v0, v1, v035; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]36 %result = lshr i8 %value, %amount37 ret i8 %result38}39 40define i8 @v_lshr_i8_7(i8 %value) {41; GFX6-LABEL: v_lshr_i8_7:42; GFX6: ; %bb.0:43; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; GFX6-NEXT: v_bfe_u32 v0, v0, 7, 145; GFX6-NEXT: s_setpc_b64 s[30:31]46;47; GFX8-LABEL: v_lshr_i8_7:48; GFX8: ; %bb.0:49; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; GFX8-NEXT: v_mov_b32_e32 v1, 751; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_052; GFX8-NEXT: s_setpc_b64 s[30:31]53;54; GFX9-LABEL: v_lshr_i8_7:55; GFX9: ; %bb.0:56; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)57; GFX9-NEXT: v_mov_b32_e32 v1, 758; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_059; GFX9-NEXT: s_setpc_b64 s[30:31]60;61; GFX10PLUS-LABEL: v_lshr_i8_7:62; GFX10PLUS: ; %bb.0:63; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)64; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xff, v065; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 7, v066; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]67 %result = lshr i8 %value, 768 ret i8 %result69}70 71define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) {72; GFX6-LABEL: s_lshr_i8:73; GFX6: ; %bb.0:74; GFX6-NEXT: s_and_b32 s0, s0, 0xff75; GFX6-NEXT: s_lshr_b32 s0, s0, s176; GFX6-NEXT: ; return to shader part epilog77;78; GFX8-LABEL: s_lshr_i8:79; GFX8: ; %bb.0:80; GFX8-NEXT: s_and_b32 s0, s0, 0xff81; GFX8-NEXT: s_and_b32 s1, s1, 0xff82; GFX8-NEXT: s_and_b32 s0, 0xffff, s083; GFX8-NEXT: s_lshr_b32 s0, s0, s184; GFX8-NEXT: ; return to shader part epilog85;86; GFX9-LABEL: s_lshr_i8:87; GFX9: ; %bb.0:88; GFX9-NEXT: s_and_b32 s0, s0, 0xff89; GFX9-NEXT: s_and_b32 s1, s1, 0xff90; GFX9-NEXT: s_and_b32 s0, 0xffff, s091; GFX9-NEXT: s_lshr_b32 s0, s0, s192; GFX9-NEXT: ; return to shader part epilog93;94; GFX10PLUS-LABEL: s_lshr_i8:95; GFX10PLUS: ; %bb.0:96; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xff97; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xff98; GFX10PLUS-NEXT: s_and_b32 s0, 0xffff, s099; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1100; GFX10PLUS-NEXT: ; return to shader part epilog101 %result = lshr i8 %value, %amount102 ret i8 %result103}104 105define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) {106; GFX6-LABEL: s_lshr_i8_7:107; GFX6: ; %bb.0:108; GFX6-NEXT: s_bfe_u32 s0, s0, 0x10007109; GFX6-NEXT: ; return to shader part epilog110;111; GFX8-LABEL: s_lshr_i8_7:112; GFX8: ; %bb.0:113; GFX8-NEXT: s_and_b32 s0, s0, 0xff114; GFX8-NEXT: s_and_b32 s0, 0xffff, s0115; GFX8-NEXT: s_lshr_b32 s0, s0, 7116; GFX8-NEXT: ; return to shader part epilog117;118; GFX9-LABEL: s_lshr_i8_7:119; GFX9: ; %bb.0:120; GFX9-NEXT: s_and_b32 s0, s0, 0xff121; GFX9-NEXT: s_and_b32 s0, 0xffff, s0122; GFX9-NEXT: s_lshr_b32 s0, s0, 7123; GFX9-NEXT: ; return to shader part epilog124;125; GFX10PLUS-LABEL: s_lshr_i8_7:126; GFX10PLUS: ; %bb.0:127; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xff128; GFX10PLUS-NEXT: s_and_b32 s0, 0xffff, s0129; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 7130; GFX10PLUS-NEXT: ; return to shader part epilog131 %result = lshr i8 %value, 7132 ret i8 %result133}134 135 136define i24 @v_lshr_i24(i24 %value, i24 %amount) {137; GCN-LABEL: v_lshr_i24:138; GCN: ; %bb.0:139; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)140; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1141; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0142; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0143; GCN-NEXT: s_setpc_b64 s[30:31]144;145; GFX10PLUS-LABEL: v_lshr_i24:146; GFX10PLUS: ; %bb.0:147; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)148; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1149; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffffff, v0150; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v1, v0151; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]152 %result = lshr i24 %value, %amount153 ret i24 %result154}155 156define i24 @v_lshr_i24_7(i24 %value) {157; GCN-LABEL: v_lshr_i24_7:158; GCN: ; %bb.0:159; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)160; GCN-NEXT: v_bfe_u32 v0, v0, 7, 17161; GCN-NEXT: s_setpc_b64 s[30:31]162;163; GFX10PLUS-LABEL: v_lshr_i24_7:164; GFX10PLUS: ; %bb.0:165; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)166; GFX10PLUS-NEXT: v_bfe_u32 v0, v0, 7, 17167; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]168 %result = lshr i24 %value, 7169 ret i24 %result170}171 172define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) {173; GCN-LABEL: s_lshr_i24:174; GCN: ; %bb.0:175; GCN-NEXT: s_and_b32 s0, s0, 0xffffff176; GCN-NEXT: s_lshr_b32 s0, s0, s1177; GCN-NEXT: ; return to shader part epilog178;179; GFX10PLUS-LABEL: s_lshr_i24:180; GFX10PLUS: ; %bb.0:181; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffffff182; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1183; GFX10PLUS-NEXT: ; return to shader part epilog184 %result = lshr i24 %value, %amount185 ret i24 %result186}187 188define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) {189; GCN-LABEL: s_lshr_i24_7:190; GCN: ; %bb.0:191; GCN-NEXT: s_bfe_u32 s0, s0, 0x110007192; GCN-NEXT: ; return to shader part epilog193;194; GFX10PLUS-LABEL: s_lshr_i24_7:195; GFX10PLUS: ; %bb.0:196; GFX10PLUS-NEXT: s_bfe_u32 s0, s0, 0x110007197; GFX10PLUS-NEXT: ; return to shader part epilog198 %result = lshr i24 %value, 7199 ret i24 %result200}201 202define i32 @v_lshr_i32(i32 %value, i32 %amount) {203; GCN-LABEL: v_lshr_i32:204; GCN: ; %bb.0:205; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)206; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0207; GCN-NEXT: s_setpc_b64 s[30:31]208;209; GFX10PLUS-LABEL: v_lshr_i32:210; GFX10PLUS: ; %bb.0:211; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)212; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v1, v0213; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]214 %result = lshr i32 %value, %amount215 ret i32 %result216}217 218define i32 @v_lshr_i32_31(i32 %value) {219; GCN-LABEL: v_lshr_i32_31:220; GCN: ; %bb.0:221; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)222; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0223; GCN-NEXT: s_setpc_b64 s[30:31]224;225; GFX10PLUS-LABEL: v_lshr_i32_31:226; GFX10PLUS: ; %bb.0:227; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)228; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 31, v0229; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]230 %result = lshr i32 %value, 31231 ret i32 %result232}233 234define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) {235; GCN-LABEL: s_lshr_i32:236; GCN: ; %bb.0:237; GCN-NEXT: s_lshr_b32 s0, s0, s1238; GCN-NEXT: ; return to shader part epilog239;240; GFX10PLUS-LABEL: s_lshr_i32:241; GFX10PLUS: ; %bb.0:242; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1243; GFX10PLUS-NEXT: ; return to shader part epilog244 %result = lshr i32 %value, %amount245 ret i32 %result246}247 248define amdgpu_ps i32 @s_lshr_i32_31(i32 inreg %value) {249; GCN-LABEL: s_lshr_i32_31:250; GCN: ; %bb.0:251; GCN-NEXT: s_lshr_b32 s0, s0, 31252; GCN-NEXT: ; return to shader part epilog253;254; GFX10PLUS-LABEL: s_lshr_i32_31:255; GFX10PLUS: ; %bb.0:256; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 31257; GFX10PLUS-NEXT: ; return to shader part epilog258 %result = lshr i32 %value, 31259 ret i32 %result260}261 262define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) {263; GFX6-LABEL: lshr_i32_sv:264; GFX6: ; %bb.0:265; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0266; GFX6-NEXT: ; return to shader part epilog267;268; GFX8-LABEL: lshr_i32_sv:269; GFX8: ; %bb.0:270; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0271; GFX8-NEXT: ; return to shader part epilog272;273; GFX9-LABEL: lshr_i32_sv:274; GFX9: ; %bb.0:275; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0276; GFX9-NEXT: ; return to shader part epilog277;278; GFX10PLUS-LABEL: lshr_i32_sv:279; GFX10PLUS: ; %bb.0:280; GFX10PLUS-NEXT: v_lshrrev_b32_e64 v0, v0, s0281; GFX10PLUS-NEXT: ; return to shader part epilog282 %result = lshr i32 %value, %amount283 %cast = bitcast i32 %result to float284 ret float %cast285}286 287define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) {288; GCN-LABEL: lshr_i32_vs:289; GCN: ; %bb.0:290; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0291; GCN-NEXT: ; return to shader part epilog292;293; GFX10PLUS-LABEL: lshr_i32_vs:294; GFX10PLUS: ; %bb.0:295; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, s0, v0296; GFX10PLUS-NEXT: ; return to shader part epilog297 %result = lshr i32 %value, %amount298 %cast = bitcast i32 %result to float299 ret float %cast300}301 302define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) {303; GCN-LABEL: v_lshr_v2i32:304; GCN: ; %bb.0:305; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)306; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0307; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1308; GCN-NEXT: s_setpc_b64 s[30:31]309;310; GFX10PLUS-LABEL: v_lshr_v2i32:311; GFX10PLUS: ; %bb.0:312; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)313; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v2, v0314; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v3, v1315; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]316 %result = lshr <2 x i32> %value, %amount317 ret <2 x i32> %result318}319 320define <2 x i32> @v_lshr_v2i32_31(<2 x i32> %value) {321; GCN-LABEL: v_lshr_v2i32_31:322; GCN: ; %bb.0:323; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)324; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0325; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v1326; GCN-NEXT: s_setpc_b64 s[30:31]327;328; GFX10PLUS-LABEL: v_lshr_v2i32_31:329; GFX10PLUS: ; %bb.0:330; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)331; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 31, v0332; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, 31, v1333; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]334 %result = lshr <2 x i32> %value, <i32 31, i32 31>335 ret <2 x i32> %result336}337 338define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) {339; GCN-LABEL: s_lshr_v2i32:340; GCN: ; %bb.0:341; GCN-NEXT: s_lshr_b32 s0, s0, s2342; GCN-NEXT: s_lshr_b32 s1, s1, s3343; GCN-NEXT: ; return to shader part epilog344;345; GFX10PLUS-LABEL: s_lshr_v2i32:346; GFX10PLUS: ; %bb.0:347; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s2348; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s3349; GFX10PLUS-NEXT: ; return to shader part epilog350 %result = lshr <2 x i32> %value, %amount351 ret <2 x i32> %result352}353 354define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) {355; GCN-LABEL: v_lshr_v3i32:356; GCN: ; %bb.0:357; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)358; GCN-NEXT: v_lshrrev_b32_e32 v0, v3, v0359; GCN-NEXT: v_lshrrev_b32_e32 v1, v4, v1360; GCN-NEXT: v_lshrrev_b32_e32 v2, v5, v2361; GCN-NEXT: s_setpc_b64 s[30:31]362;363; GFX10PLUS-LABEL: v_lshr_v3i32:364; GFX10PLUS: ; %bb.0:365; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)366; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v3, v0367; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v4, v1368; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v2, v5, v2369; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]370 %result = lshr <3 x i32> %value, %amount371 ret <3 x i32> %result372}373 374define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) {375; GCN-LABEL: s_lshr_v3i32:376; GCN: ; %bb.0:377; GCN-NEXT: s_lshr_b32 s0, s0, s3378; GCN-NEXT: s_lshr_b32 s1, s1, s4379; GCN-NEXT: s_lshr_b32 s2, s2, s5380; GCN-NEXT: ; return to shader part epilog381;382; GFX10PLUS-LABEL: s_lshr_v3i32:383; GFX10PLUS: ; %bb.0:384; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s3385; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s4386; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s5387; GFX10PLUS-NEXT: ; return to shader part epilog388 %result = lshr <3 x i32> %value, %amount389 ret <3 x i32> %result390}391 392define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) {393; GCN-LABEL: v_lshr_v4i32:394; GCN: ; %bb.0:395; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)396; GCN-NEXT: v_lshrrev_b32_e32 v0, v4, v0397; GCN-NEXT: v_lshrrev_b32_e32 v1, v5, v1398; GCN-NEXT: v_lshrrev_b32_e32 v2, v6, v2399; GCN-NEXT: v_lshrrev_b32_e32 v3, v7, v3400; GCN-NEXT: s_setpc_b64 s[30:31]401;402; GFX10PLUS-LABEL: v_lshr_v4i32:403; GFX10PLUS: ; %bb.0:404; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)405; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v4, v0406; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v5, v1407; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v2, v6, v2408; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, v7, v3409; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]410 %result = lshr <4 x i32> %value, %amount411 ret <4 x i32> %result412}413 414define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) {415; GCN-LABEL: s_lshr_v4i32:416; GCN: ; %bb.0:417; GCN-NEXT: s_lshr_b32 s0, s0, s4418; GCN-NEXT: s_lshr_b32 s1, s1, s5419; GCN-NEXT: s_lshr_b32 s2, s2, s6420; GCN-NEXT: s_lshr_b32 s3, s3, s7421; GCN-NEXT: ; return to shader part epilog422;423; GFX10PLUS-LABEL: s_lshr_v4i32:424; GFX10PLUS: ; %bb.0:425; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s4426; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s5427; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s6428; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s7429; GFX10PLUS-NEXT: ; return to shader part epilog430 %result = lshr <4 x i32> %value, %amount431 ret <4 x i32> %result432}433 434define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) {435; GCN-LABEL: v_lshr_v5i32:436; GCN: ; %bb.0:437; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)438; GCN-NEXT: v_lshrrev_b32_e32 v0, v5, v0439; GCN-NEXT: v_lshrrev_b32_e32 v1, v6, v1440; GCN-NEXT: v_lshrrev_b32_e32 v2, v7, v2441; GCN-NEXT: v_lshrrev_b32_e32 v3, v8, v3442; GCN-NEXT: v_lshrrev_b32_e32 v4, v9, v4443; GCN-NEXT: s_setpc_b64 s[30:31]444;445; GFX10PLUS-LABEL: v_lshr_v5i32:446; GFX10PLUS: ; %bb.0:447; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)448; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, v5, v0449; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, v6, v1450; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v2, v7, v2451; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, v8, v3452; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v4, v9, v4453; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]454 %result = lshr <5 x i32> %value, %amount455 ret <5 x i32> %result456}457 458define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) {459; GCN-LABEL: s_lshr_v5i32:460; GCN: ; %bb.0:461; GCN-NEXT: s_lshr_b32 s0, s0, s5462; GCN-NEXT: s_lshr_b32 s1, s1, s6463; GCN-NEXT: s_lshr_b32 s2, s2, s7464; GCN-NEXT: s_lshr_b32 s3, s3, s8465; GCN-NEXT: s_lshr_b32 s4, s4, s9466; GCN-NEXT: ; return to shader part epilog467;468; GFX10PLUS-LABEL: s_lshr_v5i32:469; GFX10PLUS: ; %bb.0:470; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s5471; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s6472; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s7473; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s8474; GFX10PLUS-NEXT: s_lshr_b32 s4, s4, s9475; GFX10PLUS-NEXT: ; return to shader part epilog476 %result = lshr <5 x i32> %value, %amount477 ret <5 x i32> %result478}479 480define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) {481; GCN-LABEL: v_lshr_v16i32:482; GCN: ; %bb.0:483; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)484; GCN-NEXT: v_lshrrev_b32_e32 v0, v16, v0485; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32486; GCN-NEXT: v_lshrrev_b32_e32 v1, v17, v1487; GCN-NEXT: v_lshrrev_b32_e32 v2, v18, v2488; GCN-NEXT: v_lshrrev_b32_e32 v3, v19, v3489; GCN-NEXT: v_lshrrev_b32_e32 v4, v20, v4490; GCN-NEXT: v_lshrrev_b32_e32 v5, v21, v5491; GCN-NEXT: v_lshrrev_b32_e32 v6, v22, v6492; GCN-NEXT: v_lshrrev_b32_e32 v7, v23, v7493; GCN-NEXT: v_lshrrev_b32_e32 v8, v24, v8494; GCN-NEXT: v_lshrrev_b32_e32 v9, v25, v9495; GCN-NEXT: v_lshrrev_b32_e32 v10, v26, v10496; GCN-NEXT: v_lshrrev_b32_e32 v11, v27, v11497; GCN-NEXT: v_lshrrev_b32_e32 v12, v28, v12498; GCN-NEXT: v_lshrrev_b32_e32 v13, v29, v13499; GCN-NEXT: v_lshrrev_b32_e32 v14, v30, v14500; GCN-NEXT: s_waitcnt vmcnt(0)501; GCN-NEXT: v_lshrrev_b32_e32 v15, v16, v15502; GCN-NEXT: s_setpc_b64 s[30:31]503;504; GFX10-LABEL: v_lshr_v16i32:505; GFX10: ; %bb.0:506; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)507; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32508; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0509; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1510; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2511; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3512; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4513; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5514; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6515; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7516; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8517; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9518; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10519; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11520; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12521; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13522; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14523; GFX10-NEXT: s_waitcnt vmcnt(0)524; GFX10-NEXT: v_lshrrev_b32_e32 v15, v31, v15525; GFX10-NEXT: s_setpc_b64 s[30:31]526;527; GFX11-LABEL: v_lshr_v16i32:528; GFX11: ; %bb.0:529; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)530; GFX11-NEXT: scratch_load_b32 v31, off, s32531; GFX11-NEXT: v_lshrrev_b32_e32 v0, v16, v0532; GFX11-NEXT: v_lshrrev_b32_e32 v1, v17, v1533; GFX11-NEXT: v_lshrrev_b32_e32 v2, v18, v2534; GFX11-NEXT: v_lshrrev_b32_e32 v3, v19, v3535; GFX11-NEXT: v_lshrrev_b32_e32 v4, v20, v4536; GFX11-NEXT: v_lshrrev_b32_e32 v5, v21, v5537; GFX11-NEXT: v_lshrrev_b32_e32 v6, v22, v6538; GFX11-NEXT: v_lshrrev_b32_e32 v7, v23, v7539; GFX11-NEXT: v_lshrrev_b32_e32 v8, v24, v8540; GFX11-NEXT: v_lshrrev_b32_e32 v9, v25, v9541; GFX11-NEXT: v_lshrrev_b32_e32 v10, v26, v10542; GFX11-NEXT: v_lshrrev_b32_e32 v11, v27, v11543; GFX11-NEXT: v_lshrrev_b32_e32 v12, v28, v12544; GFX11-NEXT: v_lshrrev_b32_e32 v13, v29, v13545; GFX11-NEXT: v_lshrrev_b32_e32 v14, v30, v14546; GFX11-NEXT: s_waitcnt vmcnt(0)547; GFX11-NEXT: v_lshrrev_b32_e32 v15, v31, v15548; GFX11-NEXT: s_setpc_b64 s[30:31]549 %result = lshr <16 x i32> %value, %amount550 ret <16 x i32> %result551}552 553define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {554; GCN-LABEL: s_lshr_v16i32:555; GCN: ; %bb.0:556; GCN-NEXT: s_lshr_b32 s0, s0, s16557; GCN-NEXT: s_lshr_b32 s1, s1, s17558; GCN-NEXT: s_lshr_b32 s2, s2, s18559; GCN-NEXT: s_lshr_b32 s3, s3, s19560; GCN-NEXT: s_lshr_b32 s4, s4, s20561; GCN-NEXT: s_lshr_b32 s5, s5, s21562; GCN-NEXT: s_lshr_b32 s6, s6, s22563; GCN-NEXT: s_lshr_b32 s7, s7, s23564; GCN-NEXT: s_lshr_b32 s8, s8, s24565; GCN-NEXT: s_lshr_b32 s9, s9, s25566; GCN-NEXT: s_lshr_b32 s10, s10, s26567; GCN-NEXT: s_lshr_b32 s11, s11, s27568; GCN-NEXT: s_lshr_b32 s12, s12, s28569; GCN-NEXT: s_lshr_b32 s13, s13, s29570; GCN-NEXT: s_lshr_b32 s14, s14, s30571; GCN-NEXT: s_lshr_b32 s15, s15, s31572; GCN-NEXT: ; return to shader part epilog573;574; GFX10PLUS-LABEL: s_lshr_v16i32:575; GFX10PLUS: ; %bb.0:576; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s16577; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s17578; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s18579; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s19580; GFX10PLUS-NEXT: s_lshr_b32 s4, s4, s20581; GFX10PLUS-NEXT: s_lshr_b32 s5, s5, s21582; GFX10PLUS-NEXT: s_lshr_b32 s6, s6, s22583; GFX10PLUS-NEXT: s_lshr_b32 s7, s7, s23584; GFX10PLUS-NEXT: s_lshr_b32 s8, s8, s24585; GFX10PLUS-NEXT: s_lshr_b32 s9, s9, s25586; GFX10PLUS-NEXT: s_lshr_b32 s10, s10, s26587; GFX10PLUS-NEXT: s_lshr_b32 s11, s11, s27588; GFX10PLUS-NEXT: s_lshr_b32 s12, s12, s28589; GFX10PLUS-NEXT: s_lshr_b32 s13, s13, s29590; GFX10PLUS-NEXT: s_lshr_b32 s14, s14, s30591; GFX10PLUS-NEXT: s_lshr_b32 s15, s15, s31592; GFX10PLUS-NEXT: ; return to shader part epilog593 %result = lshr <16 x i32> %value, %amount594 ret <16 x i32> %result595}596 597define i16 @v_lshr_i16(i16 %value, i16 %amount) {598; GFX6-LABEL: v_lshr_i16:599; GFX6: ; %bb.0:600; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)601; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1602; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0603; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0604; GFX6-NEXT: s_setpc_b64 s[30:31]605;606; GFX8-LABEL: v_lshr_i16:607; GFX8: ; %bb.0:608; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)609; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0610; GFX8-NEXT: s_setpc_b64 s[30:31]611;612; GFX9-LABEL: v_lshr_i16:613; GFX9: ; %bb.0:614; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)615; GFX9-NEXT: v_lshrrev_b16_e32 v0, v1, v0616; GFX9-NEXT: s_setpc_b64 s[30:31]617;618; GFX10PLUS-LABEL: v_lshr_i16:619; GFX10PLUS: ; %bb.0:620; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)621; GFX10PLUS-NEXT: v_lshrrev_b16 v0, v1, v0622; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]623 %result = lshr i16 %value, %amount624 ret i16 %result625}626 627define i16 @v_lshr_i16_15(i16 %value) {628; GFX6-LABEL: v_lshr_i16_15:629; GFX6: ; %bb.0:630; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)631; GFX6-NEXT: v_bfe_u32 v0, v0, 15, 1632; GFX6-NEXT: s_setpc_b64 s[30:31]633;634; GFX8-LABEL: v_lshr_i16_15:635; GFX8: ; %bb.0:636; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)637; GFX8-NEXT: v_lshrrev_b16_e32 v0, 15, v0638; GFX8-NEXT: s_setpc_b64 s[30:31]639;640; GFX9-LABEL: v_lshr_i16_15:641; GFX9: ; %bb.0:642; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)643; GFX9-NEXT: v_lshrrev_b16_e32 v0, 15, v0644; GFX9-NEXT: s_setpc_b64 s[30:31]645;646; GFX10PLUS-LABEL: v_lshr_i16_15:647; GFX10PLUS: ; %bb.0:648; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)649; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 15, v0650; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]651 %result = lshr i16 %value, 15652 ret i16 %result653}654 655define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) {656; GFX6-LABEL: s_lshr_i16:657; GFX6: ; %bb.0:658; GFX6-NEXT: s_and_b32 s0, s0, 0xffff659; GFX6-NEXT: s_lshr_b32 s0, s0, s1660; GFX6-NEXT: ; return to shader part epilog661;662; GFX8-LABEL: s_lshr_i16:663; GFX8: ; %bb.0:664; GFX8-NEXT: s_and_b32 s0, 0xffff, s0665; GFX8-NEXT: s_lshr_b32 s0, s0, s1666; GFX8-NEXT: ; return to shader part epilog667;668; GFX9-LABEL: s_lshr_i16:669; GFX9: ; %bb.0:670; GFX9-NEXT: s_and_b32 s0, 0xffff, s0671; GFX9-NEXT: s_lshr_b32 s0, s0, s1672; GFX9-NEXT: ; return to shader part epilog673;674; GFX10PLUS-LABEL: s_lshr_i16:675; GFX10PLUS: ; %bb.0:676; GFX10PLUS-NEXT: s_and_b32 s0, 0xffff, s0677; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s1678; GFX10PLUS-NEXT: ; return to shader part epilog679 %result = lshr i16 %value, %amount680 ret i16 %result681}682 683define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) {684; GFX6-LABEL: s_lshr_i16_15:685; GFX6: ; %bb.0:686; GFX6-NEXT: s_bfe_u32 s0, s0, 0x1000f687; GFX6-NEXT: ; return to shader part epilog688;689; GFX8-LABEL: s_lshr_i16_15:690; GFX8: ; %bb.0:691; GFX8-NEXT: s_and_b32 s0, 0xffff, s0692; GFX8-NEXT: s_lshr_b32 s0, s0, 15693; GFX8-NEXT: ; return to shader part epilog694;695; GFX9-LABEL: s_lshr_i16_15:696; GFX9: ; %bb.0:697; GFX9-NEXT: s_and_b32 s0, 0xffff, s0698; GFX9-NEXT: s_lshr_b32 s0, s0, 15699; GFX9-NEXT: ; return to shader part epilog700;701; GFX10PLUS-LABEL: s_lshr_i16_15:702; GFX10PLUS: ; %bb.0:703; GFX10PLUS-NEXT: s_and_b32 s0, 0xffff, s0704; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 15705; GFX10PLUS-NEXT: ; return to shader part epilog706 %result = lshr i16 %value, 15707 ret i16 %result708}709 710define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {711; GFX6-LABEL: lshr_i16_sv:712; GFX6: ; %bb.0:713; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0714; GFX6-NEXT: s_and_b32 s0, s0, 0xffff715; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0716; GFX6-NEXT: ; return to shader part epilog717;718; GFX8-LABEL: lshr_i16_sv:719; GFX8: ; %bb.0:720; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0721; GFX8-NEXT: ; return to shader part epilog722;723; GFX9-LABEL: lshr_i16_sv:724; GFX9: ; %bb.0:725; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0726; GFX9-NEXT: ; return to shader part epilog727;728; GFX10PLUS-LABEL: lshr_i16_sv:729; GFX10PLUS: ; %bb.0:730; GFX10PLUS-NEXT: v_lshrrev_b16 v0, v0, s0731; GFX10PLUS-NEXT: ; return to shader part epilog732 %result = lshr i16 %value, %amount733 %cast = bitcast i16 %result to half734 ret half %cast735}736 737define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) {738; GFX6-LABEL: lshr_i16_vs:739; GFX6: ; %bb.0:740; GFX6-NEXT: s_and_b32 s0, s0, 0xffff741; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0742; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0743; GFX6-NEXT: ; return to shader part epilog744;745; GFX8-LABEL: lshr_i16_vs:746; GFX8: ; %bb.0:747; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0748; GFX8-NEXT: ; return to shader part epilog749;750; GFX9-LABEL: lshr_i16_vs:751; GFX9: ; %bb.0:752; GFX9-NEXT: v_lshrrev_b16_e32 v0, s0, v0753; GFX9-NEXT: ; return to shader part epilog754;755; GFX10PLUS-LABEL: lshr_i16_vs:756; GFX10PLUS: ; %bb.0:757; GFX10PLUS-NEXT: v_lshrrev_b16 v0, s0, v0758; GFX10PLUS-NEXT: ; return to shader part epilog759 %result = lshr i16 %value, %amount760 %cast = bitcast i16 %result to half761 ret half %cast762}763 764define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {765; GFX6-LABEL: v_lshr_v2i16:766; GFX6: ; %bb.0:767; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)768; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2769; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0770; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0771; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3772; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1773; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1774; GFX6-NEXT: s_setpc_b64 s[30:31]775;776; GFX8-LABEL: v_lshr_v2i16:777; GFX8: ; %bb.0:778; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)779; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0780; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1781; GFX8-NEXT: v_or_b32_e32 v0, v2, v0782; GFX8-NEXT: s_setpc_b64 s[30:31]783;784; GFX9-LABEL: v_lshr_v2i16:785; GFX9: ; %bb.0:786; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)787; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0788; GFX9-NEXT: s_setpc_b64 s[30:31]789;790; GFX10PLUS-LABEL: v_lshr_v2i16:791; GFX10PLUS: ; %bb.0:792; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)793; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v1, v0794; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]795 %result = lshr <2 x i16> %value, %amount796 ret <2 x i16> %result797}798 799define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) {800; GFX6-LABEL: v_lshr_v2i16_15:801; GFX6: ; %bb.0:802; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)803; GFX6-NEXT: v_bfe_u32 v0, v0, 15, 1804; GFX6-NEXT: v_bfe_u32 v1, v1, 15, 1805; GFX6-NEXT: s_setpc_b64 s[30:31]806;807; GFX8-LABEL: v_lshr_v2i16_15:808; GFX8: ; %bb.0:809; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)810; GFX8-NEXT: v_mov_b32_e32 v1, 31811; GFX8-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD812; GFX8-NEXT: v_lshrrev_b16_e32 v0, 15, v0813; GFX8-NEXT: v_or_b32_e32 v0, v0, v1814; GFX8-NEXT: s_setpc_b64 s[30:31]815;816; GFX9-LABEL: v_lshr_v2i16_15:817; GFX9: ; %bb.0:818; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)819; GFX9-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1]820; GFX9-NEXT: s_setpc_b64 s[30:31]821;822; GFX10PLUS-LABEL: v_lshr_v2i16_15:823; GFX10PLUS: ; %bb.0:824; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)825; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1]826; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]827 %result = lshr <2 x i16> %value, <i16 15, i16 15>828 ret <2 x i16> %result829}830 831define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {832; GFX6-LABEL: s_lshr_v2i16:833; GFX6: ; %bb.0:834; GFX6-NEXT: s_and_b32 s1, s1, 0xffff835; GFX6-NEXT: s_and_b32 s0, s0, 0xffff836; GFX6-NEXT: s_lshr_b32 s1, s1, s3837; GFX6-NEXT: s_lshr_b32 s0, s0, s2838; GFX6-NEXT: s_lshl_b32 s1, s1, 16839; GFX6-NEXT: s_or_b32 s0, s0, s1840; GFX6-NEXT: ; return to shader part epilog841;842; GFX8-LABEL: s_lshr_v2i16:843; GFX8: ; %bb.0:844; GFX8-NEXT: s_lshr_b32 s2, s0, 16845; GFX8-NEXT: s_lshr_b32 s3, s1, 16846; GFX8-NEXT: s_and_b32 s0, 0xffff, s0847; GFX8-NEXT: s_lshr_b32 s0, s0, s1848; GFX8-NEXT: s_lshr_b32 s1, s2, s3849; GFX8-NEXT: s_lshl_b32 s1, s1, 16850; GFX8-NEXT: s_or_b32 s0, s0, s1851; GFX8-NEXT: ; return to shader part epilog852;853; GFX9-LABEL: s_lshr_v2i16:854; GFX9: ; %bb.0:855; GFX9-NEXT: s_and_b32 s2, s0, 0xffff856; GFX9-NEXT: s_lshr_b32 s0, s0, 16857; GFX9-NEXT: s_lshr_b32 s3, s1, 16858; GFX9-NEXT: s_lshr_b32 s1, s2, s1859; GFX9-NEXT: s_lshr_b32 s0, s0, s3860; GFX9-NEXT: s_pack_ll_b32_b16 s0, s1, s0861; GFX9-NEXT: ; return to shader part epilog862;863; GFX10PLUS-LABEL: s_lshr_v2i16:864; GFX10PLUS: ; %bb.0:865; GFX10PLUS-NEXT: s_and_b32 s2, s0, 0xffff866; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 16867; GFX10PLUS-NEXT: s_lshr_b32 s3, s1, 16868; GFX10PLUS-NEXT: s_lshr_b32 s1, s2, s1869; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s3870; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s1, s0871; GFX10PLUS-NEXT: ; return to shader part epilog872 %result = lshr <2 x i16> %value, %amount873 %cast = bitcast <2 x i16> %result to i32874 ret i32 %cast875}876 877define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {878; GFX6-LABEL: lshr_v2i16_sv:879; GFX6: ; %bb.0:880; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0881; GFX6-NEXT: s_and_b32 s0, s0, 0xffff882; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0883; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1884; GFX6-NEXT: s_and_b32 s0, s1, 0xffff885; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1886; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1887; GFX6-NEXT: v_or_b32_e32 v0, v0, v1888; GFX6-NEXT: ; return to shader part epilog889;890; GFX8-LABEL: lshr_v2i16_sv:891; GFX8: ; %bb.0:892; GFX8-NEXT: s_lshr_b32 s1, s0, 16893; GFX8-NEXT: v_mov_b32_e32 v2, s1894; GFX8-NEXT: v_lshrrev_b16_e64 v1, v0, s0895; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD896; GFX8-NEXT: v_or_b32_e32 v0, v1, v0897; GFX8-NEXT: ; return to shader part epilog898;899; GFX9-LABEL: lshr_v2i16_sv:900; GFX9: ; %bb.0:901; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0902; GFX9-NEXT: ; return to shader part epilog903;904; GFX10PLUS-LABEL: lshr_v2i16_sv:905; GFX10PLUS: ; %bb.0:906; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v0, s0907; GFX10PLUS-NEXT: ; return to shader part epilog908 %result = lshr <2 x i16> %value, %amount909 %cast = bitcast <2 x i16> %result to float910 ret float %cast911}912 913define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {914; GFX6-LABEL: lshr_v2i16_vs:915; GFX6: ; %bb.0:916; GFX6-NEXT: s_and_b32 s0, s0, 0xffff917; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0918; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0919; GFX6-NEXT: s_and_b32 s0, s1, 0xffff920; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1921; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1922; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1923; GFX6-NEXT: v_or_b32_e32 v0, v0, v1924; GFX6-NEXT: ; return to shader part epilog925;926; GFX8-LABEL: lshr_v2i16_vs:927; GFX8: ; %bb.0:928; GFX8-NEXT: s_lshr_b32 s1, s0, 16929; GFX8-NEXT: v_mov_b32_e32 v2, s1930; GFX8-NEXT: v_lshrrev_b16_e32 v1, s0, v0931; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1932; GFX8-NEXT: v_or_b32_e32 v0, v1, v0933; GFX8-NEXT: ; return to shader part epilog934;935; GFX9-LABEL: lshr_v2i16_vs:936; GFX9: ; %bb.0:937; GFX9-NEXT: v_pk_lshrrev_b16 v0, s0, v0938; GFX9-NEXT: ; return to shader part epilog939;940; GFX10PLUS-LABEL: lshr_v2i16_vs:941; GFX10PLUS: ; %bb.0:942; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, s0, v0943; GFX10PLUS-NEXT: ; return to shader part epilog944 %result = lshr <2 x i16> %value, %amount945 %cast = bitcast <2 x i16> %result to float946 ret float %cast947}948 949; FIXME950; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) {951; %result = lshr <3 x i16> %value, %amount952; ret <3 x i16> %result953; }954 955; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) {956; %result = lshr <3 x i16> %value, %amount957; ret <3 x i16> %result958; }959 960define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) {961; GFX6-LABEL: v_lshr_v4i16:962; GFX6: ; %bb.0:963; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)964; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4965; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0966; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0967; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5968; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1969; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1970; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6971; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2972; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2973; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7974; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3975; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3976; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1977; GFX6-NEXT: v_or_b32_e32 v0, v0, v1978; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3979; GFX6-NEXT: v_or_b32_e32 v1, v2, v1980; GFX6-NEXT: s_setpc_b64 s[30:31]981;982; GFX8-LABEL: v_lshr_v4i16:983; GFX8: ; %bb.0:984; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)985; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v0986; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1987; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v1988; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1989; GFX8-NEXT: v_or_b32_e32 v0, v4, v0990; GFX8-NEXT: v_or_b32_e32 v1, v2, v1991; GFX8-NEXT: s_setpc_b64 s[30:31]992;993; GFX9-LABEL: v_lshr_v4i16:994; GFX9: ; %bb.0:995; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)996; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0997; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1998; GFX9-NEXT: s_setpc_b64 s[30:31]999;1000; GFX10PLUS-LABEL: v_lshr_v4i16:1001; GFX10PLUS: ; %bb.0:1002; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1003; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v2, v01004; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v1, v3, v11005; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1006 %result = lshr <4 x i16> %value, %amount1007 %cast = bitcast <4 x i16> %result to <2 x float>1008 ret <2 x float> %cast1009}1010 1011define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {1012; GFX6-LABEL: s_lshr_v4i16:1013; GFX6: ; %bb.0:1014; GFX6-NEXT: s_and_b32 s1, s1, 0xffff1015; GFX6-NEXT: s_and_b32 s0, s0, 0xffff1016; GFX6-NEXT: s_lshr_b32 s1, s1, s51017; GFX6-NEXT: s_and_b32 s3, s3, 0xffff1018; GFX6-NEXT: s_lshr_b32 s0, s0, s41019; GFX6-NEXT: s_and_b32 s2, s2, 0xffff1020; GFX6-NEXT: s_lshr_b32 s3, s3, s71021; GFX6-NEXT: s_lshl_b32 s1, s1, 161022; GFX6-NEXT: s_lshr_b32 s2, s2, s61023; GFX6-NEXT: s_or_b32 s0, s0, s11024; GFX6-NEXT: s_lshl_b32 s1, s3, 161025; GFX6-NEXT: s_or_b32 s1, s2, s11026; GFX6-NEXT: ; return to shader part epilog1027;1028; GFX8-LABEL: s_lshr_v4i16:1029; GFX8: ; %bb.0:1030; GFX8-NEXT: s_lshr_b32 s4, s0, 161031; GFX8-NEXT: s_lshr_b32 s6, s2, 161032; GFX8-NEXT: s_and_b32 s0, 0xffff, s01033; GFX8-NEXT: s_lshr_b32 s5, s1, 161034; GFX8-NEXT: s_lshr_b32 s7, s3, 161035; GFX8-NEXT: s_lshr_b32 s0, s0, s21036; GFX8-NEXT: s_lshr_b32 s2, s4, s61037; GFX8-NEXT: s_and_b32 s1, 0xffff, s11038; GFX8-NEXT: s_lshr_b32 s1, s1, s31039; GFX8-NEXT: s_lshr_b32 s3, s5, s71040; GFX8-NEXT: s_lshl_b32 s2, s2, 161041; GFX8-NEXT: s_or_b32 s0, s0, s21042; GFX8-NEXT: s_lshl_b32 s2, s3, 161043; GFX8-NEXT: s_or_b32 s1, s1, s21044; GFX8-NEXT: ; return to shader part epilog1045;1046; GFX9-LABEL: s_lshr_v4i16:1047; GFX9: ; %bb.0:1048; GFX9-NEXT: s_and_b32 s4, s0, 0xffff1049; GFX9-NEXT: s_lshr_b32 s0, s0, 161050; GFX9-NEXT: s_lshr_b32 s5, s2, 161051; GFX9-NEXT: s_lshr_b32 s2, s4, s21052; GFX9-NEXT: s_lshr_b32 s0, s0, s51053; GFX9-NEXT: s_pack_ll_b32_b16 s0, s2, s01054; GFX9-NEXT: s_and_b32 s2, s1, 0xffff1055; GFX9-NEXT: s_lshr_b32 s1, s1, 161056; GFX9-NEXT: s_lshr_b32 s4, s3, 161057; GFX9-NEXT: s_lshr_b32 s2, s2, s31058; GFX9-NEXT: s_lshr_b32 s1, s1, s41059; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s11060; GFX9-NEXT: ; return to shader part epilog1061;1062; GFX10PLUS-LABEL: s_lshr_v4i16:1063; GFX10PLUS: ; %bb.0:1064; GFX10PLUS-NEXT: s_and_b32 s4, s0, 0xffff1065; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 161066; GFX10PLUS-NEXT: s_lshr_b32 s5, s2, 161067; GFX10PLUS-NEXT: s_lshr_b32 s2, s4, s21068; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s51069; GFX10PLUS-NEXT: s_and_b32 s4, s1, 0xffff1070; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, 161071; GFX10PLUS-NEXT: s_lshr_b32 s5, s3, 161072; GFX10PLUS-NEXT: s_lshr_b32 s3, s4, s31073; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s51074; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s2, s01075; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s3, s11076; GFX10PLUS-NEXT: ; return to shader part epilog1077 %result = lshr <4 x i16> %value, %amount1078 %cast = bitcast <4 x i16> %result to <2 x i32>1079 ret <2 x i32> %cast1080}1081 1082; FIXME1083; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) {1084; %result = lshr <5 x i16> %value, %amount1085; ret <5 x i16> %result1086; }1087 1088; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) {1089; %result = lshr <5 x i16> %value, %amount1090; ret <5 x i16> %result1091; }1092 1093; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) {1094; %result = lshr <6 x i16> %value, %amount1095; %cast = bitcast <6 x i16> %result to <3 x float>1096; ret <3 x float> %cast1097; }1098 1099; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) {1100; %result = lshr <6 x i16> %value, %amount1101; %cast = bitcast <6 x i16> %result to <3 x i32>1102; ret <3 x i32> %cast1103; }1104 1105define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) {1106; GFX6-LABEL: v_lshr_v8i16:1107; GFX6: ; %bb.0:1108; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1109; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v81110; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v01111; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v01112; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v91113; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v11114; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v11115; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v101116; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v21117; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v21118; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v111119; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v31120; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v31121; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v121122; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v41123; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v41124; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v131125; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v51126; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v51127; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v141128; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v61129; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v61130; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v151131; GFX6-NEXT: v_and_b32_e32 v7, 0xffff, v71132; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v11133; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v71134; GFX6-NEXT: v_or_b32_e32 v0, v0, v11135; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v31136; GFX6-NEXT: v_or_b32_e32 v1, v2, v11137; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v51138; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v71139; GFX6-NEXT: v_or_b32_e32 v2, v4, v21140; GFX6-NEXT: v_or_b32_e32 v3, v6, v31141; GFX6-NEXT: s_setpc_b64 s[30:31]1142;1143; GFX8-LABEL: v_lshr_v8i16:1144; GFX8: ; %bb.0:1145; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1146; GFX8-NEXT: v_lshrrev_b16_e32 v8, v4, v01147; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11148; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v11149; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11150; GFX8-NEXT: v_or_b32_e32 v1, v4, v11151; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v21152; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11153; GFX8-NEXT: v_or_b32_e32 v2, v4, v21154; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v31155; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11156; GFX8-NEXT: v_or_b32_e32 v0, v8, v01157; GFX8-NEXT: v_or_b32_e32 v3, v4, v31158; GFX8-NEXT: s_setpc_b64 s[30:31]1159;1160; GFX9-LABEL: v_lshr_v8i16:1161; GFX9: ; %bb.0:1162; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1163; GFX9-NEXT: v_pk_lshrrev_b16 v0, v4, v01164; GFX9-NEXT: v_pk_lshrrev_b16 v1, v5, v11165; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v21166; GFX9-NEXT: v_pk_lshrrev_b16 v3, v7, v31167; GFX9-NEXT: s_setpc_b64 s[30:31]1168;1169; GFX10PLUS-LABEL: v_lshr_v8i16:1170; GFX10PLUS: ; %bb.0:1171; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1172; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v0, v4, v01173; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v1, v5, v11174; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v2, v6, v21175; GFX10PLUS-NEXT: v_pk_lshrrev_b16 v3, v7, v31176; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1177 %result = lshr <8 x i16> %value, %amount1178 %cast = bitcast <8 x i16> %result to <4 x float>1179 ret <4 x float> %cast1180}1181 1182define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {1183; GFX6-LABEL: s_lshr_v8i16:1184; GFX6: ; %bb.0:1185; GFX6-NEXT: s_and_b32 s1, s1, 0xffff1186; GFX6-NEXT: s_and_b32 s0, s0, 0xffff1187; GFX6-NEXT: s_lshr_b32 s1, s1, s91188; GFX6-NEXT: s_and_b32 s3, s3, 0xffff1189; GFX6-NEXT: s_lshr_b32 s0, s0, s81190; GFX6-NEXT: s_and_b32 s2, s2, 0xffff1191; GFX6-NEXT: s_lshr_b32 s3, s3, s111192; GFX6-NEXT: s_and_b32 s5, s5, 0xffff1193; GFX6-NEXT: s_and_b32 s7, s7, 0xffff1194; GFX6-NEXT: s_lshl_b32 s1, s1, 161195; GFX6-NEXT: s_lshr_b32 s2, s2, s101196; GFX6-NEXT: s_and_b32 s4, s4, 0xffff1197; GFX6-NEXT: s_lshr_b32 s5, s5, s131198; GFX6-NEXT: s_and_b32 s6, s6, 0xffff1199; GFX6-NEXT: s_lshr_b32 s7, s7, s151200; GFX6-NEXT: s_or_b32 s0, s0, s11201; GFX6-NEXT: s_lshl_b32 s1, s3, 161202; GFX6-NEXT: s_lshr_b32 s4, s4, s121203; GFX6-NEXT: s_lshr_b32 s6, s6, s141204; GFX6-NEXT: s_or_b32 s1, s2, s11205; GFX6-NEXT: s_lshl_b32 s2, s5, 161206; GFX6-NEXT: s_lshl_b32 s3, s7, 161207; GFX6-NEXT: s_or_b32 s2, s4, s21208; GFX6-NEXT: s_or_b32 s3, s6, s31209; GFX6-NEXT: ; return to shader part epilog1210;1211; GFX8-LABEL: s_lshr_v8i16:1212; GFX8: ; %bb.0:1213; GFX8-NEXT: s_lshr_b32 s8, s0, 161214; GFX8-NEXT: s_lshr_b32 s12, s4, 161215; GFX8-NEXT: s_and_b32 s0, 0xffff, s01216; GFX8-NEXT: s_lshr_b32 s9, s1, 161217; GFX8-NEXT: s_lshr_b32 s13, s5, 161218; GFX8-NEXT: s_lshr_b32 s0, s0, s41219; GFX8-NEXT: s_lshr_b32 s4, s8, s121220; GFX8-NEXT: s_and_b32 s1, 0xffff, s11221; GFX8-NEXT: s_lshr_b32 s10, s2, 161222; GFX8-NEXT: s_lshr_b32 s14, s6, 161223; GFX8-NEXT: s_lshr_b32 s1, s1, s51224; GFX8-NEXT: s_lshr_b32 s5, s9, s131225; GFX8-NEXT: s_and_b32 s2, 0xffff, s21226; GFX8-NEXT: s_lshl_b32 s4, s4, 161227; GFX8-NEXT: s_lshr_b32 s11, s3, 161228; GFX8-NEXT: s_lshr_b32 s15, s7, 161229; GFX8-NEXT: s_lshr_b32 s2, s2, s61230; GFX8-NEXT: s_lshr_b32 s6, s10, s141231; GFX8-NEXT: s_and_b32 s3, 0xffff, s31232; GFX8-NEXT: s_or_b32 s0, s0, s41233; GFX8-NEXT: s_lshl_b32 s4, s5, 161234; GFX8-NEXT: s_lshr_b32 s3, s3, s71235; GFX8-NEXT: s_lshr_b32 s7, s11, s151236; GFX8-NEXT: s_or_b32 s1, s1, s41237; GFX8-NEXT: s_lshl_b32 s4, s6, 161238; GFX8-NEXT: s_or_b32 s2, s2, s41239; GFX8-NEXT: s_lshl_b32 s4, s7, 161240; GFX8-NEXT: s_or_b32 s3, s3, s41241; GFX8-NEXT: ; return to shader part epilog1242;1243; GFX9-LABEL: s_lshr_v8i16:1244; GFX9: ; %bb.0:1245; GFX9-NEXT: s_and_b32 s8, s0, 0xffff1246; GFX9-NEXT: s_lshr_b32 s0, s0, 161247; GFX9-NEXT: s_lshr_b32 s9, s4, 161248; GFX9-NEXT: s_lshr_b32 s4, s8, s41249; GFX9-NEXT: s_lshr_b32 s0, s0, s91250; GFX9-NEXT: s_pack_ll_b32_b16 s0, s4, s01251; GFX9-NEXT: s_and_b32 s4, s1, 0xffff1252; GFX9-NEXT: s_lshr_b32 s1, s1, 161253; GFX9-NEXT: s_lshr_b32 s8, s5, 161254; GFX9-NEXT: s_lshr_b32 s4, s4, s51255; GFX9-NEXT: s_lshr_b32 s1, s1, s81256; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s11257; GFX9-NEXT: s_and_b32 s4, s2, 0xffff1258; GFX9-NEXT: s_lshr_b32 s2, s2, 161259; GFX9-NEXT: s_lshr_b32 s5, s6, 161260; GFX9-NEXT: s_lshr_b32 s4, s4, s61261; GFX9-NEXT: s_lshr_b32 s2, s2, s51262; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s21263; GFX9-NEXT: s_and_b32 s4, s3, 0xffff1264; GFX9-NEXT: s_lshr_b32 s3, s3, 161265; GFX9-NEXT: s_lshr_b32 s5, s7, 161266; GFX9-NEXT: s_lshr_b32 s4, s4, s71267; GFX9-NEXT: s_lshr_b32 s3, s3, s51268; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s31269; GFX9-NEXT: ; return to shader part epilog1270;1271; GFX10PLUS-LABEL: s_lshr_v8i16:1272; GFX10PLUS: ; %bb.0:1273; GFX10PLUS-NEXT: s_and_b32 s8, s0, 0xffff1274; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, 161275; GFX10PLUS-NEXT: s_lshr_b32 s9, s4, 161276; GFX10PLUS-NEXT: s_lshr_b32 s4, s8, s41277; GFX10PLUS-NEXT: s_lshr_b32 s0, s0, s91278; GFX10PLUS-NEXT: s_and_b32 s8, s1, 0xffff1279; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, 161280; GFX10PLUS-NEXT: s_lshr_b32 s9, s5, 161281; GFX10PLUS-NEXT: s_lshr_b32 s5, s8, s51282; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, s91283; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s4, s01284; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s5, s11285; GFX10PLUS-NEXT: s_and_b32 s4, s2, 0xffff1286; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, 161287; GFX10PLUS-NEXT: s_lshr_b32 s5, s6, 161288; GFX10PLUS-NEXT: s_lshr_b32 s4, s4, s61289; GFX10PLUS-NEXT: s_lshr_b32 s2, s2, s51290; GFX10PLUS-NEXT: s_and_b32 s5, s3, 0xffff1291; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, 161292; GFX10PLUS-NEXT: s_lshr_b32 s6, s7, 161293; GFX10PLUS-NEXT: s_lshr_b32 s5, s5, s71294; GFX10PLUS-NEXT: s_lshr_b32 s3, s3, s61295; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s2, s4, s21296; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s3, s5, s31297; GFX10PLUS-NEXT: ; return to shader part epilog1298 %result = lshr <8 x i16> %value, %amount1299 %cast = bitcast <8 x i16> %result to <4 x i32>1300 ret <4 x i32> %cast1301}1302 1303define i64 @v_lshr_i64(i64 %value, i64 %amount) {1304; GFX6-LABEL: v_lshr_i64:1305; GFX6: ; %bb.0:1306; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1307; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v21308; GFX6-NEXT: s_setpc_b64 s[30:31]1309;1310; GFX8-LABEL: v_lshr_i64:1311; GFX8: ; %bb.0:1312; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1313; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]1314; GFX8-NEXT: s_setpc_b64 s[30:31]1315;1316; GFX9-LABEL: v_lshr_i64:1317; GFX9: ; %bb.0:1318; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1319; GFX9-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]1320; GFX9-NEXT: s_setpc_b64 s[30:31]1321;1322; GFX10PLUS-LABEL: v_lshr_i64:1323; GFX10PLUS: ; %bb.0:1324; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1325; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]1326; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1327 %result = lshr i64 %value, %amount1328 ret i64 %result1329}1330 1331define i64 @v_lshr_i64_63(i64 %value) {1332; GCN-LABEL: v_lshr_i64_63:1333; GCN: ; %bb.0:1334; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1335; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v11336; GCN-NEXT: v_mov_b32_e32 v1, 01337; GCN-NEXT: s_setpc_b64 s[30:31]1338;1339; GFX10PLUS-LABEL: v_lshr_i64_63:1340; GFX10PLUS: ; %bb.0:1341; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1342; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 31, v11343; GFX10PLUS-NEXT: v_mov_b32_e32 v1, 01344; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1345 %result = lshr i64 %value, 631346 ret i64 %result1347}1348 1349define i64 @v_lshr_i64_33(i64 %value) {1350; GCN-LABEL: v_lshr_i64_33:1351; GCN: ; %bb.0:1352; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1353; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v11354; GCN-NEXT: v_mov_b32_e32 v1, 01355; GCN-NEXT: s_setpc_b64 s[30:31]1356;1357; GFX10PLUS-LABEL: v_lshr_i64_33:1358; GFX10PLUS: ; %bb.0:1359; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1360; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 1, v11361; GFX10PLUS-NEXT: v_mov_b32_e32 v1, 01362; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1363 %result = lshr i64 %value, 331364 ret i64 %result1365}1366 1367define i64 @v_lshr_i64_32(i64 %value) {1368; GCN-LABEL: v_lshr_i64_32:1369; GCN: ; %bb.0:1370; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1371; GCN-NEXT: v_mov_b32_e32 v0, v11372; GCN-NEXT: v_mov_b32_e32 v1, 01373; GCN-NEXT: s_setpc_b64 s[30:31]1374;1375; GFX10-LABEL: v_lshr_i64_32:1376; GFX10: ; %bb.0:1377; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1378; GFX10-NEXT: v_mov_b32_e32 v0, v11379; GFX10-NEXT: v_mov_b32_e32 v1, 01380; GFX10-NEXT: s_setpc_b64 s[30:31]1381;1382; GFX11-LABEL: v_lshr_i64_32:1383; GFX11: ; %bb.0:1384; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1385; GFX11-NEXT: v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, 01386; GFX11-NEXT: s_setpc_b64 s[30:31]1387 %result = lshr i64 %value, 321388 ret i64 %result1389}1390 1391define i64 @v_lshr_i64_31(i64 %value) {1392; GFX6-LABEL: v_lshr_i64_31:1393; GFX6: ; %bb.0:1394; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1395; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 311396; GFX6-NEXT: s_setpc_b64 s[30:31]1397;1398; GFX8-LABEL: v_lshr_i64_31:1399; GFX8: ; %bb.0:1400; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1401; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]1402; GFX8-NEXT: s_setpc_b64 s[30:31]1403;1404; GFX9-LABEL: v_lshr_i64_31:1405; GFX9: ; %bb.0:1406; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1407; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]1408; GFX9-NEXT: s_setpc_b64 s[30:31]1409;1410; GFX10PLUS-LABEL: v_lshr_i64_31:1411; GFX10PLUS: ; %bb.0:1412; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1413; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]1414; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1415 %result = lshr i64 %value, 311416 ret i64 %result1417}1418 1419define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) {1420; GCN-LABEL: s_lshr_i64:1421; GCN: ; %bb.0:1422; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s21423; GCN-NEXT: ; return to shader part epilog1424;1425; GFX10PLUS-LABEL: s_lshr_i64:1426; GFX10PLUS: ; %bb.0:1427; GFX10PLUS-NEXT: s_lshr_b64 s[0:1], s[0:1], s21428; GFX10PLUS-NEXT: ; return to shader part epilog1429 %result = lshr i64 %value, %amount1430 ret i64 %result1431}1432 1433define amdgpu_ps i64 @s_lshr_i64_63(i64 inreg %value) {1434; GCN-LABEL: s_lshr_i64_63:1435; GCN: ; %bb.0:1436; GCN-NEXT: s_lshr_b32 s0, s1, 311437; GCN-NEXT: s_mov_b32 s1, 01438; GCN-NEXT: ; return to shader part epilog1439;1440; GFX10PLUS-LABEL: s_lshr_i64_63:1441; GFX10PLUS: ; %bb.0:1442; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 311443; GFX10PLUS-NEXT: s_mov_b32 s1, 01444; GFX10PLUS-NEXT: ; return to shader part epilog1445 %result = lshr i64 %value, 631446 ret i64 %result1447}1448 1449define amdgpu_ps i64 @s_lshr_i64_33(i64 inreg %value) {1450; GCN-LABEL: s_lshr_i64_33:1451; GCN: ; %bb.0:1452; GCN-NEXT: s_lshr_b32 s0, s1, 11453; GCN-NEXT: s_mov_b32 s1, 01454; GCN-NEXT: ; return to shader part epilog1455;1456; GFX10PLUS-LABEL: s_lshr_i64_33:1457; GFX10PLUS: ; %bb.0:1458; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 11459; GFX10PLUS-NEXT: s_mov_b32 s1, 01460; GFX10PLUS-NEXT: ; return to shader part epilog1461 %result = lshr i64 %value, 331462 ret i64 %result1463}1464 1465define amdgpu_ps i64 @s_lshr_i64_32(i64 inreg %value) {1466; GCN-LABEL: s_lshr_i64_32:1467; GCN: ; %bb.0:1468; GCN-NEXT: s_mov_b32 s0, s11469; GCN-NEXT: s_mov_b32 s1, 01470; GCN-NEXT: ; return to shader part epilog1471;1472; GFX10PLUS-LABEL: s_lshr_i64_32:1473; GFX10PLUS: ; %bb.0:1474; GFX10PLUS-NEXT: s_mov_b32 s0, s11475; GFX10PLUS-NEXT: s_mov_b32 s1, 01476; GFX10PLUS-NEXT: ; return to shader part epilog1477 %result = lshr i64 %value, 321478 ret i64 %result1479}1480 1481define amdgpu_ps i64 @s_lshr_i64_31(i64 inreg %value) {1482; GCN-LABEL: s_lshr_i64_31:1483; GCN: ; %bb.0:1484; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 311485; GCN-NEXT: ; return to shader part epilog1486;1487; GFX10PLUS-LABEL: s_lshr_i64_31:1488; GFX10PLUS: ; %bb.0:1489; GFX10PLUS-NEXT: s_lshr_b64 s[0:1], s[0:1], 311490; GFX10PLUS-NEXT: ; return to shader part epilog1491 %result = lshr i64 %value, 311492 ret i64 %result1493}1494 1495define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) {1496; GFX6-LABEL: lshr_i64_sv:1497; GFX6: ; %bb.0:1498; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v01499; GFX6-NEXT: ; return to shader part epilog1500;1501; GFX8-LABEL: lshr_i64_sv:1502; GFX8: ; %bb.0:1503; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]1504; GFX8-NEXT: ; return to shader part epilog1505;1506; GFX9-LABEL: lshr_i64_sv:1507; GFX9: ; %bb.0:1508; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]1509; GFX9-NEXT: ; return to shader part epilog1510;1511; GFX10PLUS-LABEL: lshr_i64_sv:1512; GFX10PLUS: ; %bb.0:1513; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]1514; GFX10PLUS-NEXT: ; return to shader part epilog1515 %result = lshr i64 %value, %amount1516 %cast = bitcast i64 %result to <2 x float>1517 ret <2 x float> %cast1518}1519 1520define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) {1521; GFX6-LABEL: lshr_i64_vs:1522; GFX6: ; %bb.0:1523; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s01524; GFX6-NEXT: ; return to shader part epilog1525;1526; GFX8-LABEL: lshr_i64_vs:1527; GFX8: ; %bb.0:1528; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1]1529; GFX8-NEXT: ; return to shader part epilog1530;1531; GFX9-LABEL: lshr_i64_vs:1532; GFX9: ; %bb.0:1533; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1]1534; GFX9-NEXT: ; return to shader part epilog1535;1536; GFX10PLUS-LABEL: lshr_i64_vs:1537; GFX10PLUS: ; %bb.0:1538; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1]1539; GFX10PLUS-NEXT: ; return to shader part epilog1540 %result = lshr i64 %value, %amount1541 %cast = bitcast i64 %result to <2 x float>1542 ret <2 x float> %cast1543}1544 1545define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) {1546; GFX6-LABEL: v_lshr_v2i64:1547; GFX6: ; %bb.0:1548; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1549; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v41550; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v61551; GFX6-NEXT: s_setpc_b64 s[30:31]1552;1553; GFX8-LABEL: v_lshr_v2i64:1554; GFX8: ; %bb.0:1555; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1556; GFX8-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]1557; GFX8-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]1558; GFX8-NEXT: s_setpc_b64 s[30:31]1559;1560; GFX9-LABEL: v_lshr_v2i64:1561; GFX9: ; %bb.0:1562; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1563; GFX9-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]1564; GFX9-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]1565; GFX9-NEXT: s_setpc_b64 s[30:31]1566;1567; GFX10PLUS-LABEL: v_lshr_v2i64:1568; GFX10PLUS: ; %bb.0:1569; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1570; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]1571; GFX10PLUS-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]1572; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1573 %result = lshr <2 x i64> %value, %amount1574 ret <2 x i64> %result1575}1576 1577define <2 x i64> @v_lshr_v2i64_31(<2 x i64> %value) {1578; GFX6-LABEL: v_lshr_v2i64_31:1579; GFX6: ; %bb.0:1580; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1581; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 311582; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 311583; GFX6-NEXT: s_setpc_b64 s[30:31]1584;1585; GFX8-LABEL: v_lshr_v2i64_31:1586; GFX8: ; %bb.0:1587; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1588; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]1589; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3]1590; GFX8-NEXT: s_setpc_b64 s[30:31]1591;1592; GFX9-LABEL: v_lshr_v2i64_31:1593; GFX9: ; %bb.0:1594; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1595; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]1596; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3]1597; GFX9-NEXT: s_setpc_b64 s[30:31]1598;1599; GFX10PLUS-LABEL: v_lshr_v2i64_31:1600; GFX10PLUS: ; %bb.0:1601; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1602; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]1603; GFX10PLUS-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3]1604; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1605 %result = lshr <2 x i64> %value, <i64 31, i64 31>1606 ret <2 x i64> %result1607}1608 1609define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) {1610; GCN-LABEL: s_lshr_v2i64:1611; GCN: ; %bb.0:1612; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s41613; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s61614; GCN-NEXT: ; return to shader part epilog1615;1616; GFX10PLUS-LABEL: s_lshr_v2i64:1617; GFX10PLUS: ; %bb.0:1618; GFX10PLUS-NEXT: s_lshr_b64 s[0:1], s[0:1], s41619; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[2:3], s61620; GFX10PLUS-NEXT: ; return to shader part epilog1621 %result = lshr <2 x i64> %value, %amount1622 ret <2 x i64> %result1623}1624 1625define i65 @v_lshr_i65(i65 %value, i65 %amount) {1626; GFX6-LABEL: v_lshr_i65:1627; GFX6: ; %bb.0:1628; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1629; GFX6-NEXT: v_mov_b32_e32 v4, 11630; GFX6-NEXT: v_mov_b32_e32 v5, 01631; GFX6-NEXT: v_and_b32_e32 v4, 1, v21632; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v31633; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xffffffc0, v31634; GFX6-NEXT: v_lshr_b64 v[6:7], v[0:1], v31635; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v81636; GFX6-NEXT: v_lshr_b64 v[10:11], v[4:5], v31637; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v21638; GFX6-NEXT: v_or_b32_e32 v6, v6, v81639; GFX6-NEXT: v_or_b32_e32 v7, v7, v91640; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31641; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc1642; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc1643; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31644; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]1645; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1646; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc1647; GFX6-NEXT: s_setpc_b64 s[30:31]1648;1649; GFX8-LABEL: v_lshr_i65:1650; GFX8: ; %bb.0:1651; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1652; GFX8-NEXT: v_mov_b32_e32 v4, 11653; GFX8-NEXT: v_mov_b32_e32 v5, 01654; GFX8-NEXT: v_and_b32_e32 v4, 1, v21655; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v31656; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0xffffffc0, v31657; GFX8-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1658; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5]1659; GFX8-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5]1660; GFX8-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5]1661; GFX8-NEXT: v_or_b32_e32 v6, v6, v81662; GFX8-NEXT: v_or_b32_e32 v7, v7, v91663; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31664; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc1665; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc1666; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31667; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]1668; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1669; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc1670; GFX8-NEXT: s_setpc_b64 s[30:31]1671;1672; GFX9-LABEL: v_lshr_i65:1673; GFX9: ; %bb.0:1674; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1675; GFX9-NEXT: v_mov_b32_e32 v4, 11676; GFX9-NEXT: v_mov_b32_e32 v5, 01677; GFX9-NEXT: v_and_b32_e32 v4, 1, v21678; GFX9-NEXT: v_sub_u32_e32 v8, 64, v31679; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffc0, v31680; GFX9-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1681; GFX9-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5]1682; GFX9-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5]1683; GFX9-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5]1684; GFX9-NEXT: v_or_b32_e32 v6, v6, v81685; GFX9-NEXT: v_or_b32_e32 v7, v7, v91686; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31687; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc1688; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc1689; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31690; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]1691; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1692; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc1693; GFX9-NEXT: s_setpc_b64 s[30:31]1694;1695; GFX10-LABEL: v_lshr_i65:1696; GFX10: ; %bb.0:1697; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1698; GFX10-NEXT: v_mov_b32_e32 v4, 11699; GFX10-NEXT: v_mov_b32_e32 v5, 01700; GFX10-NEXT: v_and_b32_e32 v4, 1, v21701; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v31702; GFX10-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v31703; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1704; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v31705; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v31706; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5]1707; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5]1708; GFX10-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5]1709; GFX10-NEXT: v_or_b32_e32 v2, v6, v81710; GFX10-NEXT: v_or_b32_e32 v6, v7, v91711; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo1712; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo1713; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s41714; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s41715; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo1716; GFX10-NEXT: s_setpc_b64 s[30:31]1717;1718; GFX11-LABEL: v_lshr_i65:1719; GFX11: ; %bb.0:1720; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1721; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v31722; GFX11-NEXT: v_mov_b32_e32 v4, 11723; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 1, v21724; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v31725; GFX11-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v31726; GFX11-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1727; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v31728; GFX11-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5]1729; GFX11-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5]1730; GFX11-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5]1731; GFX11-NEXT: v_or_b32_e32 v2, v6, v81732; GFX11-NEXT: v_or_b32_e32 v6, v7, v91733; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo1734; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo1735; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s01736; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s01737; GFX11-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo1738; GFX11-NEXT: s_setpc_b64 s[30:31]1739 %result = lshr i65 %value, %amount1740 ret i65 %result1741}1742 1743define i65 @v_lshr_i65_33(i65 %value) {1744; GFX6-LABEL: v_lshr_i65_33:1745; GFX6: ; %bb.0:1746; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1747; GFX6-NEXT: v_mov_b32_e32 v3, v11748; GFX6-NEXT: v_mov_b32_e32 v0, 11749; GFX6-NEXT: v_mov_b32_e32 v1, 01750; GFX6-NEXT: v_and_b32_e32 v0, 1, v21751; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 311752; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v31753; GFX6-NEXT: v_or_b32_e32 v0, v0, v21754; GFX6-NEXT: v_mov_b32_e32 v2, 01755; GFX6-NEXT: s_setpc_b64 s[30:31]1756;1757; GFX8-LABEL: v_lshr_i65_33:1758; GFX8: ; %bb.0:1759; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1760; GFX8-NEXT: v_mov_b32_e32 v3, v11761; GFX8-NEXT: v_mov_b32_e32 v0, 11762; GFX8-NEXT: v_mov_b32_e32 v1, 01763; GFX8-NEXT: v_and_b32_e32 v0, 1, v21764; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1765; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v31766; GFX8-NEXT: v_or_b32_e32 v0, v0, v21767; GFX8-NEXT: v_mov_b32_e32 v2, 01768; GFX8-NEXT: s_setpc_b64 s[30:31]1769;1770; GFX9-LABEL: v_lshr_i65_33:1771; GFX9: ; %bb.0:1772; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1773; GFX9-NEXT: v_mov_b32_e32 v3, v11774; GFX9-NEXT: v_mov_b32_e32 v0, 11775; GFX9-NEXT: v_mov_b32_e32 v1, 01776; GFX9-NEXT: v_and_b32_e32 v0, 1, v21777; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1778; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v31779; GFX9-NEXT: v_or_b32_e32 v0, v0, v21780; GFX9-NEXT: v_mov_b32_e32 v2, 01781; GFX9-NEXT: s_setpc_b64 s[30:31]1782;1783; GFX10-LABEL: v_lshr_i65_33:1784; GFX10: ; %bb.0:1785; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1786; GFX10-NEXT: v_mov_b32_e32 v3, v11787; GFX10-NEXT: v_mov_b32_e32 v0, 11788; GFX10-NEXT: v_mov_b32_e32 v1, 01789; GFX10-NEXT: v_and_b32_e32 v0, 1, v21790; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v31791; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1792; GFX10-NEXT: v_or_b32_e32 v0, v0, v21793; GFX10-NEXT: v_mov_b32_e32 v2, 01794; GFX10-NEXT: s_setpc_b64 s[30:31]1795;1796; GFX11-LABEL: v_lshr_i65_33:1797; GFX11: ; %bb.0:1798; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1799; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v0, 11800; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 1, v21801; GFX11-NEXT: v_lshrrev_b32_e32 v2, 1, v31802; GFX11-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1803; GFX11-NEXT: v_or_b32_e32 v0, v0, v21804; GFX11-NEXT: v_mov_b32_e32 v2, 01805; GFX11-NEXT: s_setpc_b64 s[30:31]1806 %result = lshr i65 %value, 331807 ret i65 %result1808}1809 1810define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) {1811; GCN-LABEL: s_lshr_i65:1812; GCN: ; %bb.0:1813; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 11814; GCN-NEXT: s_sub_i32 s10, s3, 641815; GCN-NEXT: s_sub_i32 s8, 64, s31816; GCN-NEXT: s_cmp_lt_u32 s3, 641817; GCN-NEXT: s_cselect_b32 s11, 1, 01818; GCN-NEXT: s_cmp_eq_u32 s3, 01819; GCN-NEXT: s_cselect_b32 s12, 1, 01820; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s31821; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s31822; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s81823; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]1824; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s101825; GCN-NEXT: s_cmp_lg_u32 s11, 01826; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]1827; GCN-NEXT: s_cmp_lg_u32 s12, 01828; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]1829; GCN-NEXT: s_cmp_lg_u32 s11, 01830; GCN-NEXT: s_cselect_b32 s2, s6, 01831; GCN-NEXT: ; return to shader part epilog1832;1833; GFX10PLUS-LABEL: s_lshr_i65:1834; GFX10PLUS: ; %bb.0:1835; GFX10PLUS-NEXT: s_and_b64 s[4:5], s[2:3], 11836; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 641837; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s31838; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 641839; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 01840; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 01841; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 01842; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s31843; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s21844; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[4:5], s31845; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]1846; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[4:5], s101847; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 01848; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]1849; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 01850; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]1851; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 01852; GFX10PLUS-NEXT: s_cselect_b32 s2, s2, 01853; GFX10PLUS-NEXT: ; return to shader part epilog1854 %result = lshr i65 %value, %amount1855 ret i65 %result1856}1857 1858define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) {1859; GCN-LABEL: s_lshr_i65_33:1860; GCN: ; %bb.0:1861; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 11862; GCN-NEXT: s_lshr_b32 s4, s1, 11863; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 311864; GCN-NEXT: s_or_b32 s0, s0, s41865; GCN-NEXT: s_mov_b32 s2, 01866; GCN-NEXT: ; return to shader part epilog1867;1868; GFX10PLUS-LABEL: s_lshr_i65_33:1869; GFX10PLUS: ; %bb.0:1870; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], 11871; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 11872; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 311873; GFX10PLUS-NEXT: s_mov_b32 s2, 01874; GFX10PLUS-NEXT: s_or_b32 s0, s0, s41875; GFX10PLUS-NEXT: ; return to shader part epilog1876 %result = lshr i65 %value, 331877 ret i65 %result1878}1879 1880; FIXME: Argument lowering asserts1881; define <2 x i65> @v_lshr_v2i65(<2 x i65> %value, <2 x i65> %amount) {1882; %result = lshr <2 x i65> %value, %amount1883; ret <2 x i65> %result1884; }1885 1886; define amdgpu_ps <2 x i65> @s_lshr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) {1887; %result = lshr <2 x i65> %value, %amount1888; ret <2 x i65> %result1889; }1890