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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1250 < %s | FileCheck %s3 4declare i64 @llvm.umin.i64(i64, i64)5declare i64 @llvm.umax.i64(i64, i64)6declare i64 @llvm.smin.i64(i64, i64)7declare i64 @llvm.smax.i64(i64, i64)8declare i64 @llvm.abs.i64(i64, i1)9 10declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)11declare <4 x i64> @llvm.umax.v4i64(<4 x i64>, <4 x i64>)12declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)13declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)14 15define i64 @test_umin_i64(i64 %a, i64 %b) {16; CHECK-LABEL: test_umin_i64:17; CHECK: ; %bb.0:18; CHECK-NEXT: s_wait_loadcnt_dscnt 0x019; CHECK-NEXT: s_wait_kmcnt 0x020; CHECK-NEXT: v_min_u64 v[0:1], v[0:1], v[2:3]21; CHECK-NEXT: s_set_pc_i64 s[30:31]22 %r = call i64 @llvm.umin.i64(i64 %a, i64 %b)23 ret i64 %r24}25 26define i64 @test_umax_i64(i64 %a, i64 %b) {27; CHECK-LABEL: test_umax_i64:28; CHECK: ; %bb.0:29; CHECK-NEXT: s_wait_loadcnt_dscnt 0x030; CHECK-NEXT: s_wait_kmcnt 0x031; CHECK-NEXT: v_max_u64 v[0:1], v[0:1], v[2:3]32; CHECK-NEXT: s_set_pc_i64 s[30:31]33 %r = call i64 @llvm.umax.i64(i64 %a, i64 %b)34 ret i64 %r35}36 37define i64 @test_smin_i64(i64 %a, i64 %b) {38; CHECK-LABEL: test_smin_i64:39; CHECK: ; %bb.0:40; CHECK-NEXT: s_wait_loadcnt_dscnt 0x041; CHECK-NEXT: s_wait_kmcnt 0x042; CHECK-NEXT: v_min_i64 v[0:1], v[0:1], v[2:3]43; CHECK-NEXT: s_set_pc_i64 s[30:31]44 %r = call i64 @llvm.smin.i64(i64 %a, i64 %b)45 ret i64 %r46}47 48define i64 @test_smax_i64(i64 %a, i64 %b) {49; CHECK-LABEL: test_smax_i64:50; CHECK: ; %bb.0:51; CHECK-NEXT: s_wait_loadcnt_dscnt 0x052; CHECK-NEXT: s_wait_kmcnt 0x053; CHECK-NEXT: v_max_i64 v[0:1], v[0:1], v[2:3]54; CHECK-NEXT: s_set_pc_i64 s[30:31]55 %r = call i64 @llvm.smax.i64(i64 %a, i64 %b)56 ret i64 %r57}58 59define <4 x i64> @test_umin_v4i64(<4 x i64> %a, <4 x i64> %b) {60; CHECK-LABEL: test_umin_v4i64:61; CHECK: ; %bb.0:62; CHECK-NEXT: s_wait_loadcnt_dscnt 0x063; CHECK-NEXT: s_wait_kmcnt 0x064; CHECK-NEXT: v_min_u64 v[0:1], v[0:1], v[8:9]65; CHECK-NEXT: v_min_u64 v[2:3], v[2:3], v[10:11]66; CHECK-NEXT: v_min_u64 v[4:5], v[4:5], v[12:13]67; CHECK-NEXT: v_min_u64 v[6:7], v[6:7], v[14:15]68; CHECK-NEXT: s_set_pc_i64 s[30:31]69 %r = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %a, <4 x i64> %b)70 ret <4 x i64> %r71}72 73define <4 x i64> @test_umax_v4i64(<4 x i64> %a, <4 x i64> %b) {74; CHECK-LABEL: test_umax_v4i64:75; CHECK: ; %bb.0:76; CHECK-NEXT: s_wait_loadcnt_dscnt 0x077; CHECK-NEXT: s_wait_kmcnt 0x078; CHECK-NEXT: v_max_u64 v[0:1], v[0:1], v[8:9]79; CHECK-NEXT: v_max_u64 v[2:3], v[2:3], v[10:11]80; CHECK-NEXT: v_max_u64 v[4:5], v[4:5], v[12:13]81; CHECK-NEXT: v_max_u64 v[6:7], v[6:7], v[14:15]82; CHECK-NEXT: s_set_pc_i64 s[30:31]83 %r = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %a, <4 x i64> %b)84 ret <4 x i64> %r85}86 87define <4 x i64> @test_smin_v4i64(<4 x i64> %a, <4 x i64> %b) {88; CHECK-LABEL: test_smin_v4i64:89; CHECK: ; %bb.0:90; CHECK-NEXT: s_wait_loadcnt_dscnt 0x091; CHECK-NEXT: s_wait_kmcnt 0x092; CHECK-NEXT: v_min_i64 v[0:1], v[0:1], v[8:9]93; CHECK-NEXT: v_min_i64 v[2:3], v[2:3], v[10:11]94; CHECK-NEXT: v_min_i64 v[4:5], v[4:5], v[12:13]95; CHECK-NEXT: v_min_i64 v[6:7], v[6:7], v[14:15]96; CHECK-NEXT: s_set_pc_i64 s[30:31]97 %r = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b)98 ret <4 x i64> %r99}100 101define <4 x i64> @test_smax_v4i64(<4 x i64> %a, <4 x i64> %b) {102; CHECK-LABEL: test_smax_v4i64:103; CHECK: ; %bb.0:104; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0105; CHECK-NEXT: s_wait_kmcnt 0x0106; CHECK-NEXT: v_max_i64 v[0:1], v[0:1], v[8:9]107; CHECK-NEXT: v_max_i64 v[2:3], v[2:3], v[10:11]108; CHECK-NEXT: v_max_i64 v[4:5], v[4:5], v[12:13]109; CHECK-NEXT: v_max_i64 v[6:7], v[6:7], v[14:15]110; CHECK-NEXT: s_set_pc_i64 s[30:31]111 %r = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %a, <4 x i64> %b)112 ret <4 x i64> %r113}114 115define i64 @test_abs_i64(i64 %a) {116; CHECK-LABEL: test_abs_i64:117; CHECK: ; %bb.0:118; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0119; CHECK-NEXT: s_wait_kmcnt 0x0120; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1121; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)122; CHECK-NEXT: v_mov_b32_e32 v3, v2123; CHECK-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]124; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)125; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2126; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2127; CHECK-NEXT: s_set_pc_i64 s[30:31]128 %r = call i64 @llvm.abs.i64(i64 %a, i1 0)129 ret i64 %r130}131 132define amdgpu_ps i64 @test_umin_i64_s(i64 inreg %a, i64 inreg %b) {133; CHECK-LABEL: test_umin_i64_s:134; CHECK: ; %bb.0:135; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1136; CHECK-NEXT: v_min_u64 v[0:1], s[0:1], s[2:3]137; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)138; CHECK-NEXT: v_readfirstlane_b32 s0, v0139; CHECK-NEXT: v_readfirstlane_b32 s1, v1140; CHECK-NEXT: ; return to shader part epilog141 %r = call i64 @llvm.umin.i64(i64 %a, i64 %b)142 ret i64 %r143}144 145define amdgpu_ps i64 @test_umax_i64_s(i64 inreg %a, i64 inreg %b) {146; CHECK-LABEL: test_umax_i64_s:147; CHECK: ; %bb.0:148; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1149; CHECK-NEXT: v_max_u64 v[0:1], s[0:1], s[2:3]150; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)151; CHECK-NEXT: v_readfirstlane_b32 s0, v0152; CHECK-NEXT: v_readfirstlane_b32 s1, v1153; CHECK-NEXT: ; return to shader part epilog154 %r = call i64 @llvm.umax.i64(i64 %a, i64 %b)155 ret i64 %r156}157 158define amdgpu_ps i64 @test_smin_i64_s(i64 inreg %a, i64 inreg %b) {159; CHECK-LABEL: test_smin_i64_s:160; CHECK: ; %bb.0:161; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1162; CHECK-NEXT: v_min_i64 v[0:1], s[0:1], s[2:3]163; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)164; CHECK-NEXT: v_readfirstlane_b32 s0, v0165; CHECK-NEXT: v_readfirstlane_b32 s1, v1166; CHECK-NEXT: ; return to shader part epilog167 %r = call i64 @llvm.smin.i64(i64 %a, i64 %b)168 ret i64 %r169}170 171define amdgpu_ps i64 @test_smax_i64_s(i64 inreg %a, i64 inreg %b) {172; CHECK-LABEL: test_smax_i64_s:173; CHECK: ; %bb.0:174; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1175; CHECK-NEXT: v_max_i64 v[0:1], s[0:1], s[2:3]176; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)177; CHECK-NEXT: v_readfirstlane_b32 s0, v0178; CHECK-NEXT: v_readfirstlane_b32 s1, v1179; CHECK-NEXT: ; return to shader part epilog180 %r = call i64 @llvm.smax.i64(i64 %a, i64 %b)181 ret i64 %r182}183 184define amdgpu_ps i64 @test_abs_i64_s(i64 inreg %a) {185; CHECK-LABEL: test_abs_i64_s:186; CHECK: ; %bb.0:187; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1188; CHECK-NEXT: s_ashr_i32 s2, s1, 31189; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)190; CHECK-NEXT: s_mov_b32 s3, s2191; CHECK-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]192; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)193; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]194; CHECK-NEXT: ; return to shader part epilog195 %r = call i64 @llvm.abs.i64(i64 %a, i1 0)196 ret i64 %r197}198