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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX10 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GFX11 %s4declare i32 @llvm.amdgcn.workitem.id.x()5 6; A 64-bit multiplication where no arguments were zero extended.7define amdgpu_kernel void @v_mul_i64_no_zext(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {8; GFX10-LABEL: v_mul_i64_no_zext:9; GFX10: ; %bb.0:10; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c11; GFX10-NEXT: v_lshlrev_b32_e32 v6, 3, v012; GFX10-NEXT: s_waitcnt lgkmcnt(0)13; GFX10-NEXT: s_clause 0x114; GFX10-NEXT: global_load_dwordx2 v[2:3], v6, s[0:1]15; GFX10-NEXT: global_load_dwordx2 v[4:5], v6, s[2:3]16; GFX10-NEXT: s_waitcnt vmcnt(0)17; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v2, v4, 018; GFX10-NEXT: v_mad_u64_u32 v[1:2], s0, v2, v5, v[1:2]19; GFX10-NEXT: v_mad_u64_u32 v[1:2], s0, v3, v4, v[1:2]20; GFX10-NEXT: global_store_dwordx2 v6, v[0:1], s[2:3]21; GFX10-NEXT: s_endpgm22;23; GFX11-LABEL: v_mul_i64_no_zext:24; GFX11: ; %bb.0:25; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c26; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v027; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)28; GFX11-NEXT: v_lshlrev_b32_e32 v8, 3, v029; GFX11-NEXT: s_waitcnt lgkmcnt(0)30; GFX11-NEXT: s_clause 0x131; GFX11-NEXT: global_load_b64 v[2:3], v8, s[0:1]32; GFX11-NEXT: global_load_b64 v[4:5], v8, s[2:3]33; GFX11-NEXT: s_waitcnt vmcnt(0)34; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v4, 035; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)36; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v2, v5, v[1:2]37; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v3, v4, v[6:7]38; GFX11-NEXT: global_store_b64 v8, v[0:1], s[2:3]39; GFX11-NEXT: s_endpgm40 %tid = call i32 @llvm.amdgcn.workitem.id.x()41 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid42 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid43 %gep.out = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid44 %a = load i64, ptr addrspace(1) %gep.a45 %b = load i64, ptr addrspace(1) %gep.b46 %mul = mul i64 %a, %b47 store i64 %mul, ptr addrspace(1) %gep.out48 ret void49}50 51; a 64 bit multiplication where the second argument was zero extended.52define amdgpu_kernel void @v_mul_i64_zext_src1(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {53; GFX10-LABEL: v_mul_i64_zext_src1:54; GFX10: ; %bb.0:55; GFX10-NEXT: s_clause 0x156; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2457; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3458; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v059; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v060; GFX10-NEXT: s_waitcnt lgkmcnt(0)61; GFX10-NEXT: global_load_dwordx2 v[2:3], v1, s[2:3]62; GFX10-NEXT: global_load_dword v4, v0, s[6:7]63; GFX10-NEXT: s_waitcnt vmcnt(0)64; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v2, v4, 065; GFX10-NEXT: v_mad_u64_u32 v[1:2], s2, v3, v4, v[1:2]66; GFX10-NEXT: v_mov_b32_e32 v2, 067; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]68; GFX10-NEXT: s_endpgm69;70; GFX11-LABEL: v_mul_i64_zext_src1:71; GFX11: ; %bb.0:72; GFX11-NEXT: s_clause 0x173; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2474; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x3475; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v076; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)77; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v078; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v079; GFX11-NEXT: s_waitcnt lgkmcnt(0)80; GFX11-NEXT: global_load_b64 v[2:3], v1, s[2:3]81; GFX11-NEXT: global_load_b32 v6, v0, s[4:5]82; GFX11-NEXT: s_waitcnt vmcnt(0)83; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v6, 084; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)85; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v3, v6, v[1:2]86; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v487; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]88; GFX11-NEXT: s_endpgm89 %tid = call i32 @llvm.amdgcn.workitem.id.x()90 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid91 %gep.b = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid92 %a = load i64, ptr addrspace(1) %gep.a93 %b = load i32, ptr addrspace(1) %gep.b94 %b_ext = zext i32 %b to i6495 %mul = mul i64 %a, %b_ext96 store i64 %mul, ptr addrspace(1) %out97 ret void98}99 100; 64 bit multiplication where the first argument was zero extended.101define amdgpu_kernel void @v_mul_i64_zext_src0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {102; GFX10-LABEL: v_mul_i64_zext_src0:103; GFX10: ; %bb.0:104; GFX10-NEXT: s_clause 0x1105; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24106; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34107; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v0108; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0109; GFX10-NEXT: s_waitcnt lgkmcnt(0)110; GFX10-NEXT: global_load_dword v4, v1, s[2:3]111; GFX10-NEXT: global_load_dwordx2 v[2:3], v0, s[6:7]112; GFX10-NEXT: s_waitcnt vmcnt(0)113; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v4, v2, 0114; GFX10-NEXT: v_mad_u64_u32 v[1:2], s2, v4, v3, v[1:2]115; GFX10-NEXT: v_mov_b32_e32 v2, 0116; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]117; GFX10-NEXT: s_endpgm118;119; GFX11-LABEL: v_mul_i64_zext_src0:120; GFX11: ; %bb.0:121; GFX11-NEXT: s_clause 0x1122; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24123; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34124; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0125; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)126; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v0127; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0128; GFX11-NEXT: s_waitcnt lgkmcnt(0)129; GFX11-NEXT: global_load_b32 v6, v1, s[2:3]130; GFX11-NEXT: global_load_b64 v[2:3], v0, s[4:5]131; GFX11-NEXT: s_waitcnt vmcnt(0)132; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v6, v2, 0133; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)134; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v6, v3, v[1:2]135; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v4136; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]137; GFX11-NEXT: s_endpgm138 %tid = call i32 @llvm.amdgcn.workitem.id.x()139 %gep.a = getelementptr inbounds i32, ptr addrspace(1) %aptr, i32 %tid140 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid141 %a = load i32, ptr addrspace(1) %gep.a142 %b = load i64, ptr addrspace(1) %gep.b143 %a_ext = zext i32 %a to i64144 %mul = mul i64 %a_ext, %b145 store i64 %mul, ptr addrspace(1) %out146 ret void147}148 149; 64-bit multiplication where both arguments were zero extended.150define amdgpu_kernel void @v_mul_i64_zext_src0_src1(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {151; GFX10-LABEL: v_mul_i64_zext_src0_src1:152; GFX10: ; %bb.0:153; GFX10-NEXT: s_clause 0x1154; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24155; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34156; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0157; GFX10-NEXT: s_waitcnt lgkmcnt(0)158; GFX10-NEXT: s_clause 0x1159; GFX10-NEXT: global_load_dword v2, v0, s[2:3]160; GFX10-NEXT: global_load_dword v3, v0, s[6:7]161; GFX10-NEXT: s_waitcnt vmcnt(0)162; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v2, v3, 0163; GFX10-NEXT: v_mov_b32_e32 v2, 0164; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]165; GFX10-NEXT: s_endpgm166;167; GFX11-LABEL: v_mul_i64_zext_src0_src1:168; GFX11: ; %bb.0:169; GFX11-NEXT: s_clause 0x1170; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24171; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34172; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0173; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)174; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0175; GFX11-NEXT: s_waitcnt lgkmcnt(0)176; GFX11-NEXT: s_clause 0x1177; GFX11-NEXT: global_load_b32 v2, v0, s[2:3]178; GFX11-NEXT: global_load_b32 v3, v0, s[4:5]179; GFX11-NEXT: s_waitcnt vmcnt(0)180; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v3, 0181; GFX11-NEXT: v_mov_b32_e32 v2, 0182; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]183; GFX11-NEXT: s_endpgm184 %tid = call i32 @llvm.amdgcn.workitem.id.x()185 %gep.a = getelementptr inbounds i32, ptr addrspace(1) %aptr, i32 %tid186 %gep.b = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid187 %a = load i32, ptr addrspace(1) %gep.a188 %b = load i32, ptr addrspace(1) %gep.b189 %a_ext = zext i32 %a to i64190 %b_ext = zext i32 %b to i64191 %mul = mul i64 %a_ext, %b_ext192 store i64 %mul, ptr addrspace(1) %out193 ret void194}195 196; 64-bit multiplication where the upper bytes of the first argument were masked.197define amdgpu_kernel void @v_mul_i64_masked_src0_hi(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {198; GFX10-LABEL: v_mul_i64_masked_src0_hi:199; GFX10: ; %bb.0:200; GFX10-NEXT: s_clause 0x1201; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24202; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34203; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0204; GFX10-NEXT: s_waitcnt lgkmcnt(0)205; GFX10-NEXT: s_clause 0x1206; GFX10-NEXT: global_load_dword v4, v0, s[2:3]207; GFX10-NEXT: global_load_dwordx2 v[2:3], v0, s[6:7]208; GFX10-NEXT: s_waitcnt vmcnt(0)209; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v4, v2, 0210; GFX10-NEXT: v_mad_u64_u32 v[1:2], s2, v4, v3, v[1:2]211; GFX10-NEXT: v_mov_b32_e32 v2, 0212; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]213; GFX10-NEXT: s_endpgm214;215; GFX11-LABEL: v_mul_i64_masked_src0_hi:216; GFX11: ; %bb.0:217; GFX11-NEXT: s_clause 0x1218; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24219; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34220; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0221; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)222; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0223; GFX11-NEXT: s_waitcnt lgkmcnt(0)224; GFX11-NEXT: s_clause 0x1225; GFX11-NEXT: global_load_b32 v6, v0, s[2:3]226; GFX11-NEXT: global_load_b64 v[2:3], v0, s[4:5]227; GFX11-NEXT: s_waitcnt vmcnt(0)228; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v6, v2, 0229; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)230; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v6, v3, v[1:2]231; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v4232; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]233; GFX11-NEXT: s_endpgm234 %tid = call i32 @llvm.amdgcn.workitem.id.x()235 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid236 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid237 %a = load i64, ptr addrspace(1) %gep.a238 %b = load i64, ptr addrspace(1) %gep.b239 %a_and = and i64 %a, u0x00000000FFFFFFFF240 %mul = mul i64 %a_and, %b241 store i64 %mul, ptr addrspace(1) %out242 ret void243}244 245; 64-bit multiplication where lower bytes of first argument were masked.246define amdgpu_kernel void @v_mul_i64_masked_src0_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {247; GFX10-LABEL: v_mul_i64_masked_src0_lo:248; GFX10: ; %bb.0:249; GFX10-NEXT: s_clause 0x1250; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24251; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34252; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0253; GFX10-NEXT: s_waitcnt lgkmcnt(0)254; GFX10-NEXT: s_clause 0x1255; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]256; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7]257; GFX10-NEXT: s_waitcnt vmcnt(1)258; GFX10-NEXT: v_mov_b32_e32 v0, 0259; GFX10-NEXT: s_waitcnt vmcnt(0)260; GFX10-NEXT: v_mul_lo_u32 v1, v1, v2261; GFX10-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]262; GFX10-NEXT: s_endpgm263;264; GFX11-LABEL: v_mul_i64_masked_src0_lo:265; GFX11: ; %bb.0:266; GFX11-NEXT: s_clause 0x1267; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24268; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34269; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0270; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)271; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0272; GFX11-NEXT: s_waitcnt lgkmcnt(0)273; GFX11-NEXT: s_clause 0x1274; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]275; GFX11-NEXT: global_load_b64 v[2:3], v2, s[4:5]276; GFX11-NEXT: s_waitcnt vmcnt(1)277; GFX11-NEXT: v_mov_b32_e32 v0, 0278; GFX11-NEXT: s_waitcnt vmcnt(0)279; GFX11-NEXT: v_mul_lo_u32 v1, v1, v2280; GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1]281; GFX11-NEXT: s_endpgm282 %tid = call i32 @llvm.amdgcn.workitem.id.x()283 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid284 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid285 %a = load i64, ptr addrspace(1) %gep.a286 %b = load i64, ptr addrspace(1) %gep.b287 %a_and = and i64 %a, u0xFFFFFFFF00000000288 %mul = mul i64 %a_and, %b289 store i64 %mul, ptr addrspace(1) %out290 ret void291}292 293; 64-bit multiplication where the lower bytes of the second argument were masked.294define amdgpu_kernel void @v_mul_i64_masked_src1_lo(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {295; GFX10-LABEL: v_mul_i64_masked_src1_lo:296; GFX10: ; %bb.0:297; GFX10-NEXT: s_clause 0x1298; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24299; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34300; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v0301; GFX10-NEXT: ; kill: killed $vgpr3302; GFX10-NEXT: ; kill: killed $sgpr2_sgpr3303; GFX10-NEXT: s_waitcnt lgkmcnt(0)304; GFX10-NEXT: s_clause 0x1305; GFX10-NEXT: global_load_dwordx2 v[0:1], v3, s[2:3]306; GFX10-NEXT: global_load_dwordx2 v[1:2], v3, s[6:7]307; GFX10-NEXT: ; kill: killed $sgpr6_sgpr7308; GFX10-NEXT: s_waitcnt vmcnt(0)309; GFX10-NEXT: v_mul_lo_u32 v1, v0, v2310; GFX10-NEXT: v_mov_b32_e32 v0, 0311; GFX10-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]312; GFX10-NEXT: s_endpgm313;314; GFX11-LABEL: v_mul_i64_masked_src1_lo:315; GFX11: ; %bb.0:316; GFX11-NEXT: s_clause 0x1317; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24318; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34319; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0320; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)321; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0322; GFX11-NEXT: s_waitcnt lgkmcnt(0)323; GFX11-NEXT: s_clause 0x1324; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]325; GFX11-NEXT: global_load_b64 v[1:2], v2, s[4:5]326; GFX11-NEXT: s_waitcnt vmcnt(0)327; GFX11-NEXT: v_mul_lo_u32 v1, v0, v2328; GFX11-NEXT: v_mov_b32_e32 v0, 0329; GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1]330; GFX11-NEXT: s_endpgm331 %tid = call i32 @llvm.amdgcn.workitem.id.x()332 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid333 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid334 %a = load i64, ptr addrspace(1) %gep.a335 %b = load i64, ptr addrspace(1) %gep.b336 %b_and = and i64 %b, u0xFFFFFFFF00000000337 %mul = mul i64 %a, %b_and338 store i64 %mul, ptr addrspace(1) %out339 ret void340}341 342; 64-bit multiplication where the entire first argument is masked.343define amdgpu_kernel void @v_mul_i64_masked_src0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {344; GFX10-LABEL: v_mul_i64_masked_src0:345; GFX10: ; %bb.0:346; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24347; GFX10-NEXT: v_mov_b32_e32 v0, 0348; GFX10-NEXT: v_mov_b32_e32 v1, 0349; GFX10-NEXT: v_mov_b32_e32 v2, 0350; GFX10-NEXT: s_waitcnt lgkmcnt(0)351; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]352; GFX10-NEXT: s_endpgm353;354; GFX11-LABEL: v_mul_i64_masked_src0:355; GFX11: ; %bb.0:356; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24357; GFX11-NEXT: v_mov_b32_e32 v0, 0358; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0359; GFX11-NEXT: s_waitcnt lgkmcnt(0)360; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]361; GFX11-NEXT: s_endpgm362 %tid = call i32 @llvm.amdgcn.workitem.id.x()363 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid364 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid365 %a = load i64, ptr addrspace(1) %gep.a366 %b = load i64, ptr addrspace(1) %gep.b367 %a_and = and i64 %a, u0x0000000000000000368 %mul = mul i64 %a_and, %b369 store i64 %mul, ptr addrspace(1) %out370 ret void371}372 373; 64-bit multiplication where the parts of the high and low bytes of the first argument are masked.374define amdgpu_kernel void @v_mul_i64_partially_masked_src0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {375; GFX10-LABEL: v_mul_i64_partially_masked_src0:376; GFX10: ; %bb.0:377; GFX10-NEXT: s_clause 0x1378; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24379; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34380; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0381; GFX10-NEXT: s_waitcnt lgkmcnt(0)382; GFX10-NEXT: s_clause 0x1383; GFX10-NEXT: global_load_dwordx2 v[1:2], v0, s[2:3]384; GFX10-NEXT: global_load_dwordx2 v[3:4], v0, s[6:7]385; GFX10-NEXT: s_waitcnt vmcnt(1)386; GFX10-NEXT: v_and_b32_e32 v5, 0xfff00000, v1387; GFX10-NEXT: s_waitcnt vmcnt(0)388; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v5, v3, 0389; GFX10-NEXT: v_mad_u64_u32 v[4:5], s2, v5, v4, v[1:2]390; GFX10-NEXT: v_and_b32_e32 v1, 0xf00f, v2391; GFX10-NEXT: v_mad_u64_u32 v[1:2], s2, v1, v3, v[4:5]392; GFX10-NEXT: v_mov_b32_e32 v2, 0393; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]394; GFX10-NEXT: s_endpgm395;396; GFX11-LABEL: v_mul_i64_partially_masked_src0:397; GFX11: ; %bb.0:398; GFX11-NEXT: s_clause 0x1399; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24400; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34401; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0402; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)403; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0404; GFX11-NEXT: s_waitcnt lgkmcnt(0)405; GFX11-NEXT: s_clause 0x1406; GFX11-NEXT: global_load_b64 v[1:2], v0, s[2:3]407; GFX11-NEXT: global_load_b64 v[3:4], v0, s[4:5]408; GFX11-NEXT: s_waitcnt vmcnt(1)409; GFX11-NEXT: v_and_b32_e32 v7, 0xfff00000, v1410; GFX11-NEXT: s_waitcnt vmcnt(0)411; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)412; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v7, v3, 0413; GFX11-NEXT: v_mad_u64_u32 v[5:6], null, v7, v4, v[1:2]414; GFX11-NEXT: v_and_b32_e32 v4, 0xf00f, v2415; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)416; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v4, v3, v[5:6]417; GFX11-NEXT: v_mov_b32_e32 v2, 0418; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]419; GFX11-NEXT: s_endpgm420 %tid = call i32 @llvm.amdgcn.workitem.id.x()421 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid422 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid423 %a = load i64, ptr addrspace(1) %gep.a424 %b = load i64, ptr addrspace(1) %gep.b425 %a_and = and i64 %a, u0x0000F00FFFF00000426 %mul = mul i64 %a_and, %b427 store i64 %mul, ptr addrspace(1) %out428 ret void429}430 431; 64-bit multiplication, where the first argument is masked before a branch432define amdgpu_kernel void @v_mul64_masked_before_branch(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {433; GFX10-LABEL: v_mul64_masked_before_branch:434; GFX10: ; %bb.0: ; %entry435; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24436; GFX10-NEXT: v_mov_b32_e32 v0, 0437; GFX10-NEXT: v_mov_b32_e32 v1, 0438; GFX10-NEXT: v_mov_b32_e32 v2, 0439; GFX10-NEXT: s_waitcnt lgkmcnt(0)440; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]441; GFX10-NEXT: s_endpgm442;443; GFX11-LABEL: v_mul64_masked_before_branch:444; GFX11: ; %bb.0: ; %entry445; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24446; GFX11-NEXT: v_mov_b32_e32 v0, 0447; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0448; GFX11-NEXT: s_waitcnt lgkmcnt(0)449; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]450; GFX11-NEXT: s_endpgm451entry:452 %tid = call i32 @llvm.amdgcn.workitem.id.x()453 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid454 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid455 %a = load i64, ptr addrspace(1) %gep.a456 %b = load i64, ptr addrspace(1) %gep.b457 %a_and = and i64 %a, u0x0000000000000000458 %0 = icmp eq i64 %b, 0459 br i1 %0, label %if, label %else460 461if:462 %b_and = and i64 %b, u0xFFFFFFFF00000000463 %1 = mul i64 %a_and, %b_and464 br label %endif465 466else:467 %2 = mul i64 %a_and, %b468 br label %endif469 470endif:471 %3 = phi i64 [%1, %if], [%2, %else]472 store i64 %3, ptr addrspace(1) %out473 ret void474}475 476; 64-bit multiplication with both arguments changed in different basic blocks.477define amdgpu_kernel void @v_mul64_masked_before_and_in_branch(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {478; GFX10-LABEL: v_mul64_masked_before_and_in_branch:479; GFX10: ; %bb.0: ; %entry480; GFX10-NEXT: s_clause 0x1481; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24482; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34483; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0484; GFX10-NEXT: s_waitcnt lgkmcnt(0)485; GFX10-NEXT: s_clause 0x1486; GFX10-NEXT: global_load_dwordx2 v[2:3], v0, s[2:3]487; GFX10-NEXT: global_load_dwordx2 v[4:5], v0, s[6:7]488; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1489; GFX10-NEXT: s_waitcnt vmcnt(1)490; GFX10-NEXT: v_cmp_ge_u64_e32 vcc_lo, 0, v[2:3]491; GFX10-NEXT: s_and_saveexec_b32 s2, vcc_lo492; GFX10-NEXT: s_xor_b32 s2, exec_lo, s2493; GFX10-NEXT: s_cbranch_execz .LBB10_2494; GFX10-NEXT: ; %bb.1: ; %else495; GFX10-NEXT: s_waitcnt vmcnt(0)496; GFX10-NEXT: v_mad_u64_u32 v[0:1], s3, v2, v4, 0497; GFX10-NEXT: v_mad_u64_u32 v[1:2], s3, v2, v5, v[1:2]498; GFX10-NEXT: ; implicit-def: $vgpr2_vgpr3499; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5500; GFX10-NEXT: .LBB10_2: ; %Flow501; GFX10-NEXT: s_andn2_saveexec_b32 s2, s2502; GFX10-NEXT: s_cbranch_execz .LBB10_4503; GFX10-NEXT: ; %bb.3: ; %if504; GFX10-NEXT: s_waitcnt vmcnt(0)505; GFX10-NEXT: v_mul_lo_u32 v1, v2, v5506; GFX10-NEXT: v_mov_b32_e32 v0, 0507; GFX10-NEXT: .LBB10_4: ; %endif508; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2509; GFX10-NEXT: v_mov_b32_e32 v2, 0510; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]511; GFX10-NEXT: s_endpgm512;513; GFX11-LABEL: v_mul64_masked_before_and_in_branch:514; GFX11: ; %bb.0: ; %entry515; GFX11-NEXT: s_clause 0x1516; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24517; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34518; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0519; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)520; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0521; GFX11-NEXT: s_waitcnt lgkmcnt(0)522; GFX11-NEXT: s_clause 0x1523; GFX11-NEXT: global_load_b64 v[2:3], v0, s[2:3]524; GFX11-NEXT: global_load_b64 v[4:5], v0, s[4:5]525; GFX11-NEXT: s_mov_b32 s2, exec_lo526; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1527; GFX11-NEXT: s_waitcnt vmcnt(1)528; GFX11-NEXT: v_cmpx_ge_u64_e32 0, v[2:3]529; GFX11-NEXT: s_xor_b32 s2, exec_lo, s2530; GFX11-NEXT: s_cbranch_execz .LBB10_2531; GFX11-NEXT: ; %bb.1: ; %else532; GFX11-NEXT: s_waitcnt vmcnt(0)533; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v4, 0534; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)535; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v2, v5, v[1:2]536; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5537; GFX11-NEXT: v_mov_b32_e32 v1, v3538; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3539; GFX11-NEXT: .LBB10_2: ; %Flow540; GFX11-NEXT: s_and_not1_saveexec_b32 s2, s2541; GFX11-NEXT: s_cbranch_execz .LBB10_4542; GFX11-NEXT: ; %bb.3: ; %if543; GFX11-NEXT: s_waitcnt vmcnt(0)544; GFX11-NEXT: v_mul_lo_u32 v1, v2, v5545; GFX11-NEXT: v_mov_b32_e32 v0, 0546; GFX11-NEXT: .LBB10_4: ; %endif547; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s2548; GFX11-NEXT: v_mov_b32_e32 v2, 0549; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]550; GFX11-NEXT: s_endpgm551entry:552 %tid = call i32 @llvm.amdgcn.workitem.id.x()553 %gep.a = getelementptr inbounds i64, ptr addrspace(1) %aptr, i32 %tid554 %gep.b = getelementptr inbounds i64, ptr addrspace(1) %bptr, i32 %tid555 %a = load i64, ptr addrspace(1) %gep.a556 %b = load i64, ptr addrspace(1) %gep.b557 %a_and = and i64 %a, u0x00000000FFFFFFFF558 %0 = icmp ugt i64 %a, 0559 br i1 %0, label %if, label %else560 561if:562 %b_and = and i64 %b, u0xFFFFFFFF00000000563 %1 = mul i64 %a_and, %b_and564 br label %endif565 566else:567 %2 = mul i64 %a_and, %b568 br label %endif569 570endif:571 %3 = phi i64 [%1, %if], [%2, %else]572 store i64 %3, ptr addrspace(1) %out573 ret void574}575 576 577