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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -global-isel=1 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s3 4---5name: v_mul_i64_no_zext6body: |7 bb.0:8 liveins: $vgpr0_vgpr1, $vgpr2_vgpr39 10 ; GFX10-LABEL: name: v_mul_i64_no_zext11 ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr312 ; GFX10-NEXT: {{ $}}13 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr114 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr315 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)16 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)17 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 018 ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]]19 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)20 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]21 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]22 ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]23 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]]24 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32)25 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)26 %0:_(s64) = COPY $vgpr0_vgpr127 %1:_(s64) = COPY $vgpr2_vgpr328 %2:_(s64) = G_MUL %0, %129 $vgpr0_vgpr1 = COPY %230 31...32---33name: v_mul_i64_zext_src134body: |35 bb.0:36 liveins: $vgpr0_vgpr1, $vgpr237 38 ; GFX10-LABEL: name: v_mul_i64_zext_src139 ; GFX10: liveins: $vgpr0_vgpr1, $vgpr240 ; GFX10-NEXT: {{ $}}41 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr142 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr243 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)44 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 045 ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[COPY1]], [[C]]46 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)47 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[COPY1]]48 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]49 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)50 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)51 %0:_(s64) = COPY $vgpr0_vgpr152 %1:_(s32) = COPY $vgpr253 %2:_(s64) = G_ZEXT %1(s32)54 %3:_(s64) = G_MUL %0, %255 $vgpr0_vgpr1 = COPY %356 57...58---59name: v_mul_i64_zext_src060body: |61 bb.0:62 liveins: $vgpr0, $vgpr2_vgpr363 64 ; GFX10-LABEL: name: v_mul_i64_zext_src065 ; GFX10: liveins: $vgpr0, $vgpr2_vgpr366 ; GFX10-NEXT: {{ $}}67 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr068 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr369 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)70 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 071 ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[COPY]](s32), [[UV2]], [[C]]72 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)73 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[UV3]]74 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]75 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)76 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)77 %0:_(s32) = COPY $vgpr078 %1:_(s64) = COPY $vgpr2_vgpr379 %2:_(s64) = G_ZEXT %0(s32)80 %3:_(s64) = G_MUL %2, %181 $vgpr0_vgpr1 = COPY %382 83...84---85name: v_mul_i64_zext_src0_src186body: |87 bb.0:88 liveins: $vgpr0, $vgpr189 90 ; GFX10-LABEL: name: v_mul_i64_zext_src0_src191 ; GFX10: liveins: $vgpr0, $vgpr192 ; GFX10-NEXT: {{ $}}93 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr194 ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)95 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)96 %0:_(s32) = COPY $vgpr097 %1:_(s32) = COPY $vgpr198 %2:_(s64) = G_ZEXT %0(s32)99 %3:_(s64) = G_ZEXT %1(s32)100 %4:_(s64) = G_MUL %2, %3101 $vgpr0_vgpr1 = COPY %3102 103...104---105name: v_mul_i64_masked_src0_hi106body: |107 bb.0:108 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3109 110 ; GFX10-LABEL: name: v_mul_i64_masked_src0_hi111 ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3112 ; GFX10-NEXT: {{ $}}113 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1114 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3115 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295116 ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]117 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)118 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)119 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0120 ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C1]]121 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)122 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]123 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]124 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)125 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)126 %0:_(s64) = COPY $vgpr0_vgpr1127 %1:_(s64) = COPY $vgpr2_vgpr3128 %2:_(s64) = G_CONSTANT i64 4294967295129 %3:_(s64) = G_AND %0, %2130 %4:_(s64) = G_MUL %3, %1131 $vgpr0_vgpr1 = COPY %4132...133---134name: v_mul_i64_masked_src0_lo135body: |136 bb.0:137 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3138 139 ; GFX10-LABEL: name: v_mul_i64_masked_src0_lo140 ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3141 ; GFX10-NEXT: {{ $}}142 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1143 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3144 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296145 ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]146 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)147 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)148 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0149 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)150 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]151 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[MUL]](s32)152 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)153 %0:_(s64) = COPY $vgpr0_vgpr1154 %1:_(s64) = COPY $vgpr2_vgpr3155 %2:_(s64) = G_CONSTANT i64 -4294967296156 %3:_(s64) = G_AND %0, %2157 %4:_(s64) = G_MUL %3, %1158 $vgpr0_vgpr1 = COPY %4159 160...161---162name: v_mul_i64_masked_src1_lo163body: |164 bb.0:165 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3166 167 ; GFX10-LABEL: name: v_mul_i64_masked_src1_lo168 ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3169 ; GFX10-NEXT: {{ $}}170 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1171 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3172 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296173 ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]174 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)175 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)176 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0177 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)178 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]179 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[MUL]](s32)180 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)181 %0:_(s64) = COPY $vgpr0_vgpr1182 %1:_(s64) = COPY $vgpr2_vgpr3183 %2:_(s64) = G_CONSTANT i64 -4294967296184 %3:_(s64) = G_AND %1, %2185 %4:_(s64) = G_MUL %0, %3186 $vgpr0_vgpr1 = COPY %4187 188...189---190name: v_mul_i64_masked_src0191body: |192 bb.0:193 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3194 195 ; GFX10-LABEL: name: v_mul_i64_masked_src0196 ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3197 ; GFX10-NEXT: {{ $}}198 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0199 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[C]](s64)200 %0:_(s64) = COPY $vgpr0_vgpr1201 %1:_(s64) = COPY $vgpr2_vgpr3202 %2:_(s64) = G_CONSTANT i64 0203 %3:_(s64) = G_AND %0, %2204 %4:_(s64) = G_MUL %3, %1205 $vgpr0_vgpr1 = COPY %4206...207---208name: v_mul_i64_partially_masked_src0209body: |210 bb.0:211 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3212 213 ; GFX10-LABEL: name: v_mul_i64_partially_masked_src0214 ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3215 ; GFX10-NEXT: {{ $}}216 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1217 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3218 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 263951509094400219 ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]220 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)221 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)222 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0223 ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C1]]224 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)225 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]226 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]227 ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]228 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]]229 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32)230 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)231 %0:_(s64) = COPY $vgpr0_vgpr1232 %1:_(s64) = COPY $vgpr2_vgpr3233 %2:_(s64) = G_CONSTANT i64 263951509094400234 %3:_(s64) = G_AND %0, %2235 %4:_(s64) = G_MUL %3, %1236 $vgpr0_vgpr1 = COPY %4237...238---239name: v_mul_i64_constant_hi240body: |241 bb.0:242 liveins: $vgpr0_vgpr1243 244 ; GFX10-LABEL: name: v_mul_i64_constant_hi245 ; GFX10: liveins: $vgpr0_vgpr1246 ; GFX10-NEXT: {{ $}}247 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1248 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296249 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)250 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)251 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0252 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)253 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]254 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[MUL]](s32)255 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)256 %0:_(s64) = COPY $vgpr0_vgpr1257 %1:_(s64) = G_CONSTANT i64 -4294967296258 %2:_(s64) = G_MUL %0, %1259 $vgpr0_vgpr1 = COPY %2260...261---262name: v_mul_i64_constant_lo263body: |264 bb.0:265 liveins: $vgpr0_vgpr1266 267 ; GFX10-LABEL: name: v_mul_i64_constant_lo268 ; GFX10: liveins: $vgpr0_vgpr1269 ; GFX10-NEXT: {{ $}}270 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1271 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295272 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)273 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)274 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0275 ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C1]]276 ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)277 ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]278 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]279 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)280 ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)281 %0:_(s64) = COPY $vgpr0_vgpr1282 %1:_(s64) = G_CONSTANT i64 4294967295283 %2:_(s64) = G_MUL %0, %1284 $vgpr0_vgpr1 = COPY %2285...286