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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16, -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s7; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16, -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s8; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12 %s9; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250 %s10 11define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) {12; GCN-LABEL: s_mul_i16:13; GCN: ; %bb.0:14; GCN-NEXT: s_mul_i32 s0, s0, s115; GCN-NEXT: ; return to shader part epilog16;17; GFX10PLUS-LABEL: s_mul_i16:18; GFX10PLUS: ; %bb.0:19; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s120; GFX10PLUS-NEXT: ; return to shader part epilog21;22; GFX12-LABEL: s_mul_i16:23; GFX12: ; %bb.0:24; GFX12-NEXT: s_mul_i32 s0, s0, s125; GFX12-NEXT: ; return to shader part epilog26;27; GFX1250-LABEL: s_mul_i16:28; GFX1250: ; %bb.0:29; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 130; GFX1250-NEXT: s_mul_i32 s0, s0, s131; GFX1250-NEXT: ; return to shader part epilog32 %result = mul i16 %num, %den33 ret i16 %result34}35 36define i16 @v_mul_i16(i16 %num, i16 %den) {37; GFX7-LABEL: v_mul_i16:38; GFX7: ; %bb.0:39; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v041; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v142; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v143; GFX7-NEXT: s_setpc_b64 s[30:31]44;45; GFX8-LABEL: v_mul_i16:46; GFX8: ; %bb.0:47; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v149; GFX8-NEXT: s_setpc_b64 s[30:31]50;51; GFX9-LABEL: v_mul_i16:52; GFX9: ; %bb.0:53; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)54; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v155; GFX9-NEXT: s_setpc_b64 s[30:31]56;57; GFX10-LABEL: v_mul_i16:58; GFX10: ; %bb.0:59; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)60; GFX10-NEXT: v_mul_lo_u16 v0, v0, v161; GFX10-NEXT: s_setpc_b64 s[30:31]62;63; GFX11-TRUE16-LABEL: v_mul_i16:64; GFX11-TRUE16: ; %bb.0:65; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)66; GFX11-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l67; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]68;69; GFX11-FAKE16-LABEL: v_mul_i16:70; GFX11-FAKE16: ; %bb.0:71; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GFX11-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v173; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]74;75; GFX12-LABEL: v_mul_i16:76; GFX12: ; %bb.0:77; GFX12-NEXT: s_wait_loadcnt_dscnt 0x078; GFX12-NEXT: s_wait_expcnt 0x079; GFX12-NEXT: s_wait_samplecnt 0x080; GFX12-NEXT: s_wait_bvhcnt 0x081; GFX12-NEXT: s_wait_kmcnt 0x082; GFX12-NEXT: v_mul_lo_u16 v0, v0, v183; GFX12-NEXT: s_setpc_b64 s[30:31]84;85; GFX1250-LABEL: v_mul_i16:86; GFX1250: ; %bb.0:87; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x088; GFX1250-NEXT: s_wait_kmcnt 0x089; GFX1250-NEXT: v_mul_lo_u16 v0, v0, v190; GFX1250-NEXT: s_set_pc_i64 s[30:31]91 %result = mul i16 %num, %den92 ret i16 %result93}94 95define amdgpu_ps zeroext i16 @s_mul_i16_zeroext(i16 inreg zeroext %num, i16 inreg zeroext %den) {96; GFX7-LABEL: s_mul_i16_zeroext:97; GFX7: ; %bb.0:98; GFX7-NEXT: s_mul_i32 s0, s0, s199; GFX7-NEXT: s_and_b32 s0, s0, 0xffff100; GFX7-NEXT: ; return to shader part epilog101;102; GFX8-LABEL: s_mul_i16_zeroext:103; GFX8: ; %bb.0:104; GFX8-NEXT: s_mul_i32 s0, s0, s1105; GFX8-NEXT: s_and_b32 s0, 0xffff, s0106; GFX8-NEXT: ; return to shader part epilog107;108; GFX9-LABEL: s_mul_i16_zeroext:109; GFX9: ; %bb.0:110; GFX9-NEXT: s_mul_i32 s0, s0, s1111; GFX9-NEXT: s_and_b32 s0, 0xffff, s0112; GFX9-NEXT: ; return to shader part epilog113;114; GFX10PLUS-LABEL: s_mul_i16_zeroext:115; GFX10PLUS: ; %bb.0:116; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1117; GFX10PLUS-NEXT: s_and_b32 s0, 0xffff, s0118; GFX10PLUS-NEXT: ; return to shader part epilog119;120; GFX12-LABEL: s_mul_i16_zeroext:121; GFX12: ; %bb.0:122; GFX12-NEXT: s_mul_i32 s0, s0, s1123; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)124; GFX12-NEXT: s_and_b32 s0, 0xffff, s0125; GFX12-NEXT: ; return to shader part epilog126;127; GFX1250-LABEL: s_mul_i16_zeroext:128; GFX1250: ; %bb.0:129; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1130; GFX1250-NEXT: s_mul_i32 s0, s0, s1131; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)132; GFX1250-NEXT: s_and_b32 s0, 0xffff, s0133; GFX1250-NEXT: ; return to shader part epilog134 %result = mul i16 %num, %den135 ret i16 %result136}137 138define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) {139; GFX7-LABEL: v_mul_i16_zeroext:140; GFX7: ; %bb.0:141; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1143; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0144; GFX7-NEXT: s_setpc_b64 s[30:31]145;146; GFX8-LABEL: v_mul_i16_zeroext:147; GFX8: ; %bb.0:148; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1150; GFX8-NEXT: s_setpc_b64 s[30:31]151;152; GFX9-LABEL: v_mul_i16_zeroext:153; GFX9: ; %bb.0:154; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)155; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1156; GFX9-NEXT: s_setpc_b64 s[30:31]157;158; GFX10-LABEL: v_mul_i16_zeroext:159; GFX10: ; %bb.0:160; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)161; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1162; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0163; GFX10-NEXT: s_setpc_b64 s[30:31]164;165; GFX11-TRUE16-LABEL: v_mul_i16_zeroext:166; GFX11-TRUE16: ; %bb.0:167; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)168; GFX11-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l169; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0170; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]171;172; GFX11-FAKE16-LABEL: v_mul_i16_zeroext:173; GFX11-FAKE16: ; %bb.0:174; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; GFX11-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1176; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0177; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]178;179; GFX12-LABEL: v_mul_i16_zeroext:180; GFX12: ; %bb.0:181; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0182; GFX12-NEXT: s_wait_expcnt 0x0183; GFX12-NEXT: s_wait_samplecnt 0x0184; GFX12-NEXT: s_wait_bvhcnt 0x0185; GFX12-NEXT: s_wait_kmcnt 0x0186; GFX12-NEXT: v_mul_lo_u16 v0, v0, v1187; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)188; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0189; GFX12-NEXT: s_setpc_b64 s[30:31]190;191; GFX1250-LABEL: v_mul_i16_zeroext:192; GFX1250: ; %bb.0:193; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0194; GFX1250-NEXT: s_wait_kmcnt 0x0195; GFX1250-NEXT: v_mul_lo_u16 v0, v0, v1196; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)197; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v0198; GFX1250-NEXT: s_set_pc_i64 s[30:31]199 %result = mul i16 %num, %den200 ret i16 %result201}202 203define amdgpu_ps signext i16 @s_mul_i16_signext(i16 inreg signext %num, i16 inreg signext %den) {204; GCN-LABEL: s_mul_i16_signext:205; GCN: ; %bb.0:206; GCN-NEXT: s_mul_i32 s0, s0, s1207; GCN-NEXT: s_sext_i32_i16 s0, s0208; GCN-NEXT: ; return to shader part epilog209;210; GFX10PLUS-LABEL: s_mul_i16_signext:211; GFX10PLUS: ; %bb.0:212; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1213; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0214; GFX10PLUS-NEXT: ; return to shader part epilog215;216; GFX12-LABEL: s_mul_i16_signext:217; GFX12: ; %bb.0:218; GFX12-NEXT: s_mul_i32 s0, s0, s1219; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)220; GFX12-NEXT: s_sext_i32_i16 s0, s0221; GFX12-NEXT: ; return to shader part epilog222;223; GFX1250-LABEL: s_mul_i16_signext:224; GFX1250: ; %bb.0:225; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1226; GFX1250-NEXT: s_mul_i32 s0, s0, s1227; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)228; GFX1250-NEXT: s_sext_i32_i16 s0, s0229; GFX1250-NEXT: ; return to shader part epilog230 %result = mul i16 %num, %den231 ret i16 %result232}233 234define signext i16 @v_mul_i16_signext(i16 signext %num, i16 signext %den) {235; GFX7-LABEL: v_mul_i16_signext:236; GFX7: ; %bb.0:237; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)238; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0239; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1240; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1241; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 16242; GFX7-NEXT: s_setpc_b64 s[30:31]243;244; GFX8-LABEL: v_mul_i16_signext:245; GFX8: ; %bb.0:246; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)247; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1248; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 16249; GFX8-NEXT: s_setpc_b64 s[30:31]250;251; GFX9-LABEL: v_mul_i16_signext:252; GFX9: ; %bb.0:253; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)254; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1255; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16256; GFX9-NEXT: s_setpc_b64 s[30:31]257;258; GFX10-LABEL: v_mul_i16_signext:259; GFX10: ; %bb.0:260; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)261; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1262; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16263; GFX10-NEXT: s_setpc_b64 s[30:31]264;265; GFX11-TRUE16-LABEL: v_mul_i16_signext:266; GFX11-TRUE16: ; %bb.0:267; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)268; GFX11-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l269; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16270; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]271;272; GFX11-FAKE16-LABEL: v_mul_i16_signext:273; GFX11-FAKE16: ; %bb.0:274; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)275; GFX11-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1276; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16277; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]278;279; GFX12-LABEL: v_mul_i16_signext:280; GFX12: ; %bb.0:281; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0282; GFX12-NEXT: s_wait_expcnt 0x0283; GFX12-NEXT: s_wait_samplecnt 0x0284; GFX12-NEXT: s_wait_bvhcnt 0x0285; GFX12-NEXT: s_wait_kmcnt 0x0286; GFX12-NEXT: v_mul_lo_u16 v0, v0, v1287; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)288; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16289; GFX12-NEXT: s_setpc_b64 s[30:31]290;291; GFX1250-LABEL: v_mul_i16_signext:292; GFX1250: ; %bb.0:293; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0294; GFX1250-NEXT: s_wait_kmcnt 0x0295; GFX1250-NEXT: v_mul_lo_u16 v0, v0, v1296; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)297; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 16298; GFX1250-NEXT: s_set_pc_i64 s[30:31]299 %result = mul i16 %num, %den300 ret i16 %result301}302 303define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) {304; GCN-LABEL: s_mul_i32:305; GCN: ; %bb.0:306; GCN-NEXT: s_mul_i32 s0, s0, s1307; GCN-NEXT: ; return to shader part epilog308;309; GFX10PLUS-LABEL: s_mul_i32:310; GFX10PLUS: ; %bb.0:311; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s1312; GFX10PLUS-NEXT: ; return to shader part epilog313;314; GFX12-LABEL: s_mul_i32:315; GFX12: ; %bb.0:316; GFX12-NEXT: s_mul_i32 s0, s0, s1317; GFX12-NEXT: ; return to shader part epilog318;319; GFX1250-LABEL: s_mul_i32:320; GFX1250: ; %bb.0:321; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1322; GFX1250-NEXT: s_mul_i32 s0, s0, s1323; GFX1250-NEXT: ; return to shader part epilog324 %result = mul i32 %num, %den325 ret i32 %result326}327 328define i32 @v_mul_i32(i32 %num, i32 %den) {329; GCN-LABEL: v_mul_i32:330; GCN: ; %bb.0:331; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)332; GCN-NEXT: v_mul_lo_u32 v0, v0, v1333; GCN-NEXT: s_setpc_b64 s[30:31]334;335; GFX10PLUS-LABEL: v_mul_i32:336; GFX10PLUS: ; %bb.0:337; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)338; GFX10PLUS-NEXT: v_mul_lo_u32 v0, v0, v1339; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]340;341; GFX12-LABEL: v_mul_i32:342; GFX12: ; %bb.0:343; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0344; GFX12-NEXT: s_wait_expcnt 0x0345; GFX12-NEXT: s_wait_samplecnt 0x0346; GFX12-NEXT: s_wait_bvhcnt 0x0347; GFX12-NEXT: s_wait_kmcnt 0x0348; GFX12-NEXT: v_mul_lo_u32 v0, v0, v1349; GFX12-NEXT: s_setpc_b64 s[30:31]350;351; GFX1250-LABEL: v_mul_i32:352; GFX1250: ; %bb.0:353; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0354; GFX1250-NEXT: s_wait_kmcnt 0x0355; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1356; GFX1250-NEXT: s_set_pc_i64 s[30:31]357 %result = mul i32 %num, %den358 ret i32 %result359}360 361define amdgpu_ps <2 x i32> @s_mul_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) {362; GCN-LABEL: s_mul_v2i32:363; GCN: ; %bb.0:364; GCN-NEXT: s_mul_i32 s0, s0, s2365; GCN-NEXT: s_mul_i32 s1, s1, s3366; GCN-NEXT: ; return to shader part epilog367;368; GFX10PLUS-LABEL: s_mul_v2i32:369; GFX10PLUS: ; %bb.0:370; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2371; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s3372; GFX10PLUS-NEXT: ; return to shader part epilog373;374; GFX12-LABEL: s_mul_v2i32:375; GFX12: ; %bb.0:376; GFX12-NEXT: s_mul_i32 s0, s0, s2377; GFX12-NEXT: s_mul_i32 s1, s1, s3378; GFX12-NEXT: ; return to shader part epilog379;380; GFX1250-LABEL: s_mul_v2i32:381; GFX1250: ; %bb.0:382; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1383; GFX1250-NEXT: s_mul_i32 s0, s0, s2384; GFX1250-NEXT: s_mul_i32 s1, s1, s3385; GFX1250-NEXT: ; return to shader part epilog386 %result = mul <2 x i32> %num, %den387 ret <2 x i32> %result388}389 390define <2 x i32> @v_mul_v2i32(<2 x i32> %num, <2 x i32> %den) {391; GCN-LABEL: v_mul_v2i32:392; GCN: ; %bb.0:393; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)394; GCN-NEXT: v_mul_lo_u32 v0, v0, v2395; GCN-NEXT: v_mul_lo_u32 v1, v1, v3396; GCN-NEXT: s_setpc_b64 s[30:31]397;398; GFX10PLUS-LABEL: v_mul_v2i32:399; GFX10PLUS: ; %bb.0:400; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)401; GFX10PLUS-NEXT: v_mul_lo_u32 v0, v0, v2402; GFX10PLUS-NEXT: v_mul_lo_u32 v1, v1, v3403; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]404;405; GFX12-LABEL: v_mul_v2i32:406; GFX12: ; %bb.0:407; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0408; GFX12-NEXT: s_wait_expcnt 0x0409; GFX12-NEXT: s_wait_samplecnt 0x0410; GFX12-NEXT: s_wait_bvhcnt 0x0411; GFX12-NEXT: s_wait_kmcnt 0x0412; GFX12-NEXT: v_mul_lo_u32 v0, v0, v2413; GFX12-NEXT: v_mul_lo_u32 v1, v1, v3414; GFX12-NEXT: s_setpc_b64 s[30:31]415;416; GFX1250-LABEL: v_mul_v2i32:417; GFX1250: ; %bb.0:418; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0419; GFX1250-NEXT: s_wait_kmcnt 0x0420; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v2421; GFX1250-NEXT: v_mul_lo_u32 v1, v1, v3422; GFX1250-NEXT: s_set_pc_i64 s[30:31]423 %result = mul <2 x i32> %num, %den424 ret <2 x i32> %result425}426 427define amdgpu_cs i33 @s_mul_i33(i33 inreg %num, i33 inreg %den) {428; GFX7-LABEL: s_mul_i33:429; GFX7: ; %bb.0:430; GFX7-NEXT: v_mov_b32_e32 v0, s2431; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0432; GFX7-NEXT: s_mul_i32 s4, s0, s2433; GFX7-NEXT: s_mul_i32 s0, s0, s3434; GFX7-NEXT: s_mul_i32 s1, s1, s2435; GFX7-NEXT: v_readfirstlane_b32 s5, v0436; GFX7-NEXT: s_add_u32 s0, s0, s5437; GFX7-NEXT: s_add_u32 s1, s1, s0438; GFX7-NEXT: s_mov_b32 s0, s4439; GFX7-NEXT: ; return to shader part epilog440;441; GFX8-LABEL: s_mul_i33:442; GFX8: ; %bb.0:443; GFX8-NEXT: v_mov_b32_e32 v0, s2444; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0445; GFX8-NEXT: s_mul_i32 s4, s0, s2446; GFX8-NEXT: s_mul_i32 s0, s0, s3447; GFX8-NEXT: s_mul_i32 s1, s1, s2448; GFX8-NEXT: v_readfirstlane_b32 s5, v0449; GFX8-NEXT: s_add_u32 s0, s0, s5450; GFX8-NEXT: s_add_u32 s1, s1, s0451; GFX8-NEXT: s_mov_b32 s0, s4452; GFX8-NEXT: ; return to shader part epilog453;454; GFX9-LABEL: s_mul_i33:455; GFX9: ; %bb.0:456; GFX9-NEXT: s_mul_i32 s4, s0, s2457; GFX9-NEXT: s_mul_hi_u32 s5, s0, s2458; GFX9-NEXT: s_mul_i32 s0, s0, s3459; GFX9-NEXT: s_add_u32 s0, s0, s5460; GFX9-NEXT: s_mul_i32 s1, s1, s2461; GFX9-NEXT: s_add_u32 s1, s1, s0462; GFX9-NEXT: s_mov_b32 s0, s4463; GFX9-NEXT: ; return to shader part epilog464;465; GFX10PLUS-LABEL: s_mul_i33:466; GFX10PLUS: ; %bb.0:467; GFX10PLUS-NEXT: s_mul_hi_u32 s4, s0, s2468; GFX10PLUS-NEXT: s_mul_i32 s3, s0, s3469; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s2470; GFX10PLUS-NEXT: s_add_i32 s3, s4, s3471; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2472; GFX10PLUS-NEXT: s_add_i32 s1, s3, s1473; GFX10PLUS-NEXT: ; return to shader part epilog474;475; GFX12-LABEL: s_mul_i33:476; GFX12: ; %bb.0:477; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]478; GFX12-NEXT: ; return to shader part epilog479;480; GFX1250-LABEL: s_mul_i33:481; GFX1250: ; %bb.0:482; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1483; GFX1250-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]484; GFX1250-NEXT: ; return to shader part epilog485 %result = mul i33 %num, %den486 ret i33 %result487}488 489define amdgpu_ps i64 @s_mul_i64(i64 inreg %num, i64 inreg %den) {490; GFX7-LABEL: s_mul_i64:491; GFX7: ; %bb.0:492; GFX7-NEXT: v_mov_b32_e32 v0, s2493; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0494; GFX7-NEXT: s_mul_i32 s4, s0, s2495; GFX7-NEXT: s_mul_i32 s0, s0, s3496; GFX7-NEXT: s_mul_i32 s1, s1, s2497; GFX7-NEXT: v_readfirstlane_b32 s5, v0498; GFX7-NEXT: s_add_u32 s0, s0, s5499; GFX7-NEXT: s_add_u32 s1, s1, s0500; GFX7-NEXT: s_mov_b32 s0, s4501; GFX7-NEXT: ; return to shader part epilog502;503; GFX8-LABEL: s_mul_i64:504; GFX8: ; %bb.0:505; GFX8-NEXT: v_mov_b32_e32 v0, s2506; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0507; GFX8-NEXT: s_mul_i32 s4, s0, s2508; GFX8-NEXT: s_mul_i32 s0, s0, s3509; GFX8-NEXT: s_mul_i32 s1, s1, s2510; GFX8-NEXT: v_readfirstlane_b32 s5, v0511; GFX8-NEXT: s_add_u32 s0, s0, s5512; GFX8-NEXT: s_add_u32 s1, s1, s0513; GFX8-NEXT: s_mov_b32 s0, s4514; GFX8-NEXT: ; return to shader part epilog515;516; GFX9-LABEL: s_mul_i64:517; GFX9: ; %bb.0:518; GFX9-NEXT: s_mul_i32 s4, s0, s2519; GFX9-NEXT: s_mul_hi_u32 s5, s0, s2520; GFX9-NEXT: s_mul_i32 s0, s0, s3521; GFX9-NEXT: s_add_u32 s0, s0, s5522; GFX9-NEXT: s_mul_i32 s1, s1, s2523; GFX9-NEXT: s_add_u32 s1, s1, s0524; GFX9-NEXT: s_mov_b32 s0, s4525; GFX9-NEXT: ; return to shader part epilog526;527; GFX10PLUS-LABEL: s_mul_i64:528; GFX10PLUS: ; %bb.0:529; GFX10PLUS-NEXT: s_mul_hi_u32 s4, s0, s2530; GFX10PLUS-NEXT: s_mul_i32 s3, s0, s3531; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s2532; GFX10PLUS-NEXT: s_add_i32 s3, s4, s3533; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s2534; GFX10PLUS-NEXT: s_add_i32 s1, s3, s1535; GFX10PLUS-NEXT: ; return to shader part epilog536;537; GFX12-LABEL: s_mul_i64:538; GFX12: ; %bb.0:539; GFX12-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]540; GFX12-NEXT: ; return to shader part epilog541;542; GFX1250-LABEL: s_mul_i64:543; GFX1250: ; %bb.0:544; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1545; GFX1250-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]546; GFX1250-NEXT: ; return to shader part epilog547 %result = mul i64 %num, %den548 ret i64 %result549}550 551define i64 @v_mul_i64(i64 %num, i64 %den) {552; GCN-LABEL: v_mul_i64:553; GCN: ; %bb.0:554; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)555; GCN-NEXT: v_mov_b32_e32 v4, v0556; GCN-NEXT: v_mov_b32_e32 v5, v2557; GCN-NEXT: v_mov_b32_e32 v6, v1558; GCN-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v5, 0559; GCN-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v4, v3, v[1:2]560; GCN-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v6, v5, v[7:8]561; GCN-NEXT: s_setpc_b64 s[30:31]562;563; GFX10-LABEL: v_mul_i64:564; GFX10: ; %bb.0:565; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)566; GFX10-NEXT: v_mov_b32_e32 v4, v0567; GFX10-NEXT: v_mov_b32_e32 v5, v1568; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0569; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v4, v3, v[1:2]570; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v5, v2, v[3:4]571; GFX10-NEXT: s_setpc_b64 s[30:31]572;573; GFX11-LABEL: v_mul_i64:574; GFX11: ; %bb.0:575; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)576; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v2577; GFX11-NEXT: v_mov_b32_e32 v6, v1578; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v5, 0579; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v4, v3, v[1:2]580; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v6, v5, v[7:8]581; GFX11-NEXT: s_setpc_b64 s[30:31]582;583; GFX12-LABEL: v_mul_i64:584; GFX12: ; %bb.0:585; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0586; GFX12-NEXT: s_wait_expcnt 0x0587; GFX12-NEXT: s_wait_samplecnt 0x0588; GFX12-NEXT: s_wait_bvhcnt 0x0589; GFX12-NEXT: s_wait_kmcnt 0x0590; GFX12-NEXT: v_mul_hi_u32 v4, v0, v2591; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)592; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v0, v3, v[4:5]593; GFX12-NEXT: v_mul_lo_u32 v0, v0, v2594; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v1, v2, v[3:4]595; GFX12-NEXT: s_setpc_b64 s[30:31]596;597; GFX1250-LABEL: v_mul_i64:598; GFX1250: ; %bb.0:599; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0600; GFX1250-NEXT: s_wait_kmcnt 0x0601; GFX1250-NEXT: v_mul_u64_e32 v[0:1], v[0:1], v[2:3]602; GFX1250-NEXT: s_set_pc_i64 s[30:31]603 %result = mul i64 %num, %den604 ret i64 %result605}606 607define amdgpu_ps <3 x i32> @s_mul_i96(i96 inreg %num, i96 inreg %den) {608; GFX7-LABEL: s_mul_i96:609; GFX7: ; %bb.0:610; GFX7-NEXT: v_mov_b32_e32 v0, s3611; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0612; GFX7-NEXT: v_mov_b32_e32 v1, s4613; GFX7-NEXT: v_mul_hi_u32 v1, s0, v1614; GFX7-NEXT: s_mul_i32 s5, s0, s5615; GFX7-NEXT: v_readfirstlane_b32 s7, v0616; GFX7-NEXT: s_mul_i32 s8, s1, s4617; GFX7-NEXT: v_mov_b32_e32 v0, s1618; GFX7-NEXT: s_add_u32 s5, s8, s5619; GFX7-NEXT: s_mul_i32 s2, s2, s3620; GFX7-NEXT: v_mul_hi_u32 v0, v0, s3621; GFX7-NEXT: s_mul_i32 s6, s0, s3622; GFX7-NEXT: s_add_u32 s2, s2, s5623; GFX7-NEXT: s_mul_i32 s0, s0, s4624; GFX7-NEXT: v_readfirstlane_b32 s4, v1625; GFX7-NEXT: s_add_u32 s0, s0, s7626; GFX7-NEXT: s_addc_u32 s2, s4, s2627; GFX7-NEXT: s_mul_i32 s1, s1, s3628; GFX7-NEXT: v_readfirstlane_b32 s3, v0629; GFX7-NEXT: s_add_u32 s1, s1, s0630; GFX7-NEXT: s_addc_u32 s2, s3, s2631; GFX7-NEXT: s_mov_b32 s0, s6632; GFX7-NEXT: ; return to shader part epilog633;634; GFX8-LABEL: s_mul_i96:635; GFX8: ; %bb.0:636; GFX8-NEXT: v_mov_b32_e32 v0, s3637; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0638; GFX8-NEXT: v_mov_b32_e32 v1, s4639; GFX8-NEXT: v_mul_hi_u32 v1, s0, v1640; GFX8-NEXT: s_mul_i32 s5, s0, s5641; GFX8-NEXT: v_readfirstlane_b32 s7, v0642; GFX8-NEXT: s_mul_i32 s8, s1, s4643; GFX8-NEXT: v_mov_b32_e32 v0, s1644; GFX8-NEXT: s_add_u32 s5, s8, s5645; GFX8-NEXT: s_mul_i32 s2, s2, s3646; GFX8-NEXT: v_mul_hi_u32 v0, v0, s3647; GFX8-NEXT: s_mul_i32 s6, s0, s3648; GFX8-NEXT: s_add_u32 s2, s2, s5649; GFX8-NEXT: s_mul_i32 s0, s0, s4650; GFX8-NEXT: v_readfirstlane_b32 s4, v1651; GFX8-NEXT: s_add_u32 s0, s0, s7652; GFX8-NEXT: s_addc_u32 s2, s4, s2653; GFX8-NEXT: s_mul_i32 s1, s1, s3654; GFX8-NEXT: v_readfirstlane_b32 s3, v0655; GFX8-NEXT: s_add_u32 s1, s1, s0656; GFX8-NEXT: s_addc_u32 s2, s3, s2657; GFX8-NEXT: s_mov_b32 s0, s6658; GFX8-NEXT: ; return to shader part epilog659;660; GFX9-LABEL: s_mul_i96:661; GFX9: ; %bb.0:662; GFX9-NEXT: s_mul_i32 s5, s0, s5663; GFX9-NEXT: s_mul_i32 s8, s1, s4664; GFX9-NEXT: s_add_u32 s5, s8, s5665; GFX9-NEXT: s_mul_i32 s2, s2, s3666; GFX9-NEXT: s_mul_hi_u32 s7, s0, s3667; GFX9-NEXT: s_add_u32 s2, s2, s5668; GFX9-NEXT: s_mul_i32 s5, s0, s4669; GFX9-NEXT: s_mul_i32 s6, s0, s3670; GFX9-NEXT: s_mul_hi_u32 s0, s0, s4671; GFX9-NEXT: s_add_u32 s4, s5, s7672; GFX9-NEXT: s_addc_u32 s0, s0, s2673; GFX9-NEXT: s_mul_i32 s2, s1, s3674; GFX9-NEXT: s_mul_hi_u32 s3, s1, s3675; GFX9-NEXT: s_add_u32 s1, s2, s4676; GFX9-NEXT: s_addc_u32 s2, s3, s0677; GFX9-NEXT: s_mov_b32 s0, s6678; GFX9-NEXT: ; return to shader part epilog679;680; GFX10PLUS-LABEL: s_mul_i96:681; GFX10PLUS: ; %bb.0:682; GFX10PLUS-NEXT: s_mul_i32 s6, s0, s5683; GFX10PLUS-NEXT: s_mul_i32 s7, s1, s4684; GFX10PLUS-NEXT: s_mul_i32 s2, s2, s3685; GFX10PLUS-NEXT: s_add_i32 s6, s6, s7686; GFX10PLUS-NEXT: s_mul_hi_u32 s7, s0, s3687; GFX10PLUS-NEXT: s_add_i32 s6, s6, s2688; GFX10PLUS-NEXT: s_mul_i32 s2, s0, s4689; GFX10PLUS-NEXT: s_mul_i32 s5, s0, s3690; GFX10PLUS-NEXT: s_mul_hi_u32 s0, s0, s4691; GFX10PLUS-NEXT: s_add_u32 s2, s2, s7692; GFX10PLUS-NEXT: s_mul_i32 s4, s1, s3693; GFX10PLUS-NEXT: s_addc_u32 s0, s0, s6694; GFX10PLUS-NEXT: s_mul_hi_u32 s3, s1, s3695; GFX10PLUS-NEXT: s_add_u32 s1, s4, s2696; GFX10PLUS-NEXT: s_addc_u32 s2, s3, s0697; GFX10PLUS-NEXT: s_mov_b32 s0, s5698; GFX10PLUS-NEXT: ; return to shader part epilog699;700; GFX12-LABEL: s_mul_i96:701; GFX12: ; %bb.0:702; GFX12-NEXT: s_mul_i32 s6, s0, s5703; GFX12-NEXT: s_mul_i32 s7, s1, s4704; GFX12-NEXT: s_mul_i32 s2, s2, s3705; GFX12-NEXT: s_add_co_i32 s6, s6, s7706; GFX12-NEXT: s_mul_hi_u32 s7, s0, s3707; GFX12-NEXT: s_add_co_i32 s6, s6, s2708; GFX12-NEXT: s_mul_i32 s2, s0, s4709; GFX12-NEXT: s_mul_i32 s5, s0, s3710; GFX12-NEXT: s_mul_hi_u32 s0, s0, s4711; GFX12-NEXT: s_add_co_u32 s2, s2, s7712; GFX12-NEXT: s_mul_i32 s4, s1, s3713; GFX12-NEXT: s_add_co_ci_u32 s0, s0, s6714; GFX12-NEXT: s_mul_hi_u32 s3, s1, s3715; GFX12-NEXT: s_add_co_u32 s1, s4, s2716; GFX12-NEXT: s_add_co_ci_u32 s2, s3, s0717; GFX12-NEXT: s_mov_b32 s0, s5718; GFX12-NEXT: ; return to shader part epilog719;720; GFX1250-LABEL: s_mul_i96:721; GFX1250: ; %bb.0:722; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1723; GFX1250-NEXT: s_mul_i32 s6, s0, s5724; GFX1250-NEXT: s_mul_i32 s7, s1, s4725; GFX1250-NEXT: s_mul_i32 s2, s2, s3726; GFX1250-NEXT: s_add_co_i32 s6, s6, s7727; GFX1250-NEXT: s_mul_hi_u32 s7, s0, s3728; GFX1250-NEXT: s_add_co_i32 s6, s6, s2729; GFX1250-NEXT: s_mul_i32 s2, s0, s4730; GFX1250-NEXT: s_mul_i32 s5, s0, s3731; GFX1250-NEXT: s_mul_hi_u32 s0, s0, s4732; GFX1250-NEXT: s_add_co_u32 s2, s2, s7733; GFX1250-NEXT: s_mul_i32 s4, s1, s3734; GFX1250-NEXT: s_add_co_ci_u32 s0, s0, s6735; GFX1250-NEXT: s_mul_hi_u32 s3, s1, s3736; GFX1250-NEXT: s_add_co_u32 s1, s4, s2737; GFX1250-NEXT: s_add_co_ci_u32 s2, s3, s0738; GFX1250-NEXT: s_mov_b32 s0, s5739; GFX1250-NEXT: ; return to shader part epilog740 %result = mul i96 %num, %den741 %cast = bitcast i96 %result to <3 x i32>742 ret <3 x i32> %cast743}744 745define i96 @v_mul_i96(i96 %num, i96 %den) {746; GCN-LABEL: v_mul_i96:747; GCN: ; %bb.0:748; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)749; GCN-NEXT: v_mov_b32_e32 v6, v0750; GCN-NEXT: v_mov_b32_e32 v7, v1751; GCN-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v5, 0752; GCN-NEXT: v_mov_b32_e32 v8, v2753; GCN-NEXT: v_mov_b32_e32 v9, v3754; GCN-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v7, v4, v[0:1]755; GCN-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v9, 0756; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v9, v[10:11]757; GCN-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v6, v4, v[1:2]758; GCN-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v7, v9, v[10:11]759; GCN-NEXT: s_setpc_b64 s[30:31]760;761; GFX10-LABEL: v_mul_i96:762; GFX10: ; %bb.0:763; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)764; GFX10-NEXT: v_mov_b32_e32 v6, v0765; GFX10-NEXT: v_mov_b32_e32 v7, v1766; GFX10-NEXT: v_mov_b32_e32 v8, v3767; GFX10-NEXT: v_mul_lo_u32 v0, v6, v5768; GFX10-NEXT: v_mad_u64_u32 v[9:10], s4, v7, v4, v[0:1]769; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v6, v8, 0770; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v2, v8, v[9:10]771; GFX10-NEXT: v_mad_u64_u32 v[9:10], s4, v6, v4, v[1:2]772; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v7, v8, v[9:10]773; GFX10-NEXT: s_setpc_b64 s[30:31]774;775; GFX11-LABEL: v_mul_i96:776; GFX11: ; %bb.0:777; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)778; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1779; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v9, v3780; GFX11-NEXT: v_mul_lo_u32 v0, v6, v5781; GFX11-NEXT: v_mad_u64_u32 v[10:11], null, v7, v4, v[0:1]782; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v6, v9, 0783; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v8, v9, v[10:11]784; GFX11-NEXT: v_mad_u64_u32 v[10:11], null, v6, v4, v[1:2]785; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v7, v9, v[10:11]786; GFX11-NEXT: s_setpc_b64 s[30:31]787;788; GFX12-LABEL: v_mul_i96:789; GFX12: ; %bb.0:790; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0791; GFX12-NEXT: s_wait_expcnt 0x0792; GFX12-NEXT: s_wait_samplecnt 0x0793; GFX12-NEXT: s_wait_bvhcnt 0x0794; GFX12-NEXT: s_wait_kmcnt 0x0795; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1796; GFX12-NEXT: v_mov_b32_e32 v8, v3797; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)798; GFX12-NEXT: v_mul_lo_u32 v0, v6, v5799; GFX12-NEXT: v_mad_co_u64_u32 v[9:10], null, v7, v4, v[0:1]800; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)801; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v6, v8, 0802; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, v2, v8, v[9:10]803; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)804; GFX12-NEXT: v_mad_co_u64_u32 v[9:10], null, v6, v4, v[1:2]805; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v7, v8, v[9:10]806; GFX12-NEXT: s_setpc_b64 s[30:31]807;808; GFX1250-LABEL: v_mul_i96:809; GFX1250: ; %bb.0:810; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0811; GFX1250-NEXT: s_wait_kmcnt 0x0812; GFX1250-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1813; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)814; GFX1250-NEXT: v_mul_lo_u32 v0, v7, v4815; GFX1250-NEXT: v_mad_u32 v5, v6, v5, v0816; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v6, v3, 0817; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)818; GFX1250-NEXT: v_mad_u32 v9, v2, v3, v5819; GFX1250-NEXT: v_mov_b32_e32 v8, v1820; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)821; GFX1250-NEXT: v_mad_nc_u64_u32 v[10:11], v6, v4, v[8:9]822; GFX1250-NEXT: v_mad_nc_u64_u32 v[4:5], v7, v3, v[10:11]823; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)824; GFX1250-NEXT: v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v2, v5825; GFX1250-NEXT: s_set_pc_i64 s[30:31]826 %result = mul i96 %num, %den827 ret i96 %result828}829 830define amdgpu_ps <4 x i32> @s_mul_i128(i128 inreg %num, i128 inreg %den) {831; GFX7-LABEL: s_mul_i128:832; GFX7: ; %bb.0:833; GFX7-NEXT: v_mov_b32_e32 v0, s4834; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0835; GFX7-NEXT: v_mov_b32_e32 v1, s5836; GFX7-NEXT: v_mul_hi_u32 v2, s1, v1837; GFX7-NEXT: s_mul_i32 s10, s0, s6838; GFX7-NEXT: v_readfirstlane_b32 s9, v0839; GFX7-NEXT: v_mov_b32_e32 v0, s6840; GFX7-NEXT: v_mul_hi_u32 v0, s0, v0841; GFX7-NEXT: v_readfirstlane_b32 s13, v2842; GFX7-NEXT: v_mov_b32_e32 v2, s2843; GFX7-NEXT: v_mul_hi_u32 v2, v2, s4844; GFX7-NEXT: s_mul_i32 s12, s1, s5845; GFX7-NEXT: v_readfirstlane_b32 s11, v0846; GFX7-NEXT: s_add_u32 s10, s12, s10847; GFX7-NEXT: v_mul_hi_u32 v1, s0, v1848; GFX7-NEXT: v_mov_b32_e32 v0, s1849; GFX7-NEXT: s_addc_u32 s11, s13, s11850; GFX7-NEXT: s_mul_i32 s12, s2, s4851; GFX7-NEXT: v_readfirstlane_b32 s13, v2852; GFX7-NEXT: s_add_u32 s10, s12, s10853; GFX7-NEXT: v_mul_hi_u32 v0, v0, s4854; GFX7-NEXT: s_addc_u32 s11, s13, s11855; GFX7-NEXT: s_mul_i32 s12, s0, s5856; GFX7-NEXT: v_readfirstlane_b32 s13, v1857; GFX7-NEXT: s_add_u32 s9, s12, s9858; GFX7-NEXT: s_addc_u32 s10, s13, s10859; GFX7-NEXT: s_mul_i32 s13, s1, s4860; GFX7-NEXT: s_cselect_b32 s12, 1, 0861; GFX7-NEXT: v_readfirstlane_b32 s14, v0862; GFX7-NEXT: s_add_u32 s9, s13, s9863; GFX7-NEXT: s_mul_i32 s8, s0, s4864; GFX7-NEXT: s_addc_u32 s10, s14, s10865; GFX7-NEXT: s_mul_i32 s0, s0, s7866; GFX7-NEXT: s_addc_u32 s0, s11, s0867; GFX7-NEXT: s_mul_i32 s1, s1, s6868; GFX7-NEXT: s_cmp_lg_u32 s12, 0869; GFX7-NEXT: s_addc_u32 s0, s0, s1870; GFX7-NEXT: s_mul_i32 s2, s2, s5871; GFX7-NEXT: s_add_u32 s0, s2, s0872; GFX7-NEXT: s_mul_i32 s3, s3, s4873; GFX7-NEXT: s_add_u32 s3, s3, s0874; GFX7-NEXT: s_mov_b32 s0, s8875; GFX7-NEXT: s_mov_b32 s1, s9876; GFX7-NEXT: s_mov_b32 s2, s10877; GFX7-NEXT: ; return to shader part epilog878;879; GFX8-LABEL: s_mul_i128:880; GFX8: ; %bb.0:881; GFX8-NEXT: v_mov_b32_e32 v0, s4882; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0883; GFX8-NEXT: v_mov_b32_e32 v1, s5884; GFX8-NEXT: v_mul_hi_u32 v2, s1, v1885; GFX8-NEXT: s_mul_i32 s10, s0, s6886; GFX8-NEXT: v_readfirstlane_b32 s9, v0887; GFX8-NEXT: v_mov_b32_e32 v0, s6888; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0889; GFX8-NEXT: v_readfirstlane_b32 s13, v2890; GFX8-NEXT: v_mov_b32_e32 v2, s2891; GFX8-NEXT: v_mul_hi_u32 v2, v2, s4892; GFX8-NEXT: s_mul_i32 s12, s1, s5893; GFX8-NEXT: v_readfirstlane_b32 s11, v0894; GFX8-NEXT: s_add_u32 s10, s12, s10895; GFX8-NEXT: v_mul_hi_u32 v1, s0, v1896; GFX8-NEXT: v_mov_b32_e32 v0, s1897; GFX8-NEXT: s_addc_u32 s11, s13, s11898; GFX8-NEXT: s_mul_i32 s12, s2, s4899; GFX8-NEXT: v_readfirstlane_b32 s13, v2900; GFX8-NEXT: s_add_u32 s10, s12, s10901; GFX8-NEXT: v_mul_hi_u32 v0, v0, s4902; GFX8-NEXT: s_addc_u32 s11, s13, s11903; GFX8-NEXT: s_mul_i32 s12, s0, s5904; GFX8-NEXT: v_readfirstlane_b32 s13, v1905; GFX8-NEXT: s_add_u32 s9, s12, s9906; GFX8-NEXT: s_addc_u32 s10, s13, s10907; GFX8-NEXT: s_mul_i32 s13, s1, s4908; GFX8-NEXT: s_cselect_b32 s12, 1, 0909; GFX8-NEXT: v_readfirstlane_b32 s14, v0910; GFX8-NEXT: s_add_u32 s9, s13, s9911; GFX8-NEXT: s_mul_i32 s8, s0, s4912; GFX8-NEXT: s_addc_u32 s10, s14, s10913; GFX8-NEXT: s_mul_i32 s0, s0, s7914; GFX8-NEXT: s_addc_u32 s0, s11, s0915; GFX8-NEXT: s_mul_i32 s1, s1, s6916; GFX8-NEXT: s_cmp_lg_u32 s12, 0917; GFX8-NEXT: s_addc_u32 s0, s0, s1918; GFX8-NEXT: s_mul_i32 s2, s2, s5919; GFX8-NEXT: s_add_u32 s0, s2, s0920; GFX8-NEXT: s_mul_i32 s3, s3, s4921; GFX8-NEXT: s_add_u32 s3, s3, s0922; GFX8-NEXT: s_mov_b32 s0, s8923; GFX8-NEXT: s_mov_b32 s1, s9924; GFX8-NEXT: s_mov_b32 s2, s10925; GFX8-NEXT: ; return to shader part epilog926;927; GFX9-LABEL: s_mul_i128:928; GFX9: ; %bb.0:929; GFX9-NEXT: s_mul_i32 s10, s0, s6930; GFX9-NEXT: s_mul_i32 s12, s1, s5931; GFX9-NEXT: s_mul_hi_u32 s11, s0, s6932; GFX9-NEXT: s_mul_hi_u32 s13, s1, s5933; GFX9-NEXT: s_add_u32 s10, s12, s10934; GFX9-NEXT: s_addc_u32 s11, s13, s11935; GFX9-NEXT: s_mul_i32 s12, s2, s4936; GFX9-NEXT: s_mul_hi_u32 s13, s2, s4937; GFX9-NEXT: s_add_u32 s10, s12, s10938; GFX9-NEXT: s_mul_hi_u32 s9, s0, s4939; GFX9-NEXT: s_addc_u32 s11, s13, s11940; GFX9-NEXT: s_mul_i32 s12, s0, s5941; GFX9-NEXT: s_mul_hi_u32 s13, s0, s5942; GFX9-NEXT: s_add_u32 s9, s12, s9943; GFX9-NEXT: s_addc_u32 s10, s13, s10944; GFX9-NEXT: s_mul_i32 s13, s1, s4945; GFX9-NEXT: s_cselect_b32 s12, 1, 0946; GFX9-NEXT: s_mul_hi_u32 s14, s1, s4947; GFX9-NEXT: s_add_u32 s9, s13, s9948; GFX9-NEXT: s_mul_i32 s8, s0, s4949; GFX9-NEXT: s_addc_u32 s10, s14, s10950; GFX9-NEXT: s_mul_i32 s0, s0, s7951; GFX9-NEXT: s_addc_u32 s0, s11, s0952; GFX9-NEXT: s_mul_i32 s1, s1, s6953; GFX9-NEXT: s_cmp_lg_u32 s12, 0954; GFX9-NEXT: s_addc_u32 s0, s0, s1955; GFX9-NEXT: s_mul_i32 s2, s2, s5956; GFX9-NEXT: s_add_u32 s0, s2, s0957; GFX9-NEXT: s_mul_i32 s3, s3, s4958; GFX9-NEXT: s_add_u32 s3, s3, s0959; GFX9-NEXT: s_mov_b32 s0, s8960; GFX9-NEXT: s_mov_b32 s1, s9961; GFX9-NEXT: s_mov_b32 s2, s10962; GFX9-NEXT: ; return to shader part epilog963;964; GFX10PLUS-LABEL: s_mul_i128:965; GFX10PLUS: ; %bb.0:966; GFX10PLUS-NEXT: s_mul_i32 s9, s0, s6967; GFX10PLUS-NEXT: s_mul_i32 s11, s1, s5968; GFX10PLUS-NEXT: s_mul_hi_u32 s10, s0, s6969; GFX10PLUS-NEXT: s_mul_hi_u32 s12, s1, s5970; GFX10PLUS-NEXT: s_add_u32 s9, s11, s9971; GFX10PLUS-NEXT: s_mul_i32 s11, s2, s4972; GFX10PLUS-NEXT: s_addc_u32 s10, s12, s10973; GFX10PLUS-NEXT: s_mul_hi_u32 s12, s2, s4974; GFX10PLUS-NEXT: s_mul_hi_u32 s8, s0, s4975; GFX10PLUS-NEXT: s_add_u32 s9, s11, s9976; GFX10PLUS-NEXT: s_mul_i32 s11, s0, s5977; GFX10PLUS-NEXT: s_addc_u32 s10, s12, s10978; GFX10PLUS-NEXT: s_mul_hi_u32 s12, s0, s5979; GFX10PLUS-NEXT: s_add_u32 s8, s11, s8980; GFX10PLUS-NEXT: s_addc_u32 s9, s12, s9981; GFX10PLUS-NEXT: s_mul_i32 s12, s1, s4982; GFX10PLUS-NEXT: s_mul_hi_u32 s13, s1, s4983; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0984; GFX10PLUS-NEXT: s_add_u32 s8, s12, s8985; GFX10PLUS-NEXT: s_mul_i32 s12, s0, s7986; GFX10PLUS-NEXT: s_addc_u32 s7, s13, s9987; GFX10PLUS-NEXT: s_addc_u32 s9, s10, s12988; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s6989; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0990; GFX10PLUS-NEXT: s_mul_i32 s2, s2, s5991; GFX10PLUS-NEXT: s_addc_u32 s1, s9, s1992; GFX10PLUS-NEXT: s_mul_i32 s3, s3, s4993; GFX10PLUS-NEXT: s_add_i32 s1, s1, s2994; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s4995; GFX10PLUS-NEXT: s_add_i32 s3, s1, s3996; GFX10PLUS-NEXT: s_mov_b32 s1, s8997; GFX10PLUS-NEXT: s_mov_b32 s2, s7998; GFX10PLUS-NEXT: ; return to shader part epilog999;1000; GFX12-LABEL: s_mul_i128:1001; GFX12: ; %bb.0:1002; GFX12-NEXT: s_mul_i32 s9, s0, s61003; GFX12-NEXT: s_mul_i32 s11, s1, s51004; GFX12-NEXT: s_mul_hi_u32 s10, s0, s61005; GFX12-NEXT: s_mul_hi_u32 s12, s1, s51006; GFX12-NEXT: s_add_co_u32 s9, s11, s91007; GFX12-NEXT: s_mul_i32 s11, s2, s41008; GFX12-NEXT: s_add_co_ci_u32 s10, s12, s101009; GFX12-NEXT: s_mul_hi_u32 s12, s2, s41010; GFX12-NEXT: s_mul_hi_u32 s8, s0, s41011; GFX12-NEXT: s_add_co_u32 s9, s11, s91012; GFX12-NEXT: s_mul_i32 s11, s0, s51013; GFX12-NEXT: s_add_co_ci_u32 s10, s12, s101014; GFX12-NEXT: s_mul_hi_u32 s12, s0, s51015; GFX12-NEXT: s_add_co_u32 s8, s11, s81016; GFX12-NEXT: s_add_co_ci_u32 s9, s12, s91017; GFX12-NEXT: s_mul_i32 s12, s1, s41018; GFX12-NEXT: s_mul_hi_u32 s13, s1, s41019; GFX12-NEXT: s_cselect_b32 s11, 1, 01020; GFX12-NEXT: s_add_co_u32 s8, s12, s81021; GFX12-NEXT: s_mul_i32 s12, s0, s71022; GFX12-NEXT: s_add_co_ci_u32 s7, s13, s91023; GFX12-NEXT: s_add_co_ci_u32 s9, s10, s121024; GFX12-NEXT: s_mul_i32 s1, s1, s61025; GFX12-NEXT: s_cmp_lg_u32 s11, 01026; GFX12-NEXT: s_mul_i32 s2, s2, s51027; GFX12-NEXT: s_add_co_ci_u32 s1, s9, s11028; GFX12-NEXT: s_mul_i32 s3, s3, s41029; GFX12-NEXT: s_add_co_i32 s1, s1, s21030; GFX12-NEXT: s_mul_i32 s0, s0, s41031; GFX12-NEXT: s_add_co_i32 s3, s1, s31032; GFX12-NEXT: s_mov_b32 s1, s81033; GFX12-NEXT: s_mov_b32 s2, s71034; GFX12-NEXT: ; return to shader part epilog1035;1036; GFX1250-LABEL: s_mul_i128:1037; GFX1250: ; %bb.0:1038; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11039; GFX1250-NEXT: s_mul_i32 s9, s0, s61040; GFX1250-NEXT: s_mul_i32 s11, s1, s51041; GFX1250-NEXT: s_mul_hi_u32 s10, s0, s61042; GFX1250-NEXT: s_mul_hi_u32 s12, s1, s51043; GFX1250-NEXT: s_add_co_u32 s9, s11, s91044; GFX1250-NEXT: s_mul_i32 s11, s2, s41045; GFX1250-NEXT: s_add_co_ci_u32 s10, s12, s101046; GFX1250-NEXT: s_mul_hi_u32 s12, s2, s41047; GFX1250-NEXT: s_mul_hi_u32 s8, s0, s41048; GFX1250-NEXT: s_add_co_u32 s9, s11, s91049; GFX1250-NEXT: s_mul_i32 s11, s0, s51050; GFX1250-NEXT: s_add_co_ci_u32 s10, s12, s101051; GFX1250-NEXT: s_mul_hi_u32 s12, s0, s51052; GFX1250-NEXT: s_add_co_u32 s8, s11, s81053; GFX1250-NEXT: s_add_co_ci_u32 s9, s12, s91054; GFX1250-NEXT: s_mul_i32 s12, s1, s41055; GFX1250-NEXT: s_mul_hi_u32 s13, s1, s41056; GFX1250-NEXT: s_cselect_b32 s11, 1, 01057; GFX1250-NEXT: s_add_co_u32 s8, s12, s81058; GFX1250-NEXT: s_mul_i32 s12, s0, s71059; GFX1250-NEXT: s_add_co_ci_u32 s7, s13, s91060; GFX1250-NEXT: s_add_co_ci_u32 s9, s10, s121061; GFX1250-NEXT: s_mul_i32 s1, s1, s61062; GFX1250-NEXT: s_cmp_lg_u32 s11, 01063; GFX1250-NEXT: s_mul_i32 s2, s2, s51064; GFX1250-NEXT: s_add_co_ci_u32 s1, s9, s11065; GFX1250-NEXT: s_mul_i32 s3, s3, s41066; GFX1250-NEXT: s_add_co_i32 s1, s1, s21067; GFX1250-NEXT: s_mul_i32 s0, s0, s41068; GFX1250-NEXT: s_add_co_i32 s3, s1, s31069; GFX1250-NEXT: s_mov_b32 s1, s81070; GFX1250-NEXT: s_mov_b32 s2, s71071; GFX1250-NEXT: ; return to shader part epilog1072 %result = mul i128 %num, %den1073 %cast = bitcast i128 %result to <4 x i32>1074 ret <4 x i32> %cast1075}1076 1077define i128 @v_mul_i128(i128 %num, i128 %den) {1078; GFX7-LABEL: v_mul_i128:1079; GFX7: ; %bb.0:1080; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1081; GFX7-NEXT: v_mov_b32_e32 v8, v01082; GFX7-NEXT: v_mov_b32_e32 v9, v11083; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v6, 01084; GFX7-NEXT: v_mov_b32_e32 v10, v21085; GFX7-NEXT: v_mov_b32_e32 v12, v41086; GFX7-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v9, v5, v[0:1]1087; GFX7-NEXT: v_mov_b32_e32 v11, v31088; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v12, 01089; GFX7-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v12, v[13:14]1090; GFX7-NEXT: v_mul_lo_u32 v4, v9, v61091; GFX7-NEXT: v_mul_lo_u32 v6, v8, v71092; GFX7-NEXT: v_mad_u64_u32 v[13:14], vcc, v8, v5, v[1:2]1093; GFX7-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v12, v[13:14]1094; GFX7-NEXT: v_addc_u32_e64 v3, s[4:5], v3, v6, s[4:5]1095; GFX7-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc1096; GFX7-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v10, v5, v[3:4]1097; GFX7-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v12, v[6:7]1098; GFX7-NEXT: s_setpc_b64 s[30:31]1099;1100; GFX8-LABEL: v_mul_i128:1101; GFX8: ; %bb.0:1102; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1103; GFX8-NEXT: v_mov_b32_e32 v8, v01104; GFX8-NEXT: v_mov_b32_e32 v9, v11105; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v6, 01106; GFX8-NEXT: v_mov_b32_e32 v10, v21107; GFX8-NEXT: v_mov_b32_e32 v12, v41108; GFX8-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v9, v5, v[0:1]1109; GFX8-NEXT: v_mov_b32_e32 v11, v31110; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v12, 01111; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v12, v[13:14]1112; GFX8-NEXT: v_mul_lo_u32 v4, v9, v61113; GFX8-NEXT: v_mul_lo_u32 v6, v8, v71114; GFX8-NEXT: v_mad_u64_u32 v[13:14], vcc, v8, v5, v[1:2]1115; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v12, v[13:14]1116; GFX8-NEXT: v_addc_u32_e64 v3, s[4:5], v3, v6, s[4:5]1117; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc1118; GFX8-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v10, v5, v[3:4]1119; GFX8-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v12, v[6:7]1120; GFX8-NEXT: s_setpc_b64 s[30:31]1121;1122; GFX9-LABEL: v_mul_i128:1123; GFX9: ; %bb.0:1124; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1125; GFX9-NEXT: v_mov_b32_e32 v8, v01126; GFX9-NEXT: v_mov_b32_e32 v9, v11127; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v6, 01128; GFX9-NEXT: v_mov_b32_e32 v10, v21129; GFX9-NEXT: v_mov_b32_e32 v12, v41130; GFX9-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v9, v5, v[0:1]1131; GFX9-NEXT: v_mov_b32_e32 v11, v31132; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v12, 01133; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v12, v[13:14]1134; GFX9-NEXT: v_mul_lo_u32 v4, v9, v61135; GFX9-NEXT: v_mul_lo_u32 v6, v8, v71136; GFX9-NEXT: v_mad_u64_u32 v[13:14], vcc, v8, v5, v[1:2]1137; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v12, v[13:14]1138; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], v3, v6, s[4:5]1139; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc1140; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v10, v5, v[3:4]1141; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v12, v[6:7]1142; GFX9-NEXT: s_setpc_b64 s[30:31]1143;1144; GFX10-LABEL: v_mul_i128:1145; GFX10: ; %bb.0:1146; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1147; GFX10-NEXT: v_mov_b32_e32 v8, v01148; GFX10-NEXT: v_mov_b32_e32 v9, v11149; GFX10-NEXT: v_mov_b32_e32 v10, v21150; GFX10-NEXT: v_mov_b32_e32 v11, v31151; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v6, 01152; GFX10-NEXT: v_mul_lo_u32 v7, v8, v71153; GFX10-NEXT: v_mul_lo_u32 v6, v9, v61154; GFX10-NEXT: v_mad_u64_u32 v[12:13], s4, v9, v5, v[0:1]1155; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v8, v4, 01156; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v10, v4, v[12:13]1157; GFX10-NEXT: v_mad_u64_u32 v[12:13], vcc_lo, v8, v5, v[1:2]1158; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v9, v4, v[12:13]1159; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s4, v3, v7, s41160; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v6, vcc_lo1161; GFX10-NEXT: v_mad_u64_u32 v[5:6], s4, v10, v5, v[3:4]1162; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v11, v4, v[5:6]1163; GFX10-NEXT: s_setpc_b64 s[30:31]1164;1165; GFX11-LABEL: v_mul_i128:1166; GFX11: ; %bb.0:1167; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1168; GFX11-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v9, v11169; GFX11-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v41170; GFX11-NEXT: v_mov_b32_e32 v12, v31171; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v8, v6, 01172; GFX11-NEXT: v_mul_lo_u32 v4, v9, v61173; GFX11-NEXT: v_mul_lo_u32 v6, v8, v71174; GFX11-NEXT: v_mad_u64_u32 v[13:14], null, v9, v5, v[0:1]1175; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v8, v11, 01176; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v10, v11, v[13:14]1177; GFX11-NEXT: v_mad_u64_u32 v[13:14], vcc_lo, v8, v5, v[1:2]1178; GFX11-NEXT: v_mad_u64_u32 v[1:2], s0, v9, v11, v[13:14]1179; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v6, s01180; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v4, vcc_lo1181; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v10, v5, v[3:4]1182; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v12, v11, v[6:7]1183; GFX11-NEXT: s_setpc_b64 s[30:31]1184;1185; GFX12-LABEL: v_mul_i128:1186; GFX12: ; %bb.0:1187; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01188; GFX12-NEXT: s_wait_expcnt 0x01189; GFX12-NEXT: s_wait_samplecnt 0x01190; GFX12-NEXT: s_wait_bvhcnt 0x01191; GFX12-NEXT: s_wait_kmcnt 0x01192; GFX12-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v9, v11193; GFX12-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v31194; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)1195; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v8, v6, 01196; GFX12-NEXT: v_mul_lo_u32 v7, v8, v71197; GFX12-NEXT: v_mul_lo_u32 v6, v9, v61198; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)1199; GFX12-NEXT: v_mad_co_u64_u32 v[12:13], null, v9, v5, v[0:1]1200; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v8, v4, 01201; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, v10, v4, v[12:13]1202; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1203; GFX12-NEXT: v_mad_co_u64_u32 v[12:13], vcc_lo, v8, v5, v[1:2]1204; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], s0, v9, v4, v[12:13]1205; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)1206; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)1207; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, s01208; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)1209; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v6, vcc_lo1210; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1211; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v10, v5, v[3:4]1212; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v11, v4, v[5:6]1213; GFX12-NEXT: s_setpc_b64 s[30:31]1214;1215; GFX1250-LABEL: v_mul_i128:1216; GFX1250: ; %bb.0:1217; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01218; GFX1250-NEXT: s_wait_kmcnt 0x01219; GFX1250-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v9, v11220; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1221; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v8, v6, 01222; GFX1250-NEXT: v_mad_nc_u64_u32 v[10:11], v9, v5, v[0:1]1223; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v8, v4, 01224; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1225; GFX1250-NEXT: v_mad_nc_u64_u32 v[12:13], v2, v4, v[10:11]1226; GFX1250-NEXT: v_mov_b32_e32 v10, v11227; GFX1250-NEXT: v_mul_lo_u32 v1, v9, v61228; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)1229; GFX1250-NEXT: v_mov_b32_e32 v11, v121230; GFX1250-NEXT: v_mad_co_u64_u32 v[14:15], vcc_lo, v8, v5, v[10:11]1231; GFX1250-NEXT: v_mul_lo_u32 v8, v8, v71232; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1233; GFX1250-NEXT: v_mad_co_u64_u32 v[6:7], s0, v9, v4, v[14:15]1234; GFX1250-NEXT: v_add_co_ci_u32_e64 v8, null, v13, v8, s01235; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1236; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v8, v1, vcc_lo1237; GFX1250-NEXT: v_mad_u32 v1, v2, v5, v11238; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)1239; GFX1250-NEXT: v_mov_b32_e32 v2, v71240; GFX1250-NEXT: v_mad_u32 v3, v3, v4, v11241; GFX1250-NEXT: v_mov_b32_e32 v1, v61242; GFX1250-NEXT: s_set_pc_i64 s[30:31]1243 %result = mul i128 %num, %den1244 ret i128 %result1245}1246 1247define amdgpu_ps <8 x i32> @s_mul_i256(i256 inreg %num, i256 inreg %den) {1248; GFX7-LABEL: s_mul_i256:1249; GFX7: ; %bb.0:1250; GFX7-NEXT: s_mov_b32 s16, s01251; GFX7-NEXT: v_mov_b32_e32 v0, s81252; GFX7-NEXT: v_mul_hi_u32 v0, s16, v01253; GFX7-NEXT: v_mov_b32_e32 v1, s91254; GFX7-NEXT: v_mul_hi_u32 v2, s1, v11255; GFX7-NEXT: v_mul_hi_u32 v1, s16, v11256; GFX7-NEXT: v_readfirstlane_b32 s17, v01257; GFX7-NEXT: v_mov_b32_e32 v0, s101258; GFX7-NEXT: v_mul_hi_u32 v0, s16, v01259; GFX7-NEXT: v_readfirstlane_b32 s21, v21260; GFX7-NEXT: v_mov_b32_e32 v2, s21261; GFX7-NEXT: v_mul_hi_u32 v3, v2, s81262; GFX7-NEXT: s_mul_i32 s18, s16, s101263; GFX7-NEXT: s_mul_i32 s20, s1, s91264; GFX7-NEXT: v_readfirstlane_b32 s19, v01265; GFX7-NEXT: v_mov_b32_e32 v0, s11266; GFX7-NEXT: s_add_u32 s18, s20, s181267; GFX7-NEXT: s_addc_u32 s19, s21, s191268; GFX7-NEXT: s_mul_i32 s21, s2, s81269; GFX7-NEXT: v_readfirstlane_b32 s23, v11270; GFX7-NEXT: v_mul_hi_u32 v1, v0, s81271; GFX7-NEXT: s_cselect_b32 s20, 1, 01272; GFX7-NEXT: v_readfirstlane_b32 s22, v31273; GFX7-NEXT: s_add_u32 s18, s21, s181274; GFX7-NEXT: s_addc_u32 s19, s22, s191275; GFX7-NEXT: s_mul_i32 s22, s16, s91276; GFX7-NEXT: s_cselect_b32 s21, 1, 01277; GFX7-NEXT: s_add_u32 s17, s22, s171278; GFX7-NEXT: s_addc_u32 s22, s23, s181279; GFX7-NEXT: v_readfirstlane_b32 s23, v11280; GFX7-NEXT: v_mov_b32_e32 v1, s121281; GFX7-NEXT: v_mul_hi_u32 v3, s16, v11282; GFX7-NEXT: s_mul_i32 s18, s1, s81283; GFX7-NEXT: s_cselect_b32 s25, 1, 01284; GFX7-NEXT: s_add_u32 s18, s18, s171285; GFX7-NEXT: s_addc_u32 s17, s23, s221286; GFX7-NEXT: v_mov_b32_e32 v4, s111287; GFX7-NEXT: v_readfirstlane_b32 s23, v31288; GFX7-NEXT: v_mul_hi_u32 v3, v2, s101289; GFX7-NEXT: v_mul_hi_u32 v5, s1, v41290; GFX7-NEXT: s_mul_i32 s22, s16, s121291; GFX7-NEXT: s_mul_i32 s24, s1, s111292; GFX7-NEXT: v_readfirstlane_b32 s28, v31293; GFX7-NEXT: v_mov_b32_e32 v3, s31294; GFX7-NEXT: v_readfirstlane_b32 s27, v51295; GFX7-NEXT: v_mul_hi_u32 v5, v3, s91296; GFX7-NEXT: s_cselect_b32 s26, 1, 01297; GFX7-NEXT: s_add_u32 s24, s24, s221298; GFX7-NEXT: s_addc_u32 s23, s27, s231299; GFX7-NEXT: v_readfirstlane_b32 s29, v51300; GFX7-NEXT: v_mov_b32_e32 v5, s41301; GFX7-NEXT: v_mul_hi_u32 v6, v5, s81302; GFX7-NEXT: s_mul_i32 s27, s2, s101303; GFX7-NEXT: s_cselect_b32 s22, 1, 01304; GFX7-NEXT: s_add_u32 s24, s27, s241305; GFX7-NEXT: v_mul_hi_u32 v0, v0, s101306; GFX7-NEXT: s_addc_u32 s27, s28, s231307; GFX7-NEXT: s_mul_i32 s28, s3, s91308; GFX7-NEXT: s_cselect_b32 s23, 1, 01309; GFX7-NEXT: s_add_u32 s28, s28, s241310; GFX7-NEXT: v_readfirstlane_b32 s30, v61311; GFX7-NEXT: v_mul_hi_u32 v6, s16, v41312; GFX7-NEXT: s_addc_u32 s27, s29, s271313; GFX7-NEXT: s_mul_i32 s29, s4, s81314; GFX7-NEXT: s_cselect_b32 s24, 1, 01315; GFX7-NEXT: s_add_u32 s28, s29, s281316; GFX7-NEXT: v_readfirstlane_b32 s33, v01317; GFX7-NEXT: v_mul_hi_u32 v0, v2, s91318; GFX7-NEXT: s_addc_u32 s27, s30, s271319; GFX7-NEXT: s_mul_i32 s30, s16, s111320; GFX7-NEXT: s_cselect_b32 s29, 1, 01321; GFX7-NEXT: v_readfirstlane_b32 s31, v61322; GFX7-NEXT: s_add_u32 s19, s30, s191323; GFX7-NEXT: s_addc_u32 s28, s31, s281324; GFX7-NEXT: s_mul_i32 s31, s1, s101325; GFX7-NEXT: s_cselect_b32 s30, 1, 01326; GFX7-NEXT: s_add_u32 s19, s31, s191327; GFX7-NEXT: v_readfirstlane_b32 s34, v01328; GFX7-NEXT: v_mul_hi_u32 v0, v3, s81329; GFX7-NEXT: s_addc_u32 s28, s33, s281330; GFX7-NEXT: s_mul_i32 s33, s2, s91331; GFX7-NEXT: s_cselect_b32 s31, 1, 01332; GFX7-NEXT: s_add_u32 s19, s33, s191333; GFX7-NEXT: s_addc_u32 s28, s34, s281334; GFX7-NEXT: s_mul_i32 s34, s3, s81335; GFX7-NEXT: s_cselect_b32 s33, 1, 01336; GFX7-NEXT: v_readfirstlane_b32 s35, v01337; GFX7-NEXT: s_add_u32 s19, s34, s191338; GFX7-NEXT: v_mov_b32_e32 v0, s141339; GFX7-NEXT: s_addc_u32 s28, s35, s281340; GFX7-NEXT: v_mul_hi_u32 v0, s16, v01341; GFX7-NEXT: s_cselect_b32 s34, 1, 01342; GFX7-NEXT: s_cmp_lg_u32 s26, 01343; GFX7-NEXT: s_addc_u32 s19, s25, s191344; GFX7-NEXT: v_mov_b32_e32 v2, s131345; GFX7-NEXT: s_cselect_b32 s25, 1, 01346; GFX7-NEXT: s_cmp_lg_u32 s21, 01347; GFX7-NEXT: v_mul_hi_u32 v6, s1, v21348; GFX7-NEXT: s_addc_u32 s20, s20, 01349; GFX7-NEXT: v_readfirstlane_b32 s26, v01350; GFX7-NEXT: v_mul_hi_u32 v0, s2, v11351; GFX7-NEXT: s_cmp_lg_u32 s25, 01352; GFX7-NEXT: s_addc_u32 s20, s20, s281353; GFX7-NEXT: s_mul_i32 s25, s16, s141354; GFX7-NEXT: s_mul_i32 s28, s1, s131355; GFX7-NEXT: s_cselect_b32 s21, 1, 01356; GFX7-NEXT: v_readfirstlane_b32 s35, v61357; GFX7-NEXT: s_add_u32 s25, s28, s251358; GFX7-NEXT: s_addc_u32 s26, s35, s261359; GFX7-NEXT: v_readfirstlane_b32 s35, v01360; GFX7-NEXT: v_mul_hi_u32 v0, v3, s111361; GFX7-NEXT: s_mul_i32 s28, s2, s121362; GFX7-NEXT: s_add_u32 s25, s28, s251363; GFX7-NEXT: s_addc_u32 s26, s35, s261364; GFX7-NEXT: v_readfirstlane_b32 s35, v01365; GFX7-NEXT: v_mul_hi_u32 v0, v5, s101366; GFX7-NEXT: s_mul_i32 s28, s3, s111367; GFX7-NEXT: s_add_u32 s25, s28, s251368; GFX7-NEXT: s_addc_u32 s26, s35, s261369; GFX7-NEXT: v_readfirstlane_b32 s35, v01370; GFX7-NEXT: v_mov_b32_e32 v0, s51371; GFX7-NEXT: v_mul_hi_u32 v6, v0, s91372; GFX7-NEXT: s_mul_i32 s28, s4, s101373; GFX7-NEXT: s_add_u32 s25, s28, s251374; GFX7-NEXT: v_mul_hi_u32 v1, s1, v11375; GFX7-NEXT: s_addc_u32 s26, s35, s261376; GFX7-NEXT: v_readfirstlane_b32 s35, v61377; GFX7-NEXT: v_mov_b32_e32 v6, s61378; GFX7-NEXT: v_mul_hi_u32 v6, v6, s81379; GFX7-NEXT: s_mul_i32 s28, s5, s91380; GFX7-NEXT: s_add_u32 s25, s28, s251381; GFX7-NEXT: v_mul_hi_u32 v2, s16, v21382; GFX7-NEXT: v_readfirstlane_b32 s36, v11383; GFX7-NEXT: v_mul_hi_u32 v1, s2, v41384; GFX7-NEXT: s_addc_u32 s26, s35, s261385; GFX7-NEXT: s_mul_i32 s28, s6, s81386; GFX7-NEXT: v_readfirstlane_b32 s35, v61387; GFX7-NEXT: s_add_u32 s25, s28, s251388; GFX7-NEXT: s_addc_u32 s26, s35, s261389; GFX7-NEXT: s_mul_i32 s28, s16, s131390; GFX7-NEXT: v_readfirstlane_b32 s35, v21391; GFX7-NEXT: s_add_u32 s27, s28, s271392; GFX7-NEXT: v_readfirstlane_b32 s37, v11393; GFX7-NEXT: v_mul_hi_u32 v1, v3, s101394; GFX7-NEXT: s_addc_u32 s25, s35, s251395; GFX7-NEXT: s_mul_i32 s35, s1, s121396; GFX7-NEXT: s_cselect_b32 s28, 1, 01397; GFX7-NEXT: s_add_u32 s27, s35, s271398; GFX7-NEXT: s_addc_u32 s25, s36, s251399; GFX7-NEXT: s_mul_i32 s36, s2, s111400; GFX7-NEXT: s_cselect_b32 s35, 1, 01401; GFX7-NEXT: s_add_u32 s27, s36, s271402; GFX7-NEXT: v_readfirstlane_b32 s38, v11403; GFX7-NEXT: v_mul_hi_u32 v1, v5, s91404; GFX7-NEXT: s_addc_u32 s25, s37, s251405; GFX7-NEXT: s_mul_i32 s37, s3, s101406; GFX7-NEXT: s_cselect_b32 s36, 1, 01407; GFX7-NEXT: s_add_u32 s27, s37, s271408; GFX7-NEXT: v_mul_hi_u32 v0, v0, s81409; GFX7-NEXT: s_addc_u32 s25, s38, s251410; GFX7-NEXT: s_mul_i32 s38, s4, s91411; GFX7-NEXT: s_cselect_b32 s37, 1, 01412; GFX7-NEXT: v_readfirstlane_b32 s39, v11413; GFX7-NEXT: s_add_u32 s27, s38, s271414; GFX7-NEXT: s_addc_u32 s25, s39, s251415; GFX7-NEXT: s_mul_i32 s39, s5, s81416; GFX7-NEXT: s_cselect_b32 s38, 1, 01417; GFX7-NEXT: v_readfirstlane_b32 s40, v01418; GFX7-NEXT: s_add_u32 s27, s39, s271419; GFX7-NEXT: s_addc_u32 s25, s40, s251420; GFX7-NEXT: s_cselect_b32 s39, 1, 01421; GFX7-NEXT: s_cmp_lg_u32 s31, 01422; GFX7-NEXT: s_addc_u32 s30, s30, 01423; GFX7-NEXT: s_cmp_lg_u32 s33, 01424; GFX7-NEXT: s_addc_u32 s30, s30, 01425; GFX7-NEXT: s_cmp_lg_u32 s34, 01426; GFX7-NEXT: s_addc_u32 s30, s30, 01427; GFX7-NEXT: s_cmp_lg_u32 s21, 01428; GFX7-NEXT: s_addc_u32 s21, s30, s271429; GFX7-NEXT: s_cselect_b32 s27, 1, 01430; GFX7-NEXT: s_cmp_lg_u32 s23, 01431; GFX7-NEXT: s_addc_u32 s22, s22, 01432; GFX7-NEXT: s_cmp_lg_u32 s24, 01433; GFX7-NEXT: s_addc_u32 s22, s22, 01434; GFX7-NEXT: s_cmp_lg_u32 s29, 01435; GFX7-NEXT: s_addc_u32 s22, s22, 01436; GFX7-NEXT: s_cmp_lg_u32 s27, 01437; GFX7-NEXT: s_addc_u32 s22, s22, s251438; GFX7-NEXT: s_mul_i32 s16, s16, s151439; GFX7-NEXT: s_addc_u32 s15, s26, s161440; GFX7-NEXT: s_mul_i32 s1, s1, s141441; GFX7-NEXT: s_cmp_lg_u32 s39, 01442; GFX7-NEXT: s_addc_u32 s1, s15, s11443; GFX7-NEXT: s_mul_i32 s2, s2, s131444; GFX7-NEXT: s_cmp_lg_u32 s38, 01445; GFX7-NEXT: s_addc_u32 s1, s1, s21446; GFX7-NEXT: s_mul_i32 s3, s3, s121447; GFX7-NEXT: s_cmp_lg_u32 s37, 01448; GFX7-NEXT: s_addc_u32 s1, s1, s31449; GFX7-NEXT: s_mul_i32 s4, s4, s111450; GFX7-NEXT: s_cmp_lg_u32 s36, 01451; GFX7-NEXT: s_addc_u32 s1, s1, s41452; GFX7-NEXT: s_mul_i32 s5, s5, s101453; GFX7-NEXT: s_cmp_lg_u32 s35, 01454; GFX7-NEXT: s_addc_u32 s1, s1, s51455; GFX7-NEXT: s_mul_i32 s6, s6, s91456; GFX7-NEXT: s_cmp_lg_u32 s28, 01457; GFX7-NEXT: s_addc_u32 s1, s1, s61458; GFX7-NEXT: s_mul_i32 s7, s7, s81459; GFX7-NEXT: s_mul_i32 s0, s0, s81460; GFX7-NEXT: s_add_u32 s7, s7, s11461; GFX7-NEXT: s_mov_b32 s1, s181462; GFX7-NEXT: s_mov_b32 s2, s171463; GFX7-NEXT: s_mov_b32 s3, s191464; GFX7-NEXT: s_mov_b32 s4, s201465; GFX7-NEXT: s_mov_b32 s5, s211466; GFX7-NEXT: s_mov_b32 s6, s221467; GFX7-NEXT: ; return to shader part epilog1468;1469; GFX8-LABEL: s_mul_i256:1470; GFX8: ; %bb.0:1471; GFX8-NEXT: s_mov_b32 s16, s01472; GFX8-NEXT: v_mov_b32_e32 v0, s81473; GFX8-NEXT: v_mul_hi_u32 v0, s16, v01474; GFX8-NEXT: v_mov_b32_e32 v1, s91475; GFX8-NEXT: v_mul_hi_u32 v2, s1, v11476; GFX8-NEXT: v_mul_hi_u32 v1, s16, v11477; GFX8-NEXT: v_readfirstlane_b32 s17, v01478; GFX8-NEXT: v_mov_b32_e32 v0, s101479; GFX8-NEXT: v_mul_hi_u32 v0, s16, v01480; GFX8-NEXT: v_readfirstlane_b32 s21, v21481; GFX8-NEXT: v_mov_b32_e32 v2, s21482; GFX8-NEXT: v_mul_hi_u32 v3, v2, s81483; GFX8-NEXT: s_mul_i32 s18, s16, s101484; GFX8-NEXT: s_mul_i32 s20, s1, s91485; GFX8-NEXT: v_readfirstlane_b32 s19, v01486; GFX8-NEXT: v_mov_b32_e32 v0, s11487; GFX8-NEXT: s_add_u32 s18, s20, s181488; GFX8-NEXT: s_addc_u32 s19, s21, s191489; GFX8-NEXT: s_mul_i32 s21, s2, s81490; GFX8-NEXT: v_readfirstlane_b32 s23, v11491; GFX8-NEXT: v_mul_hi_u32 v1, v0, s81492; GFX8-NEXT: s_cselect_b32 s20, 1, 01493; GFX8-NEXT: v_readfirstlane_b32 s22, v31494; GFX8-NEXT: s_add_u32 s18, s21, s181495; GFX8-NEXT: s_addc_u32 s19, s22, s191496; GFX8-NEXT: s_mul_i32 s22, s16, s91497; GFX8-NEXT: s_cselect_b32 s21, 1, 01498; GFX8-NEXT: s_add_u32 s17, s22, s171499; GFX8-NEXT: s_addc_u32 s22, s23, s181500; GFX8-NEXT: v_readfirstlane_b32 s23, v11501; GFX8-NEXT: v_mov_b32_e32 v1, s121502; GFX8-NEXT: v_mul_hi_u32 v3, s16, v11503; GFX8-NEXT: s_mul_i32 s18, s1, s81504; GFX8-NEXT: s_cselect_b32 s25, 1, 01505; GFX8-NEXT: s_add_u32 s18, s18, s171506; GFX8-NEXT: s_addc_u32 s17, s23, s221507; GFX8-NEXT: v_mov_b32_e32 v4, s111508; GFX8-NEXT: v_readfirstlane_b32 s23, v31509; GFX8-NEXT: v_mul_hi_u32 v3, v2, s101510; GFX8-NEXT: v_mul_hi_u32 v5, s1, v41511; GFX8-NEXT: s_mul_i32 s22, s16, s121512; GFX8-NEXT: s_mul_i32 s24, s1, s111513; GFX8-NEXT: v_readfirstlane_b32 s28, v31514; GFX8-NEXT: v_mov_b32_e32 v3, s31515; GFX8-NEXT: v_readfirstlane_b32 s27, v51516; GFX8-NEXT: v_mul_hi_u32 v5, v3, s91517; GFX8-NEXT: s_cselect_b32 s26, 1, 01518; GFX8-NEXT: s_add_u32 s24, s24, s221519; GFX8-NEXT: s_addc_u32 s23, s27, s231520; GFX8-NEXT: v_readfirstlane_b32 s29, v51521; GFX8-NEXT: v_mov_b32_e32 v5, s41522; GFX8-NEXT: v_mul_hi_u32 v6, v5, s81523; GFX8-NEXT: s_mul_i32 s27, s2, s101524; GFX8-NEXT: s_cselect_b32 s22, 1, 01525; GFX8-NEXT: s_add_u32 s24, s27, s241526; GFX8-NEXT: v_mul_hi_u32 v0, v0, s101527; GFX8-NEXT: s_addc_u32 s27, s28, s231528; GFX8-NEXT: s_mul_i32 s28, s3, s91529; GFX8-NEXT: s_cselect_b32 s23, 1, 01530; GFX8-NEXT: s_add_u32 s28, s28, s241531; GFX8-NEXT: v_readfirstlane_b32 s30, v61532; GFX8-NEXT: v_mul_hi_u32 v6, s16, v41533; GFX8-NEXT: s_addc_u32 s27, s29, s271534; GFX8-NEXT: s_mul_i32 s29, s4, s81535; GFX8-NEXT: s_cselect_b32 s24, 1, 01536; GFX8-NEXT: s_add_u32 s28, s29, s281537; GFX8-NEXT: v_readfirstlane_b32 s33, v01538; GFX8-NEXT: v_mul_hi_u32 v0, v2, s91539; GFX8-NEXT: s_addc_u32 s27, s30, s271540; GFX8-NEXT: s_mul_i32 s30, s16, s111541; GFX8-NEXT: s_cselect_b32 s29, 1, 01542; GFX8-NEXT: v_readfirstlane_b32 s31, v61543; GFX8-NEXT: s_add_u32 s19, s30, s191544; GFX8-NEXT: s_addc_u32 s28, s31, s281545; GFX8-NEXT: s_mul_i32 s31, s1, s101546; GFX8-NEXT: s_cselect_b32 s30, 1, 01547; GFX8-NEXT: s_add_u32 s19, s31, s191548; GFX8-NEXT: v_readfirstlane_b32 s34, v01549; GFX8-NEXT: v_mul_hi_u32 v0, v3, s81550; GFX8-NEXT: s_addc_u32 s28, s33, s281551; GFX8-NEXT: s_mul_i32 s33, s2, s91552; GFX8-NEXT: s_cselect_b32 s31, 1, 01553; GFX8-NEXT: s_add_u32 s19, s33, s191554; GFX8-NEXT: s_addc_u32 s28, s34, s281555; GFX8-NEXT: s_mul_i32 s34, s3, s81556; GFX8-NEXT: s_cselect_b32 s33, 1, 01557; GFX8-NEXT: v_readfirstlane_b32 s35, v01558; GFX8-NEXT: s_add_u32 s19, s34, s191559; GFX8-NEXT: v_mov_b32_e32 v0, s141560; GFX8-NEXT: s_addc_u32 s28, s35, s281561; GFX8-NEXT: v_mul_hi_u32 v0, s16, v01562; GFX8-NEXT: s_cselect_b32 s34, 1, 01563; GFX8-NEXT: s_cmp_lg_u32 s26, 01564; GFX8-NEXT: s_addc_u32 s19, s25, s191565; GFX8-NEXT: v_mov_b32_e32 v2, s131566; GFX8-NEXT: s_cselect_b32 s25, 1, 01567; GFX8-NEXT: s_cmp_lg_u32 s21, 01568; GFX8-NEXT: v_mul_hi_u32 v6, s1, v21569; GFX8-NEXT: s_addc_u32 s20, s20, 01570; GFX8-NEXT: v_readfirstlane_b32 s26, v01571; GFX8-NEXT: v_mul_hi_u32 v0, s2, v11572; GFX8-NEXT: s_cmp_lg_u32 s25, 01573; GFX8-NEXT: s_addc_u32 s20, s20, s281574; GFX8-NEXT: s_mul_i32 s25, s16, s141575; GFX8-NEXT: s_mul_i32 s28, s1, s131576; GFX8-NEXT: s_cselect_b32 s21, 1, 01577; GFX8-NEXT: v_readfirstlane_b32 s35, v61578; GFX8-NEXT: s_add_u32 s25, s28, s251579; GFX8-NEXT: s_addc_u32 s26, s35, s261580; GFX8-NEXT: v_readfirstlane_b32 s35, v01581; GFX8-NEXT: v_mul_hi_u32 v0, v3, s111582; GFX8-NEXT: s_mul_i32 s28, s2, s121583; GFX8-NEXT: s_add_u32 s25, s28, s251584; GFX8-NEXT: s_addc_u32 s26, s35, s261585; GFX8-NEXT: v_readfirstlane_b32 s35, v01586; GFX8-NEXT: v_mul_hi_u32 v0, v5, s101587; GFX8-NEXT: s_mul_i32 s28, s3, s111588; GFX8-NEXT: s_add_u32 s25, s28, s251589; GFX8-NEXT: s_addc_u32 s26, s35, s261590; GFX8-NEXT: v_readfirstlane_b32 s35, v01591; GFX8-NEXT: v_mov_b32_e32 v0, s51592; GFX8-NEXT: v_mul_hi_u32 v6, v0, s91593; GFX8-NEXT: s_mul_i32 s28, s4, s101594; GFX8-NEXT: s_add_u32 s25, s28, s251595; GFX8-NEXT: v_mul_hi_u32 v1, s1, v11596; GFX8-NEXT: s_addc_u32 s26, s35, s261597; GFX8-NEXT: v_readfirstlane_b32 s35, v61598; GFX8-NEXT: v_mov_b32_e32 v6, s61599; GFX8-NEXT: v_mul_hi_u32 v6, v6, s81600; GFX8-NEXT: s_mul_i32 s28, s5, s91601; GFX8-NEXT: s_add_u32 s25, s28, s251602; GFX8-NEXT: v_mul_hi_u32 v2, s16, v21603; GFX8-NEXT: v_readfirstlane_b32 s36, v11604; GFX8-NEXT: v_mul_hi_u32 v1, s2, v41605; GFX8-NEXT: s_addc_u32 s26, s35, s261606; GFX8-NEXT: s_mul_i32 s28, s6, s81607; GFX8-NEXT: v_readfirstlane_b32 s35, v61608; GFX8-NEXT: s_add_u32 s25, s28, s251609; GFX8-NEXT: s_addc_u32 s26, s35, s261610; GFX8-NEXT: s_mul_i32 s28, s16, s131611; GFX8-NEXT: v_readfirstlane_b32 s35, v21612; GFX8-NEXT: s_add_u32 s27, s28, s271613; GFX8-NEXT: v_readfirstlane_b32 s37, v11614; GFX8-NEXT: v_mul_hi_u32 v1, v3, s101615; GFX8-NEXT: s_addc_u32 s25, s35, s251616; GFX8-NEXT: s_mul_i32 s35, s1, s121617; GFX8-NEXT: s_cselect_b32 s28, 1, 01618; GFX8-NEXT: s_add_u32 s27, s35, s271619; GFX8-NEXT: s_addc_u32 s25, s36, s251620; GFX8-NEXT: s_mul_i32 s36, s2, s111621; GFX8-NEXT: s_cselect_b32 s35, 1, 01622; GFX8-NEXT: s_add_u32 s27, s36, s271623; GFX8-NEXT: v_readfirstlane_b32 s38, v11624; GFX8-NEXT: v_mul_hi_u32 v1, v5, s91625; GFX8-NEXT: s_addc_u32 s25, s37, s251626; GFX8-NEXT: s_mul_i32 s37, s3, s101627; GFX8-NEXT: s_cselect_b32 s36, 1, 01628; GFX8-NEXT: s_add_u32 s27, s37, s271629; GFX8-NEXT: v_mul_hi_u32 v0, v0, s81630; GFX8-NEXT: s_addc_u32 s25, s38, s251631; GFX8-NEXT: s_mul_i32 s38, s4, s91632; GFX8-NEXT: s_cselect_b32 s37, 1, 01633; GFX8-NEXT: v_readfirstlane_b32 s39, v11634; GFX8-NEXT: s_add_u32 s27, s38, s271635; GFX8-NEXT: s_addc_u32 s25, s39, s251636; GFX8-NEXT: s_mul_i32 s39, s5, s81637; GFX8-NEXT: s_cselect_b32 s38, 1, 01638; GFX8-NEXT: v_readfirstlane_b32 s40, v01639; GFX8-NEXT: s_add_u32 s27, s39, s271640; GFX8-NEXT: s_addc_u32 s25, s40, s251641; GFX8-NEXT: s_cselect_b32 s39, 1, 01642; GFX8-NEXT: s_cmp_lg_u32 s31, 01643; GFX8-NEXT: s_addc_u32 s30, s30, 01644; GFX8-NEXT: s_cmp_lg_u32 s33, 01645; GFX8-NEXT: s_addc_u32 s30, s30, 01646; GFX8-NEXT: s_cmp_lg_u32 s34, 01647; GFX8-NEXT: s_addc_u32 s30, s30, 01648; GFX8-NEXT: s_cmp_lg_u32 s21, 01649; GFX8-NEXT: s_addc_u32 s21, s30, s271650; GFX8-NEXT: s_cselect_b32 s27, 1, 01651; GFX8-NEXT: s_cmp_lg_u32 s23, 01652; GFX8-NEXT: s_addc_u32 s22, s22, 01653; GFX8-NEXT: s_cmp_lg_u32 s24, 01654; GFX8-NEXT: s_addc_u32 s22, s22, 01655; GFX8-NEXT: s_cmp_lg_u32 s29, 01656; GFX8-NEXT: s_addc_u32 s22, s22, 01657; GFX8-NEXT: s_cmp_lg_u32 s27, 01658; GFX8-NEXT: s_addc_u32 s22, s22, s251659; GFX8-NEXT: s_mul_i32 s16, s16, s151660; GFX8-NEXT: s_addc_u32 s15, s26, s161661; GFX8-NEXT: s_mul_i32 s1, s1, s141662; GFX8-NEXT: s_cmp_lg_u32 s39, 01663; GFX8-NEXT: s_addc_u32 s1, s15, s11664; GFX8-NEXT: s_mul_i32 s2, s2, s131665; GFX8-NEXT: s_cmp_lg_u32 s38, 01666; GFX8-NEXT: s_addc_u32 s1, s1, s21667; GFX8-NEXT: s_mul_i32 s3, s3, s121668; GFX8-NEXT: s_cmp_lg_u32 s37, 01669; GFX8-NEXT: s_addc_u32 s1, s1, s31670; GFX8-NEXT: s_mul_i32 s4, s4, s111671; GFX8-NEXT: s_cmp_lg_u32 s36, 01672; GFX8-NEXT: s_addc_u32 s1, s1, s41673; GFX8-NEXT: s_mul_i32 s5, s5, s101674; GFX8-NEXT: s_cmp_lg_u32 s35, 01675; GFX8-NEXT: s_addc_u32 s1, s1, s51676; GFX8-NEXT: s_mul_i32 s6, s6, s91677; GFX8-NEXT: s_cmp_lg_u32 s28, 01678; GFX8-NEXT: s_addc_u32 s1, s1, s61679; GFX8-NEXT: s_mul_i32 s7, s7, s81680; GFX8-NEXT: s_mul_i32 s0, s0, s81681; GFX8-NEXT: s_add_u32 s7, s7, s11682; GFX8-NEXT: s_mov_b32 s1, s181683; GFX8-NEXT: s_mov_b32 s2, s171684; GFX8-NEXT: s_mov_b32 s3, s191685; GFX8-NEXT: s_mov_b32 s4, s201686; GFX8-NEXT: s_mov_b32 s5, s211687; GFX8-NEXT: s_mov_b32 s6, s221688; GFX8-NEXT: ; return to shader part epilog1689;1690; GFX9-LABEL: s_mul_i256:1691; GFX9: ; %bb.0:1692; GFX9-NEXT: s_mov_b32 s16, s01693; GFX9-NEXT: s_mul_i32 s18, s16, s101694; GFX9-NEXT: s_mul_i32 s20, s1, s91695; GFX9-NEXT: s_mul_hi_u32 s19, s16, s101696; GFX9-NEXT: s_mul_hi_u32 s21, s1, s91697; GFX9-NEXT: s_add_u32 s18, s20, s181698; GFX9-NEXT: s_addc_u32 s19, s21, s191699; GFX9-NEXT: s_mul_i32 s21, s2, s81700; GFX9-NEXT: s_cselect_b32 s20, 1, 01701; GFX9-NEXT: s_mul_hi_u32 s22, s2, s81702; GFX9-NEXT: s_add_u32 s18, s21, s181703; GFX9-NEXT: s_mul_hi_u32 s17, s16, s81704; GFX9-NEXT: s_addc_u32 s19, s22, s191705; GFX9-NEXT: s_mul_i32 s22, s16, s91706; GFX9-NEXT: s_cselect_b32 s21, 1, 01707; GFX9-NEXT: s_mul_hi_u32 s23, s16, s91708; GFX9-NEXT: s_add_u32 s17, s22, s171709; GFX9-NEXT: s_addc_u32 s18, s23, s181710; GFX9-NEXT: s_mul_i32 s23, s1, s81711; GFX9-NEXT: s_cselect_b32 s22, 1, 01712; GFX9-NEXT: s_mul_hi_u32 s24, s1, s81713; GFX9-NEXT: s_add_u32 s17, s23, s171714; GFX9-NEXT: s_addc_u32 s18, s24, s181715; GFX9-NEXT: s_mul_i32 s24, s16, s121716; GFX9-NEXT: s_mul_i32 s26, s1, s111717; GFX9-NEXT: s_cselect_b32 s23, 1, 01718; GFX9-NEXT: s_mul_hi_u32 s25, s16, s121719; GFX9-NEXT: s_mul_hi_u32 s27, s1, s111720; GFX9-NEXT: s_add_u32 s24, s26, s241721; GFX9-NEXT: s_addc_u32 s25, s27, s251722; GFX9-NEXT: s_mul_i32 s27, s2, s101723; GFX9-NEXT: s_cselect_b32 s26, 1, 01724; GFX9-NEXT: s_mul_hi_u32 s28, s2, s101725; GFX9-NEXT: s_add_u32 s24, s27, s241726; GFX9-NEXT: s_addc_u32 s25, s28, s251727; GFX9-NEXT: s_mul_i32 s28, s3, s91728; GFX9-NEXT: s_cselect_b32 s27, 1, 01729; GFX9-NEXT: s_mul_hi_u32 s29, s3, s91730; GFX9-NEXT: s_add_u32 s24, s28, s241731; GFX9-NEXT: s_addc_u32 s25, s29, s251732; GFX9-NEXT: s_mul_i32 s29, s4, s81733; GFX9-NEXT: s_cselect_b32 s28, 1, 01734; GFX9-NEXT: s_mul_hi_u32 s30, s4, s81735; GFX9-NEXT: s_add_u32 s24, s29, s241736; GFX9-NEXT: s_addc_u32 s25, s30, s251737; GFX9-NEXT: s_mul_i32 s30, s16, s111738; GFX9-NEXT: s_cselect_b32 s29, 1, 01739; GFX9-NEXT: s_mul_hi_u32 s31, s16, s111740; GFX9-NEXT: s_add_u32 s19, s30, s191741; GFX9-NEXT: s_addc_u32 s24, s31, s241742; GFX9-NEXT: s_mul_i32 s31, s1, s101743; GFX9-NEXT: s_cselect_b32 s30, 1, 01744; GFX9-NEXT: s_mul_hi_u32 s33, s1, s101745; GFX9-NEXT: s_add_u32 s19, s31, s191746; GFX9-NEXT: s_addc_u32 s24, s33, s241747; GFX9-NEXT: s_mul_i32 s33, s2, s91748; GFX9-NEXT: s_cselect_b32 s31, 1, 01749; GFX9-NEXT: s_mul_hi_u32 s34, s2, s91750; GFX9-NEXT: s_add_u32 s19, s33, s191751; GFX9-NEXT: s_addc_u32 s24, s34, s241752; GFX9-NEXT: s_mul_i32 s34, s3, s81753; GFX9-NEXT: s_cselect_b32 s33, 1, 01754; GFX9-NEXT: s_mul_hi_u32 s35, s3, s81755; GFX9-NEXT: s_add_u32 s19, s34, s191756; GFX9-NEXT: s_addc_u32 s24, s35, s241757; GFX9-NEXT: s_cselect_b32 s34, 1, 01758; GFX9-NEXT: s_cmp_lg_u32 s23, 01759; GFX9-NEXT: s_addc_u32 s19, s22, s191760; GFX9-NEXT: s_cselect_b32 s22, 1, 01761; GFX9-NEXT: s_cmp_lg_u32 s21, 01762; GFX9-NEXT: s_addc_u32 s20, s20, 01763; GFX9-NEXT: s_cmp_lg_u32 s22, 01764; GFX9-NEXT: s_addc_u32 s20, s20, s241765; GFX9-NEXT: s_mul_i32 s22, s16, s141766; GFX9-NEXT: s_mul_i32 s24, s1, s131767; GFX9-NEXT: s_cselect_b32 s21, 1, 01768; GFX9-NEXT: s_mul_hi_u32 s23, s16, s141769; GFX9-NEXT: s_mul_hi_u32 s35, s1, s131770; GFX9-NEXT: s_add_u32 s22, s24, s221771; GFX9-NEXT: s_addc_u32 s23, s35, s231772; GFX9-NEXT: s_mul_i32 s24, s2, s121773; GFX9-NEXT: s_mul_hi_u32 s35, s2, s121774; GFX9-NEXT: s_add_u32 s22, s24, s221775; GFX9-NEXT: s_addc_u32 s23, s35, s231776; GFX9-NEXT: s_mul_i32 s24, s3, s111777; GFX9-NEXT: s_mul_hi_u32 s35, s3, s111778; GFX9-NEXT: s_add_u32 s22, s24, s221779; GFX9-NEXT: s_addc_u32 s23, s35, s231780; GFX9-NEXT: s_mul_i32 s24, s4, s101781; GFX9-NEXT: s_mul_hi_u32 s35, s4, s101782; GFX9-NEXT: s_add_u32 s22, s24, s221783; GFX9-NEXT: s_addc_u32 s23, s35, s231784; GFX9-NEXT: s_mul_i32 s24, s5, s91785; GFX9-NEXT: s_mul_hi_u32 s35, s5, s91786; GFX9-NEXT: s_add_u32 s22, s24, s221787; GFX9-NEXT: s_addc_u32 s23, s35, s231788; GFX9-NEXT: s_mul_i32 s24, s6, s81789; GFX9-NEXT: s_mul_hi_u32 s35, s6, s81790; GFX9-NEXT: s_add_u32 s22, s24, s221791; GFX9-NEXT: s_addc_u32 s23, s35, s231792; GFX9-NEXT: s_mul_i32 s24, s16, s131793; GFX9-NEXT: s_mul_hi_u32 s35, s16, s131794; GFX9-NEXT: s_add_u32 s24, s24, s251795; GFX9-NEXT: s_addc_u32 s22, s35, s221796; GFX9-NEXT: s_mul_i32 s35, s1, s121797; GFX9-NEXT: s_cselect_b32 s25, 1, 01798; GFX9-NEXT: s_mul_hi_u32 s36, s1, s121799; GFX9-NEXT: s_add_u32 s24, s35, s241800; GFX9-NEXT: s_addc_u32 s22, s36, s221801; GFX9-NEXT: s_mul_i32 s36, s2, s111802; GFX9-NEXT: s_cselect_b32 s35, 1, 01803; GFX9-NEXT: s_mul_hi_u32 s37, s2, s111804; GFX9-NEXT: s_add_u32 s24, s36, s241805; GFX9-NEXT: s_addc_u32 s22, s37, s221806; GFX9-NEXT: s_mul_i32 s37, s3, s101807; GFX9-NEXT: s_cselect_b32 s36, 1, 01808; GFX9-NEXT: s_mul_hi_u32 s38, s3, s101809; GFX9-NEXT: s_add_u32 s24, s37, s241810; GFX9-NEXT: s_addc_u32 s22, s38, s221811; GFX9-NEXT: s_mul_i32 s38, s4, s91812; GFX9-NEXT: s_cselect_b32 s37, 1, 01813; GFX9-NEXT: s_mul_hi_u32 s39, s4, s91814; GFX9-NEXT: s_add_u32 s24, s38, s241815; GFX9-NEXT: s_addc_u32 s22, s39, s221816; GFX9-NEXT: s_mul_i32 s39, s5, s81817; GFX9-NEXT: s_cselect_b32 s38, 1, 01818; GFX9-NEXT: s_mul_hi_u32 s40, s5, s81819; GFX9-NEXT: s_add_u32 s24, s39, s241820; GFX9-NEXT: s_addc_u32 s22, s40, s221821; GFX9-NEXT: s_cselect_b32 s39, 1, 01822; GFX9-NEXT: s_cmp_lg_u32 s31, 01823; GFX9-NEXT: s_addc_u32 s30, s30, 01824; GFX9-NEXT: s_cmp_lg_u32 s33, 01825; GFX9-NEXT: s_addc_u32 s30, s30, 01826; GFX9-NEXT: s_cmp_lg_u32 s34, 01827; GFX9-NEXT: s_addc_u32 s30, s30, 01828; GFX9-NEXT: s_cmp_lg_u32 s21, 01829; GFX9-NEXT: s_addc_u32 s21, s30, s241830; GFX9-NEXT: s_cselect_b32 s24, 1, 01831; GFX9-NEXT: s_cmp_lg_u32 s27, 01832; GFX9-NEXT: s_addc_u32 s26, s26, 01833; GFX9-NEXT: s_cmp_lg_u32 s28, 01834; GFX9-NEXT: s_addc_u32 s26, s26, 01835; GFX9-NEXT: s_cmp_lg_u32 s29, 01836; GFX9-NEXT: s_addc_u32 s26, s26, 01837; GFX9-NEXT: s_cmp_lg_u32 s24, 01838; GFX9-NEXT: s_addc_u32 s22, s26, s221839; GFX9-NEXT: s_mul_i32 s16, s16, s151840; GFX9-NEXT: s_addc_u32 s15, s23, s161841; GFX9-NEXT: s_mul_i32 s1, s1, s141842; GFX9-NEXT: s_cmp_lg_u32 s39, 01843; GFX9-NEXT: s_addc_u32 s1, s15, s11844; GFX9-NEXT: s_mul_i32 s2, s2, s131845; GFX9-NEXT: s_cmp_lg_u32 s38, 01846; GFX9-NEXT: s_addc_u32 s1, s1, s21847; GFX9-NEXT: s_mul_i32 s3, s3, s121848; GFX9-NEXT: s_cmp_lg_u32 s37, 01849; GFX9-NEXT: s_addc_u32 s1, s1, s31850; GFX9-NEXT: s_mul_i32 s4, s4, s111851; GFX9-NEXT: s_cmp_lg_u32 s36, 01852; GFX9-NEXT: s_addc_u32 s1, s1, s41853; GFX9-NEXT: s_mul_i32 s5, s5, s101854; GFX9-NEXT: s_cmp_lg_u32 s35, 01855; GFX9-NEXT: s_addc_u32 s1, s1, s51856; GFX9-NEXT: s_mul_i32 s6, s6, s91857; GFX9-NEXT: s_cmp_lg_u32 s25, 01858; GFX9-NEXT: s_addc_u32 s1, s1, s61859; GFX9-NEXT: s_mul_i32 s7, s7, s81860; GFX9-NEXT: s_mul_i32 s0, s0, s81861; GFX9-NEXT: s_add_u32 s7, s7, s11862; GFX9-NEXT: s_mov_b32 s1, s171863; GFX9-NEXT: s_mov_b32 s2, s181864; GFX9-NEXT: s_mov_b32 s3, s191865; GFX9-NEXT: s_mov_b32 s4, s201866; GFX9-NEXT: s_mov_b32 s5, s211867; GFX9-NEXT: s_mov_b32 s6, s221868; GFX9-NEXT: ; return to shader part epilog1869;1870; GFX10PLUS-LABEL: s_mul_i256:1871; GFX10PLUS: ; %bb.0:1872; GFX10PLUS-NEXT: s_mul_i32 s17, s0, s101873; GFX10PLUS-NEXT: s_mul_i32 s19, s1, s91874; GFX10PLUS-NEXT: s_mul_hi_u32 s18, s0, s101875; GFX10PLUS-NEXT: s_mul_hi_u32 s20, s1, s91876; GFX10PLUS-NEXT: s_add_u32 s17, s19, s171877; GFX10PLUS-NEXT: s_addc_u32 s18, s20, s181878; GFX10PLUS-NEXT: s_mul_i32 s20, s2, s81879; GFX10PLUS-NEXT: s_mul_hi_u32 s21, s2, s81880; GFX10PLUS-NEXT: s_cselect_b32 s19, 1, 01881; GFX10PLUS-NEXT: s_add_u32 s17, s20, s171882; GFX10PLUS-NEXT: s_mul_hi_u32 s16, s0, s81883; GFX10PLUS-NEXT: s_addc_u32 s18, s21, s181884; GFX10PLUS-NEXT: s_mul_i32 s21, s0, s91885; GFX10PLUS-NEXT: s_mul_hi_u32 s22, s0, s91886; GFX10PLUS-NEXT: s_cselect_b32 s20, 1, 01887; GFX10PLUS-NEXT: s_add_u32 s16, s21, s161888; GFX10PLUS-NEXT: s_addc_u32 s17, s22, s171889; GFX10PLUS-NEXT: s_mul_i32 s22, s1, s81890; GFX10PLUS-NEXT: s_mul_hi_u32 s23, s1, s81891; GFX10PLUS-NEXT: s_cselect_b32 s21, 1, 01892; GFX10PLUS-NEXT: s_add_u32 s16, s22, s161893; GFX10PLUS-NEXT: s_addc_u32 s17, s23, s171894; GFX10PLUS-NEXT: s_mul_i32 s23, s0, s121895; GFX10PLUS-NEXT: s_mul_i32 s25, s1, s111896; GFX10PLUS-NEXT: s_mul_hi_u32 s24, s0, s121897; GFX10PLUS-NEXT: s_mul_hi_u32 s26, s1, s111898; GFX10PLUS-NEXT: s_cselect_b32 s22, 1, 01899; GFX10PLUS-NEXT: s_add_u32 s23, s25, s231900; GFX10PLUS-NEXT: s_addc_u32 s24, s26, s241901; GFX10PLUS-NEXT: s_mul_i32 s26, s2, s101902; GFX10PLUS-NEXT: s_mul_hi_u32 s27, s2, s101903; GFX10PLUS-NEXT: s_cselect_b32 s25, 1, 01904; GFX10PLUS-NEXT: s_add_u32 s23, s26, s231905; GFX10PLUS-NEXT: s_addc_u32 s24, s27, s241906; GFX10PLUS-NEXT: s_mul_i32 s27, s3, s91907; GFX10PLUS-NEXT: s_mul_hi_u32 s28, s3, s91908; GFX10PLUS-NEXT: s_cselect_b32 s26, 1, 01909; GFX10PLUS-NEXT: s_add_u32 s23, s27, s231910; GFX10PLUS-NEXT: s_addc_u32 s24, s28, s241911; GFX10PLUS-NEXT: s_mul_i32 s28, s4, s81912; GFX10PLUS-NEXT: s_mul_hi_u32 s29, s4, s81913; GFX10PLUS-NEXT: s_cselect_b32 s27, 1, 01914; GFX10PLUS-NEXT: s_add_u32 s23, s28, s231915; GFX10PLUS-NEXT: s_addc_u32 s24, s29, s241916; GFX10PLUS-NEXT: s_mul_i32 s29, s0, s111917; GFX10PLUS-NEXT: s_mul_hi_u32 s30, s0, s111918; GFX10PLUS-NEXT: s_cselect_b32 s28, 1, 01919; GFX10PLUS-NEXT: s_add_u32 s18, s29, s181920; GFX10PLUS-NEXT: s_addc_u32 s23, s30, s231921; GFX10PLUS-NEXT: s_mul_i32 s30, s1, s101922; GFX10PLUS-NEXT: s_mul_hi_u32 s31, s1, s101923; GFX10PLUS-NEXT: s_cselect_b32 s29, 1, 01924; GFX10PLUS-NEXT: s_add_u32 s18, s30, s181925; GFX10PLUS-NEXT: s_addc_u32 s23, s31, s231926; GFX10PLUS-NEXT: s_mul_i32 s31, s2, s91927; GFX10PLUS-NEXT: s_mul_hi_u32 s33, s2, s91928; GFX10PLUS-NEXT: s_cselect_b32 s30, 1, 01929; GFX10PLUS-NEXT: s_add_u32 s18, s31, s181930; GFX10PLUS-NEXT: s_addc_u32 s23, s33, s231931; GFX10PLUS-NEXT: s_mul_i32 s33, s3, s81932; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s3, s81933; GFX10PLUS-NEXT: s_cselect_b32 s31, 1, 01934; GFX10PLUS-NEXT: s_add_u32 s18, s33, s181935; GFX10PLUS-NEXT: s_addc_u32 s23, s34, s231936; GFX10PLUS-NEXT: s_cselect_b32 s33, 1, 01937; GFX10PLUS-NEXT: s_cmp_lg_u32 s22, 01938; GFX10PLUS-NEXT: s_mul_hi_u32 s22, s0, s141939; GFX10PLUS-NEXT: s_addc_u32 s18, s21, s181940; GFX10PLUS-NEXT: s_cselect_b32 s21, 1, 01941; GFX10PLUS-NEXT: s_cmp_lg_u32 s20, 01942; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s1, s131943; GFX10PLUS-NEXT: s_addc_u32 s19, s19, 01944; GFX10PLUS-NEXT: s_cmp_lg_u32 s21, 01945; GFX10PLUS-NEXT: s_mul_i32 s21, s0, s141946; GFX10PLUS-NEXT: s_addc_u32 s19, s19, s231947; GFX10PLUS-NEXT: s_mul_i32 s23, s1, s131948; GFX10PLUS-NEXT: s_cselect_b32 s20, 1, 01949; GFX10PLUS-NEXT: s_add_u32 s21, s23, s211950; GFX10PLUS-NEXT: s_mul_i32 s23, s2, s121951; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s221952; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s2, s121953; GFX10PLUS-NEXT: s_add_u32 s21, s23, s211954; GFX10PLUS-NEXT: s_mul_i32 s23, s3, s111955; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s221956; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s3, s111957; GFX10PLUS-NEXT: s_add_u32 s21, s23, s211958; GFX10PLUS-NEXT: s_mul_i32 s23, s4, s101959; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s221960; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s4, s101961; GFX10PLUS-NEXT: s_add_u32 s21, s23, s211962; GFX10PLUS-NEXT: s_mul_i32 s23, s5, s91963; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s221964; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s5, s91965; GFX10PLUS-NEXT: s_add_u32 s21, s23, s211966; GFX10PLUS-NEXT: s_mul_i32 s23, s6, s81967; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s221968; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s6, s81969; GFX10PLUS-NEXT: s_add_u32 s21, s23, s211970; GFX10PLUS-NEXT: s_mul_i32 s23, s0, s131971; GFX10PLUS-NEXT: s_addc_u32 s22, s34, s221972; GFX10PLUS-NEXT: s_mul_hi_u32 s34, s0, s131973; GFX10PLUS-NEXT: s_add_u32 s23, s23, s241974; GFX10PLUS-NEXT: s_addc_u32 s21, s34, s211975; GFX10PLUS-NEXT: s_mul_i32 s34, s1, s121976; GFX10PLUS-NEXT: s_mul_hi_u32 s35, s1, s121977; GFX10PLUS-NEXT: s_cselect_b32 s24, 1, 01978; GFX10PLUS-NEXT: s_add_u32 s23, s34, s231979; GFX10PLUS-NEXT: s_addc_u32 s21, s35, s211980; GFX10PLUS-NEXT: s_mul_i32 s35, s2, s111981; GFX10PLUS-NEXT: s_mul_hi_u32 s36, s2, s111982; GFX10PLUS-NEXT: s_cselect_b32 s34, 1, 01983; GFX10PLUS-NEXT: s_add_u32 s23, s35, s231984; GFX10PLUS-NEXT: s_addc_u32 s21, s36, s211985; GFX10PLUS-NEXT: s_mul_i32 s36, s3, s101986; GFX10PLUS-NEXT: s_mul_hi_u32 s37, s3, s101987; GFX10PLUS-NEXT: s_cselect_b32 s35, 1, 01988; GFX10PLUS-NEXT: s_add_u32 s23, s36, s231989; GFX10PLUS-NEXT: s_addc_u32 s21, s37, s211990; GFX10PLUS-NEXT: s_mul_i32 s37, s4, s91991; GFX10PLUS-NEXT: s_mul_hi_u32 s38, s4, s91992; GFX10PLUS-NEXT: s_cselect_b32 s36, 1, 01993; GFX10PLUS-NEXT: s_add_u32 s23, s37, s231994; GFX10PLUS-NEXT: s_addc_u32 s21, s38, s211995; GFX10PLUS-NEXT: s_mul_i32 s38, s5, s81996; GFX10PLUS-NEXT: s_mul_hi_u32 s39, s5, s81997; GFX10PLUS-NEXT: s_cselect_b32 s37, 1, 01998; GFX10PLUS-NEXT: s_add_u32 s23, s38, s231999; GFX10PLUS-NEXT: s_addc_u32 s21, s39, s212000; GFX10PLUS-NEXT: s_cselect_b32 s38, 1, 02001; GFX10PLUS-NEXT: s_cmp_lg_u32 s30, 02002; GFX10PLUS-NEXT: s_mul_i32 s1, s1, s142003; GFX10PLUS-NEXT: s_addc_u32 s29, s29, 02004; GFX10PLUS-NEXT: s_cmp_lg_u32 s31, 02005; GFX10PLUS-NEXT: s_mul_i32 s2, s2, s132006; GFX10PLUS-NEXT: s_addc_u32 s29, s29, 02007; GFX10PLUS-NEXT: s_cmp_lg_u32 s33, 02008; GFX10PLUS-NEXT: s_mul_i32 s3, s3, s122009; GFX10PLUS-NEXT: s_addc_u32 s29, s29, 02010; GFX10PLUS-NEXT: s_cmp_lg_u32 s20, 02011; GFX10PLUS-NEXT: s_mul_i32 s4, s4, s112012; GFX10PLUS-NEXT: s_addc_u32 s20, s29, s232013; GFX10PLUS-NEXT: s_cselect_b32 s23, 1, 02014; GFX10PLUS-NEXT: s_cmp_lg_u32 s26, 02015; GFX10PLUS-NEXT: s_mul_i32 s26, s0, s152016; GFX10PLUS-NEXT: s_addc_u32 s25, s25, 02017; GFX10PLUS-NEXT: s_cmp_lg_u32 s27, 02018; GFX10PLUS-NEXT: s_mul_i32 s5, s5, s102019; GFX10PLUS-NEXT: s_addc_u32 s25, s25, 02020; GFX10PLUS-NEXT: s_cmp_lg_u32 s28, 02021; GFX10PLUS-NEXT: s_mul_i32 s6, s6, s92022; GFX10PLUS-NEXT: s_addc_u32 s25, s25, 02023; GFX10PLUS-NEXT: s_cmp_lg_u32 s23, 02024; GFX10PLUS-NEXT: s_mul_i32 s7, s7, s82025; GFX10PLUS-NEXT: s_addc_u32 s15, s25, s212026; GFX10PLUS-NEXT: s_addc_u32 s21, s22, s262027; GFX10PLUS-NEXT: s_cmp_lg_u32 s38, 02028; GFX10PLUS-NEXT: s_mul_i32 s0, s0, s82029; GFX10PLUS-NEXT: s_addc_u32 s1, s21, s12030; GFX10PLUS-NEXT: s_cmp_lg_u32 s37, 02031; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s22032; GFX10PLUS-NEXT: s_cmp_lg_u32 s36, 02033; GFX10PLUS-NEXT: s_mov_b32 s2, s172034; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s32035; GFX10PLUS-NEXT: s_cmp_lg_u32 s35, 02036; GFX10PLUS-NEXT: s_mov_b32 s3, s182037; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s42038; GFX10PLUS-NEXT: s_cmp_lg_u32 s34, 02039; GFX10PLUS-NEXT: s_mov_b32 s4, s192040; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s52041; GFX10PLUS-NEXT: s_cmp_lg_u32 s24, 02042; GFX10PLUS-NEXT: s_mov_b32 s5, s202043; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s62044; GFX10PLUS-NEXT: s_mov_b32 s6, s152045; GFX10PLUS-NEXT: s_add_i32 s7, s1, s72046; GFX10PLUS-NEXT: s_mov_b32 s1, s162047; GFX10PLUS-NEXT: ; return to shader part epilog2048;2049; GFX12-LABEL: s_mul_i256:2050; GFX12: ; %bb.0:2051; GFX12-NEXT: s_mul_i32 s17, s0, s102052; GFX12-NEXT: s_mul_i32 s19, s1, s92053; GFX12-NEXT: s_mul_hi_u32 s18, s0, s102054; GFX12-NEXT: s_mul_hi_u32 s20, s1, s92055; GFX12-NEXT: s_add_co_u32 s17, s19, s172056; GFX12-NEXT: s_add_co_ci_u32 s18, s20, s182057; GFX12-NEXT: s_mul_i32 s20, s2, s82058; GFX12-NEXT: s_mul_hi_u32 s21, s2, s82059; GFX12-NEXT: s_cselect_b32 s19, 1, 02060; GFX12-NEXT: s_add_co_u32 s17, s20, s172061; GFX12-NEXT: s_mul_hi_u32 s16, s0, s82062; GFX12-NEXT: s_add_co_ci_u32 s18, s21, s182063; GFX12-NEXT: s_mul_i32 s21, s0, s92064; GFX12-NEXT: s_mul_hi_u32 s22, s0, s92065; GFX12-NEXT: s_cselect_b32 s20, 1, 02066; GFX12-NEXT: s_add_co_u32 s16, s21, s162067; GFX12-NEXT: s_add_co_ci_u32 s17, s22, s172068; GFX12-NEXT: s_mul_i32 s22, s1, s82069; GFX12-NEXT: s_mul_hi_u32 s23, s1, s82070; GFX12-NEXT: s_cselect_b32 s21, 1, 02071; GFX12-NEXT: s_add_co_u32 s16, s22, s162072; GFX12-NEXT: s_add_co_ci_u32 s17, s23, s172073; GFX12-NEXT: s_mul_i32 s23, s0, s122074; GFX12-NEXT: s_mul_i32 s25, s1, s112075; GFX12-NEXT: s_mul_hi_u32 s24, s0, s122076; GFX12-NEXT: s_mul_hi_u32 s26, s1, s112077; GFX12-NEXT: s_cselect_b32 s22, 1, 02078; GFX12-NEXT: s_add_co_u32 s23, s25, s232079; GFX12-NEXT: s_add_co_ci_u32 s24, s26, s242080; GFX12-NEXT: s_mul_i32 s26, s2, s102081; GFX12-NEXT: s_mul_hi_u32 s27, s2, s102082; GFX12-NEXT: s_cselect_b32 s25, 1, 02083; GFX12-NEXT: s_add_co_u32 s23, s26, s232084; GFX12-NEXT: s_add_co_ci_u32 s24, s27, s242085; GFX12-NEXT: s_mul_i32 s27, s3, s92086; GFX12-NEXT: s_mul_hi_u32 s28, s3, s92087; GFX12-NEXT: s_cselect_b32 s26, 1, 02088; GFX12-NEXT: s_add_co_u32 s23, s27, s232089; GFX12-NEXT: s_add_co_ci_u32 s24, s28, s242090; GFX12-NEXT: s_mul_i32 s28, s4, s82091; GFX12-NEXT: s_mul_hi_u32 s29, s4, s82092; GFX12-NEXT: s_cselect_b32 s27, 1, 02093; GFX12-NEXT: s_add_co_u32 s23, s28, s232094; GFX12-NEXT: s_add_co_ci_u32 s24, s29, s242095; GFX12-NEXT: s_mul_i32 s29, s0, s112096; GFX12-NEXT: s_mul_hi_u32 s30, s0, s112097; GFX12-NEXT: s_cselect_b32 s28, 1, 02098; GFX12-NEXT: s_add_co_u32 s18, s29, s182099; GFX12-NEXT: s_add_co_ci_u32 s23, s30, s232100; GFX12-NEXT: s_mul_i32 s30, s1, s102101; GFX12-NEXT: s_mul_hi_u32 s31, s1, s102102; GFX12-NEXT: s_cselect_b32 s29, 1, 02103; GFX12-NEXT: s_add_co_u32 s18, s30, s182104; GFX12-NEXT: s_add_co_ci_u32 s23, s31, s232105; GFX12-NEXT: s_mul_i32 s31, s2, s92106; GFX12-NEXT: s_mul_hi_u32 s33, s2, s92107; GFX12-NEXT: s_cselect_b32 s30, 1, 02108; GFX12-NEXT: s_add_co_u32 s18, s31, s182109; GFX12-NEXT: s_add_co_ci_u32 s23, s33, s232110; GFX12-NEXT: s_mul_i32 s33, s3, s82111; GFX12-NEXT: s_mul_hi_u32 s34, s3, s82112; GFX12-NEXT: s_cselect_b32 s31, 1, 02113; GFX12-NEXT: s_add_co_u32 s18, s33, s182114; GFX12-NEXT: s_add_co_ci_u32 s23, s34, s232115; GFX12-NEXT: s_cselect_b32 s33, 1, 02116; GFX12-NEXT: s_cmp_lg_u32 s22, 02117; GFX12-NEXT: s_mul_hi_u32 s22, s0, s142118; GFX12-NEXT: s_add_co_ci_u32 s18, s21, s182119; GFX12-NEXT: s_cselect_b32 s21, 1, 02120; GFX12-NEXT: s_cmp_lg_u32 s20, 02121; GFX12-NEXT: s_mul_hi_u32 s34, s1, s132122; GFX12-NEXT: s_add_co_ci_u32 s19, s19, 02123; GFX12-NEXT: s_cmp_lg_u32 s21, 02124; GFX12-NEXT: s_mul_i32 s21, s0, s142125; GFX12-NEXT: s_add_co_ci_u32 s19, s19, s232126; GFX12-NEXT: s_mul_i32 s23, s1, s132127; GFX12-NEXT: s_cselect_b32 s20, 1, 02128; GFX12-NEXT: s_add_co_u32 s21, s23, s212129; GFX12-NEXT: s_mul_i32 s23, s2, s122130; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s222131; GFX12-NEXT: s_mul_hi_u32 s34, s2, s122132; GFX12-NEXT: s_add_co_u32 s21, s23, s212133; GFX12-NEXT: s_mul_i32 s23, s3, s112134; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s222135; GFX12-NEXT: s_mul_hi_u32 s34, s3, s112136; GFX12-NEXT: s_add_co_u32 s21, s23, s212137; GFX12-NEXT: s_mul_i32 s23, s4, s102138; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s222139; GFX12-NEXT: s_mul_hi_u32 s34, s4, s102140; GFX12-NEXT: s_add_co_u32 s21, s23, s212141; GFX12-NEXT: s_mul_i32 s23, s5, s92142; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s222143; GFX12-NEXT: s_mul_hi_u32 s34, s5, s92144; GFX12-NEXT: s_add_co_u32 s21, s23, s212145; GFX12-NEXT: s_mul_i32 s23, s6, s82146; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s222147; GFX12-NEXT: s_mul_hi_u32 s34, s6, s82148; GFX12-NEXT: s_add_co_u32 s21, s23, s212149; GFX12-NEXT: s_mul_i32 s23, s0, s132150; GFX12-NEXT: s_add_co_ci_u32 s22, s34, s222151; GFX12-NEXT: s_mul_hi_u32 s34, s0, s132152; GFX12-NEXT: s_add_co_u32 s23, s23, s242153; GFX12-NEXT: s_add_co_ci_u32 s21, s34, s212154; GFX12-NEXT: s_mul_i32 s34, s1, s122155; GFX12-NEXT: s_mul_hi_u32 s35, s1, s122156; GFX12-NEXT: s_cselect_b32 s24, 1, 02157; GFX12-NEXT: s_add_co_u32 s23, s34, s232158; GFX12-NEXT: s_add_co_ci_u32 s21, s35, s212159; GFX12-NEXT: s_mul_i32 s35, s2, s112160; GFX12-NEXT: s_mul_hi_u32 s36, s2, s112161; GFX12-NEXT: s_cselect_b32 s34, 1, 02162; GFX12-NEXT: s_add_co_u32 s23, s35, s232163; GFX12-NEXT: s_add_co_ci_u32 s21, s36, s212164; GFX12-NEXT: s_mul_i32 s36, s3, s102165; GFX12-NEXT: s_mul_hi_u32 s37, s3, s102166; GFX12-NEXT: s_cselect_b32 s35, 1, 02167; GFX12-NEXT: s_add_co_u32 s23, s36, s232168; GFX12-NEXT: s_add_co_ci_u32 s21, s37, s212169; GFX12-NEXT: s_mul_i32 s37, s4, s92170; GFX12-NEXT: s_mul_hi_u32 s38, s4, s92171; GFX12-NEXT: s_cselect_b32 s36, 1, 02172; GFX12-NEXT: s_add_co_u32 s23, s37, s232173; GFX12-NEXT: s_add_co_ci_u32 s21, s38, s212174; GFX12-NEXT: s_mul_i32 s38, s5, s82175; GFX12-NEXT: s_mul_hi_u32 s39, s5, s82176; GFX12-NEXT: s_cselect_b32 s37, 1, 02177; GFX12-NEXT: s_add_co_u32 s23, s38, s232178; GFX12-NEXT: s_add_co_ci_u32 s21, s39, s212179; GFX12-NEXT: s_cselect_b32 s38, 1, 02180; GFX12-NEXT: s_cmp_lg_u32 s30, 02181; GFX12-NEXT: s_mul_i32 s1, s1, s142182; GFX12-NEXT: s_add_co_ci_u32 s29, s29, 02183; GFX12-NEXT: s_cmp_lg_u32 s31, 02184; GFX12-NEXT: s_mul_i32 s2, s2, s132185; GFX12-NEXT: s_add_co_ci_u32 s29, s29, 02186; GFX12-NEXT: s_cmp_lg_u32 s33, 02187; GFX12-NEXT: s_mul_i32 s3, s3, s122188; GFX12-NEXT: s_add_co_ci_u32 s29, s29, 02189; GFX12-NEXT: s_cmp_lg_u32 s20, 02190; GFX12-NEXT: s_mul_i32 s4, s4, s112191; GFX12-NEXT: s_add_co_ci_u32 s20, s29, s232192; GFX12-NEXT: s_cselect_b32 s23, 1, 02193; GFX12-NEXT: s_cmp_lg_u32 s26, 02194; GFX12-NEXT: s_mul_i32 s26, s0, s152195; GFX12-NEXT: s_add_co_ci_u32 s25, s25, 02196; GFX12-NEXT: s_cmp_lg_u32 s27, 02197; GFX12-NEXT: s_mul_i32 s5, s5, s102198; GFX12-NEXT: s_add_co_ci_u32 s25, s25, 02199; GFX12-NEXT: s_cmp_lg_u32 s28, 02200; GFX12-NEXT: s_mul_i32 s6, s6, s92201; GFX12-NEXT: s_add_co_ci_u32 s25, s25, 02202; GFX12-NEXT: s_cmp_lg_u32 s23, 02203; GFX12-NEXT: s_mul_i32 s7, s7, s82204; GFX12-NEXT: s_add_co_ci_u32 s15, s25, s212205; GFX12-NEXT: s_add_co_ci_u32 s21, s22, s262206; GFX12-NEXT: s_cmp_lg_u32 s38, 02207; GFX12-NEXT: s_mul_i32 s0, s0, s82208; GFX12-NEXT: s_add_co_ci_u32 s1, s21, s12209; GFX12-NEXT: s_cmp_lg_u32 s37, 02210; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s22211; GFX12-NEXT: s_cmp_lg_u32 s36, 02212; GFX12-NEXT: s_mov_b32 s2, s172213; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s32214; GFX12-NEXT: s_cmp_lg_u32 s35, 02215; GFX12-NEXT: s_mov_b32 s3, s182216; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s42217; GFX12-NEXT: s_cmp_lg_u32 s34, 02218; GFX12-NEXT: s_mov_b32 s4, s192219; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s52220; GFX12-NEXT: s_cmp_lg_u32 s24, 02221; GFX12-NEXT: s_mov_b32 s5, s202222; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s62223; GFX12-NEXT: s_mov_b32 s6, s152224; GFX12-NEXT: s_add_co_i32 s7, s1, s72225; GFX12-NEXT: s_mov_b32 s1, s162226; GFX12-NEXT: ; return to shader part epilog2227;2228; GFX1250-LABEL: s_mul_i256:2229; GFX1250: ; %bb.0:2230; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12231; GFX1250-NEXT: s_mul_i32 s17, s0, s102232; GFX1250-NEXT: s_mul_i32 s19, s1, s92233; GFX1250-NEXT: s_mul_hi_u32 s18, s0, s102234; GFX1250-NEXT: s_mul_hi_u32 s20, s1, s92235; GFX1250-NEXT: s_add_co_u32 s17, s19, s172236; GFX1250-NEXT: s_add_co_ci_u32 s18, s20, s182237; GFX1250-NEXT: s_mul_i32 s20, s2, s82238; GFX1250-NEXT: s_mul_hi_u32 s21, s2, s82239; GFX1250-NEXT: s_cselect_b32 s19, 1, 02240; GFX1250-NEXT: s_add_co_u32 s17, s20, s172241; GFX1250-NEXT: s_mul_hi_u32 s16, s0, s82242; GFX1250-NEXT: s_add_co_ci_u32 s18, s21, s182243; GFX1250-NEXT: s_mul_i32 s21, s0, s92244; GFX1250-NEXT: s_mul_hi_u32 s22, s0, s92245; GFX1250-NEXT: s_cselect_b32 s20, 1, 02246; GFX1250-NEXT: s_add_co_u32 s16, s21, s162247; GFX1250-NEXT: s_add_co_ci_u32 s17, s22, s172248; GFX1250-NEXT: s_mul_i32 s22, s1, s82249; GFX1250-NEXT: s_mul_hi_u32 s23, s1, s82250; GFX1250-NEXT: s_cselect_b32 s21, 1, 02251; GFX1250-NEXT: s_add_co_u32 s16, s22, s162252; GFX1250-NEXT: s_add_co_ci_u32 s17, s23, s172253; GFX1250-NEXT: s_mul_i32 s23, s0, s122254; GFX1250-NEXT: s_mul_i32 s25, s1, s112255; GFX1250-NEXT: s_mul_hi_u32 s24, s0, s122256; GFX1250-NEXT: s_mul_hi_u32 s26, s1, s112257; GFX1250-NEXT: s_cselect_b32 s22, 1, 02258; GFX1250-NEXT: s_add_co_u32 s23, s25, s232259; GFX1250-NEXT: s_add_co_ci_u32 s24, s26, s242260; GFX1250-NEXT: s_mul_i32 s26, s2, s102261; GFX1250-NEXT: s_mul_hi_u32 s27, s2, s102262; GFX1250-NEXT: s_cselect_b32 s25, 1, 02263; GFX1250-NEXT: s_add_co_u32 s23, s26, s232264; GFX1250-NEXT: s_add_co_ci_u32 s24, s27, s242265; GFX1250-NEXT: s_mul_i32 s27, s3, s92266; GFX1250-NEXT: s_mul_hi_u32 s28, s3, s92267; GFX1250-NEXT: s_cselect_b32 s26, 1, 02268; GFX1250-NEXT: s_add_co_u32 s23, s27, s232269; GFX1250-NEXT: s_add_co_ci_u32 s24, s28, s242270; GFX1250-NEXT: s_mul_i32 s28, s4, s82271; GFX1250-NEXT: s_mul_hi_u32 s29, s4, s82272; GFX1250-NEXT: s_cselect_b32 s27, 1, 02273; GFX1250-NEXT: s_add_co_u32 s23, s28, s232274; GFX1250-NEXT: s_add_co_ci_u32 s24, s29, s242275; GFX1250-NEXT: s_mul_i32 s29, s0, s112276; GFX1250-NEXT: s_mul_hi_u32 s30, s0, s112277; GFX1250-NEXT: s_cselect_b32 s28, 1, 02278; GFX1250-NEXT: s_add_co_u32 s18, s29, s182279; GFX1250-NEXT: s_add_co_ci_u32 s23, s30, s232280; GFX1250-NEXT: s_mul_i32 s30, s1, s102281; GFX1250-NEXT: s_mul_hi_u32 s31, s1, s102282; GFX1250-NEXT: s_cselect_b32 s29, 1, 02283; GFX1250-NEXT: s_add_co_u32 s18, s30, s182284; GFX1250-NEXT: s_add_co_ci_u32 s23, s31, s232285; GFX1250-NEXT: s_mul_i32 s31, s2, s92286; GFX1250-NEXT: s_mul_hi_u32 s33, s2, s92287; GFX1250-NEXT: s_cselect_b32 s30, 1, 02288; GFX1250-NEXT: s_add_co_u32 s18, s31, s182289; GFX1250-NEXT: s_add_co_ci_u32 s23, s33, s232290; GFX1250-NEXT: s_mul_i32 s33, s3, s82291; GFX1250-NEXT: s_mul_hi_u32 s34, s3, s82292; GFX1250-NEXT: s_cselect_b32 s31, 1, 02293; GFX1250-NEXT: s_add_co_u32 s18, s33, s182294; GFX1250-NEXT: s_add_co_ci_u32 s23, s34, s232295; GFX1250-NEXT: s_cselect_b32 s33, 1, 02296; GFX1250-NEXT: s_cmp_lg_u32 s22, 02297; GFX1250-NEXT: s_mul_hi_u32 s22, s0, s142298; GFX1250-NEXT: s_add_co_ci_u32 s18, s21, s182299; GFX1250-NEXT: s_cselect_b32 s21, 1, 02300; GFX1250-NEXT: s_cmp_lg_u32 s20, 02301; GFX1250-NEXT: s_mul_hi_u32 s34, s1, s132302; GFX1250-NEXT: s_add_co_ci_u32 s19, s19, 02303; GFX1250-NEXT: s_cmp_lg_u32 s21, 02304; GFX1250-NEXT: s_mul_i32 s21, s0, s142305; GFX1250-NEXT: s_add_co_ci_u32 s19, s19, s232306; GFX1250-NEXT: s_mul_i32 s23, s1, s132307; GFX1250-NEXT: s_cselect_b32 s20, 1, 02308; GFX1250-NEXT: s_add_co_u32 s21, s23, s212309; GFX1250-NEXT: s_mul_i32 s23, s2, s122310; GFX1250-NEXT: s_add_co_ci_u32 s22, s34, s222311; GFX1250-NEXT: s_mul_hi_u32 s34, s2, s122312; GFX1250-NEXT: s_add_co_u32 s21, s23, s212313; GFX1250-NEXT: s_mul_i32 s23, s3, s112314; GFX1250-NEXT: s_add_co_ci_u32 s22, s34, s222315; GFX1250-NEXT: s_mul_hi_u32 s34, s3, s112316; GFX1250-NEXT: s_add_co_u32 s21, s23, s212317; GFX1250-NEXT: s_mul_i32 s23, s4, s102318; GFX1250-NEXT: s_add_co_ci_u32 s22, s34, s222319; GFX1250-NEXT: s_mul_hi_u32 s34, s4, s102320; GFX1250-NEXT: s_add_co_u32 s21, s23, s212321; GFX1250-NEXT: s_mul_i32 s23, s5, s92322; GFX1250-NEXT: s_add_co_ci_u32 s22, s34, s222323; GFX1250-NEXT: s_mul_hi_u32 s34, s5, s92324; GFX1250-NEXT: s_add_co_u32 s21, s23, s212325; GFX1250-NEXT: s_mul_i32 s23, s6, s82326; GFX1250-NEXT: s_add_co_ci_u32 s22, s34, s222327; GFX1250-NEXT: s_mul_hi_u32 s34, s6, s82328; GFX1250-NEXT: s_add_co_u32 s21, s23, s212329; GFX1250-NEXT: s_mul_i32 s23, s0, s132330; GFX1250-NEXT: s_add_co_ci_u32 s22, s34, s222331; GFX1250-NEXT: s_mul_hi_u32 s34, s0, s132332; GFX1250-NEXT: s_add_co_u32 s23, s23, s242333; GFX1250-NEXT: s_add_co_ci_u32 s21, s34, s212334; GFX1250-NEXT: s_mul_i32 s34, s1, s122335; GFX1250-NEXT: s_mul_hi_u32 s35, s1, s122336; GFX1250-NEXT: s_cselect_b32 s24, 1, 02337; GFX1250-NEXT: s_add_co_u32 s23, s34, s232338; GFX1250-NEXT: s_add_co_ci_u32 s21, s35, s212339; GFX1250-NEXT: s_mul_i32 s35, s2, s112340; GFX1250-NEXT: s_mul_hi_u32 s36, s2, s112341; GFX1250-NEXT: s_cselect_b32 s34, 1, 02342; GFX1250-NEXT: s_add_co_u32 s23, s35, s232343; GFX1250-NEXT: s_add_co_ci_u32 s21, s36, s212344; GFX1250-NEXT: s_mul_i32 s36, s3, s102345; GFX1250-NEXT: s_mul_hi_u32 s37, s3, s102346; GFX1250-NEXT: s_cselect_b32 s35, 1, 02347; GFX1250-NEXT: s_add_co_u32 s23, s36, s232348; GFX1250-NEXT: s_add_co_ci_u32 s21, s37, s212349; GFX1250-NEXT: s_mul_i32 s37, s4, s92350; GFX1250-NEXT: s_mul_hi_u32 s38, s4, s92351; GFX1250-NEXT: s_cselect_b32 s36, 1, 02352; GFX1250-NEXT: s_add_co_u32 s23, s37, s232353; GFX1250-NEXT: s_add_co_ci_u32 s21, s38, s212354; GFX1250-NEXT: s_mul_i32 s38, s5, s82355; GFX1250-NEXT: s_mul_hi_u32 s39, s5, s82356; GFX1250-NEXT: s_cselect_b32 s37, 1, 02357; GFX1250-NEXT: s_add_co_u32 s23, s38, s232358; GFX1250-NEXT: s_add_co_ci_u32 s21, s39, s212359; GFX1250-NEXT: s_cselect_b32 s38, 1, 02360; GFX1250-NEXT: s_cmp_lg_u32 s30, 02361; GFX1250-NEXT: s_mul_i32 s1, s1, s142362; GFX1250-NEXT: s_add_co_ci_u32 s29, s29, 02363; GFX1250-NEXT: s_cmp_lg_u32 s31, 02364; GFX1250-NEXT: s_mul_i32 s2, s2, s132365; GFX1250-NEXT: s_add_co_ci_u32 s29, s29, 02366; GFX1250-NEXT: s_cmp_lg_u32 s33, 02367; GFX1250-NEXT: s_mul_i32 s3, s3, s122368; GFX1250-NEXT: s_add_co_ci_u32 s29, s29, 02369; GFX1250-NEXT: s_cmp_lg_u32 s20, 02370; GFX1250-NEXT: s_mul_i32 s4, s4, s112371; GFX1250-NEXT: s_add_co_ci_u32 s20, s29, s232372; GFX1250-NEXT: s_cselect_b32 s23, 1, 02373; GFX1250-NEXT: s_cmp_lg_u32 s26, 02374; GFX1250-NEXT: s_mul_i32 s26, s0, s152375; GFX1250-NEXT: s_add_co_ci_u32 s25, s25, 02376; GFX1250-NEXT: s_cmp_lg_u32 s27, 02377; GFX1250-NEXT: s_mul_i32 s5, s5, s102378; GFX1250-NEXT: s_add_co_ci_u32 s25, s25, 02379; GFX1250-NEXT: s_cmp_lg_u32 s28, 02380; GFX1250-NEXT: s_mul_i32 s6, s6, s92381; GFX1250-NEXT: s_add_co_ci_u32 s25, s25, 02382; GFX1250-NEXT: s_cmp_lg_u32 s23, 02383; GFX1250-NEXT: s_mul_i32 s7, s7, s82384; GFX1250-NEXT: s_add_co_ci_u32 s15, s25, s212385; GFX1250-NEXT: s_add_co_ci_u32 s21, s22, s262386; GFX1250-NEXT: s_cmp_lg_u32 s38, 02387; GFX1250-NEXT: s_mul_i32 s0, s0, s82388; GFX1250-NEXT: s_add_co_ci_u32 s1, s21, s12389; GFX1250-NEXT: s_cmp_lg_u32 s37, 02390; GFX1250-NEXT: s_add_co_ci_u32 s1, s1, s22391; GFX1250-NEXT: s_cmp_lg_u32 s36, 02392; GFX1250-NEXT: s_mov_b32 s2, s172393; GFX1250-NEXT: s_add_co_ci_u32 s1, s1, s32394; GFX1250-NEXT: s_cmp_lg_u32 s35, 02395; GFX1250-NEXT: s_mov_b32 s3, s182396; GFX1250-NEXT: s_add_co_ci_u32 s1, s1, s42397; GFX1250-NEXT: s_cmp_lg_u32 s34, 02398; GFX1250-NEXT: s_mov_b32 s4, s192399; GFX1250-NEXT: s_add_co_ci_u32 s1, s1, s52400; GFX1250-NEXT: s_cmp_lg_u32 s24, 02401; GFX1250-NEXT: s_mov_b32 s5, s202402; GFX1250-NEXT: s_add_co_ci_u32 s1, s1, s62403; GFX1250-NEXT: s_mov_b32 s6, s152404; GFX1250-NEXT: s_add_co_i32 s7, s1, s72405; GFX1250-NEXT: s_mov_b32 s1, s162406; GFX1250-NEXT: ; return to shader part epilog2407 %result = mul i256 %num, %den2408 %cast = bitcast i256 %result to <8 x i32>2409 ret <8 x i32> %cast2410}2411 2412define i256 @v_mul_i256(i256 %num, i256 %den) {2413; GFX7-LABEL: v_mul_i256:2414; GFX7: ; %bb.0:2415; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2416; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v14, 02417; GFX7-NEXT: v_mul_lo_u32 v28, v4, v112418; GFX7-NEXT: v_mul_lo_u32 v29, v3, v122419; GFX7-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v1, v13, v[16:17]2420; GFX7-NEXT: v_mul_lo_u32 v30, v2, v132421; GFX7-NEXT: v_mul_lo_u32 v27, v5, v102422; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v12, v[18:19]2423; GFX7-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v3, v11, v[16:17]2424; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v10, 02425; GFX7-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v4, v10, v[18:19]2426; GFX7-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v1, v9, v[16:17]2427; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[6:7], v5, v9, v[20:21]2428; GFX7-NEXT: v_cndmask_b32_e64 v26, 0, 1, s[4:5]2429; GFX7-NEXT: v_mad_u64_u32 v[18:19], vcc, v2, v8, v[22:23]2430; GFX7-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v6, v8, v[16:17]2431; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v12, 02432; GFX7-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v1, v11, v[16:17]2433; GFX7-NEXT: v_cndmask_b32_e64 v24, 0, 1, s[4:5]2434; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v10, v[20:21]2435; GFX7-NEXT: v_addc_u32_e64 v20, s[4:5], 0, v24, s[4:5]2436; GFX7-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v3, v9, v[16:17]2437; GFX7-NEXT: v_addc_u32_e64 v16, s[4:5], 0, v20, s[4:5]2438; GFX7-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v4, v8, v[24:25]2439; GFX7-NEXT: v_addc_u32_e64 v24, s[4:5], 0, v16, s[4:5]2440; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v13, v[21:22]2441; GFX7-NEXT: v_mul_lo_u32 v25, v6, v92442; GFX7-NEXT: v_mad_u64_u32 v[21:22], s[6:7], v1, v12, v[16:17]2443; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[8:9], v2, v11, v[21:22]2444; GFX7-NEXT: v_mad_u64_u32 v[21:22], s[10:11], v3, v10, v[16:17]2445; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[14:15], v0, v11, v[19:20]2446; GFX7-NEXT: v_mad_u64_u32 v[12:13], s[12:13], v4, v9, v[21:22]2447; GFX7-NEXT: v_addc_u32_e32 v4, vcc, 0, v26, vcc2448; GFX7-NEXT: v_mad_u64_u32 v[19:20], vcc, v1, v10, v[16:17]2449; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[14:15]2450; GFX7-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc2451; GFX7-NEXT: v_mad_u64_u32 v[10:11], vcc, v2, v9, v[19:20]2452; GFX7-NEXT: v_mad_u64_u32 v[16:17], s[16:17], v0, v8, 02453; GFX7-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc2454; GFX7-NEXT: v_mad_u64_u32 v[19:20], vcc, v3, v8, v[10:11]2455; GFX7-NEXT: v_mad_u64_u32 v[21:22], s[14:15], v5, v8, v[12:13]2456; GFX7-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc2457; GFX7-NEXT: v_mad_u64_u32 v[2:3], s[16:17], v0, v9, v[17:18]2458; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[16:17]2459; GFX7-NEXT: v_mul_lo_u32 v0, v0, v152460; GFX7-NEXT: v_mad_u64_u32 v[11:12], vcc, v1, v8, v[2:3]2461; GFX7-NEXT: v_addc_u32_e32 v3, vcc, v6, v19, vcc2462; GFX7-NEXT: v_mul_lo_u32 v10, v1, v142463; GFX7-NEXT: v_addc_u32_e32 v4, vcc, v4, v20, vcc2464; GFX7-NEXT: v_addc_u32_e32 v5, vcc, v5, v21, vcc2465; GFX7-NEXT: v_addc_u32_e32 v6, vcc, v24, v22, vcc2466; GFX7-NEXT: v_addc_u32_e32 v0, vcc, v23, v0, vcc2467; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v10, s[14:15]2468; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v30, s[12:13]2469; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v29, s[10:11]2470; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v28, s[8:9]2471; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v27, s[6:7]2472; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v25, s[4:5]2473; GFX7-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v7, v8, v[0:1]2474; GFX7-NEXT: v_mov_b32_e32 v0, v162475; GFX7-NEXT: v_mov_b32_e32 v1, v112476; GFX7-NEXT: v_mov_b32_e32 v2, v122477; GFX7-NEXT: v_mov_b32_e32 v7, v92478; GFX7-NEXT: s_setpc_b64 s[30:31]2479;2480; GFX8-LABEL: v_mul_i256:2481; GFX8: ; %bb.0:2482; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2483; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v14, 02484; GFX8-NEXT: v_mul_lo_u32 v28, v4, v112485; GFX8-NEXT: v_mul_lo_u32 v29, v3, v122486; GFX8-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v1, v13, v[16:17]2487; GFX8-NEXT: v_mul_lo_u32 v30, v2, v132488; GFX8-NEXT: v_mul_lo_u32 v27, v5, v102489; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v12, v[18:19]2490; GFX8-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v3, v11, v[16:17]2491; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v10, 02492; GFX8-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v4, v10, v[18:19]2493; GFX8-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v1, v9, v[16:17]2494; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[6:7], v5, v9, v[20:21]2495; GFX8-NEXT: v_cndmask_b32_e64 v26, 0, 1, s[4:5]2496; GFX8-NEXT: v_mad_u64_u32 v[18:19], vcc, v2, v8, v[22:23]2497; GFX8-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v6, v8, v[16:17]2498; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v12, 02499; GFX8-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v1, v11, v[16:17]2500; GFX8-NEXT: v_cndmask_b32_e64 v24, 0, 1, s[4:5]2501; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v10, v[20:21]2502; GFX8-NEXT: v_addc_u32_e64 v20, s[4:5], 0, v24, s[4:5]2503; GFX8-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v3, v9, v[16:17]2504; GFX8-NEXT: v_addc_u32_e64 v16, s[4:5], 0, v20, s[4:5]2505; GFX8-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v4, v8, v[24:25]2506; GFX8-NEXT: v_addc_u32_e64 v24, s[4:5], 0, v16, s[4:5]2507; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v13, v[21:22]2508; GFX8-NEXT: v_mul_lo_u32 v25, v6, v92509; GFX8-NEXT: v_mad_u64_u32 v[21:22], s[6:7], v1, v12, v[16:17]2510; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[8:9], v2, v11, v[21:22]2511; GFX8-NEXT: v_mad_u64_u32 v[21:22], s[10:11], v3, v10, v[16:17]2512; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[14:15], v0, v11, v[19:20]2513; GFX8-NEXT: v_mad_u64_u32 v[12:13], s[12:13], v4, v9, v[21:22]2514; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v26, vcc2515; GFX8-NEXT: v_mad_u64_u32 v[19:20], vcc, v1, v10, v[16:17]2516; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[14:15]2517; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc2518; GFX8-NEXT: v_mad_u64_u32 v[10:11], vcc, v2, v9, v[19:20]2519; GFX8-NEXT: v_mad_u64_u32 v[16:17], s[16:17], v0, v8, 02520; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc2521; GFX8-NEXT: v_mad_u64_u32 v[19:20], vcc, v3, v8, v[10:11]2522; GFX8-NEXT: v_mad_u64_u32 v[21:22], s[14:15], v5, v8, v[12:13]2523; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc2524; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[16:17], v0, v9, v[17:18]2525; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[16:17]2526; GFX8-NEXT: v_mul_lo_u32 v0, v0, v152527; GFX8-NEXT: v_mad_u64_u32 v[11:12], vcc, v1, v8, v[2:3]2528; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v6, v19, vcc2529; GFX8-NEXT: v_mul_lo_u32 v10, v1, v142530; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v4, v20, vcc2531; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v5, v21, vcc2532; GFX8-NEXT: v_addc_u32_e32 v6, vcc, v24, v22, vcc2533; GFX8-NEXT: v_addc_u32_e32 v0, vcc, v23, v0, vcc2534; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v10, s[14:15]2535; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v30, s[12:13]2536; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v29, s[10:11]2537; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v28, s[8:9]2538; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v27, s[6:7]2539; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v25, s[4:5]2540; GFX8-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v7, v8, v[0:1]2541; GFX8-NEXT: v_mov_b32_e32 v0, v162542; GFX8-NEXT: v_mov_b32_e32 v1, v112543; GFX8-NEXT: v_mov_b32_e32 v2, v122544; GFX8-NEXT: v_mov_b32_e32 v7, v92545; GFX8-NEXT: s_setpc_b64 s[30:31]2546;2547; GFX9-LABEL: v_mul_i256:2548; GFX9: ; %bb.0:2549; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2550; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v14, 02551; GFX9-NEXT: v_mul_lo_u32 v28, v4, v112552; GFX9-NEXT: v_mul_lo_u32 v29, v3, v122553; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v1, v13, v[16:17]2554; GFX9-NEXT: v_mul_lo_u32 v30, v2, v132555; GFX9-NEXT: v_mul_lo_u32 v27, v5, v102556; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v12, v[18:19]2557; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v3, v11, v[16:17]2558; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v10, 02559; GFX9-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v4, v10, v[18:19]2560; GFX9-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v1, v9, v[16:17]2561; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[6:7], v5, v9, v[20:21]2562; GFX9-NEXT: v_cndmask_b32_e64 v26, 0, 1, s[4:5]2563; GFX9-NEXT: v_mad_u64_u32 v[18:19], vcc, v2, v8, v[22:23]2564; GFX9-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v6, v8, v[16:17]2565; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v12, 02566; GFX9-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v1, v11, v[16:17]2567; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, 1, s[4:5]2568; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v2, v10, v[20:21]2569; GFX9-NEXT: v_addc_co_u32_e64 v20, s[4:5], 0, v24, s[4:5]2570; GFX9-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v3, v9, v[16:17]2571; GFX9-NEXT: v_addc_co_u32_e64 v16, s[4:5], 0, v20, s[4:5]2572; GFX9-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v4, v8, v[24:25]2573; GFX9-NEXT: v_addc_co_u32_e64 v24, s[4:5], 0, v16, s[4:5]2574; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v0, v13, v[21:22]2575; GFX9-NEXT: v_mul_lo_u32 v25, v6, v92576; GFX9-NEXT: v_mad_u64_u32 v[21:22], s[6:7], v1, v12, v[16:17]2577; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[8:9], v2, v11, v[21:22]2578; GFX9-NEXT: v_mad_u64_u32 v[21:22], s[10:11], v3, v10, v[16:17]2579; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[14:15], v0, v11, v[19:20]2580; GFX9-NEXT: v_mad_u64_u32 v[12:13], s[12:13], v4, v9, v[21:22]2581; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v26, vcc2582; GFX9-NEXT: v_mad_u64_u32 v[19:20], vcc, v1, v10, v[16:17]2583; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[14:15]2584; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc2585; GFX9-NEXT: v_mad_u64_u32 v[10:11], vcc, v2, v9, v[19:20]2586; GFX9-NEXT: v_mad_u64_u32 v[16:17], s[16:17], v0, v8, 02587; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v6, vcc2588; GFX9-NEXT: v_mad_u64_u32 v[19:20], vcc, v3, v8, v[10:11]2589; GFX9-NEXT: v_mad_u64_u32 v[21:22], s[14:15], v5, v8, v[12:13]2590; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v2, vcc2591; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[16:17], v0, v9, v[17:18]2592; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[16:17]2593; GFX9-NEXT: v_mul_lo_u32 v0, v0, v152594; GFX9-NEXT: v_mad_u64_u32 v[11:12], vcc, v1, v8, v[2:3]2595; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v19, vcc2596; GFX9-NEXT: v_mul_lo_u32 v10, v1, v142597; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v20, vcc2598; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v21, vcc2599; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v24, v22, vcc2600; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v23, v0, vcc2601; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v10, s[14:15]2602; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v30, s[12:13]2603; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v29, s[10:11]2604; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v28, s[8:9]2605; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v27, s[6:7]2606; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v25, s[4:5]2607; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v7, v8, v[0:1]2608; GFX9-NEXT: v_mov_b32_e32 v0, v162609; GFX9-NEXT: v_mov_b32_e32 v1, v112610; GFX9-NEXT: v_mov_b32_e32 v2, v122611; GFX9-NEXT: v_mov_b32_e32 v7, v92612; GFX9-NEXT: s_setpc_b64 s[30:31]2613;2614; GFX10-LABEL: v_mul_i256:2615; GFX10: ; %bb.0:2616; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2617; GFX10-NEXT: v_mov_b32_e32 v16, v02618; GFX10-NEXT: v_mov_b32_e32 v17, v12619; GFX10-NEXT: v_mov_b32_e32 v18, v22620; GFX10-NEXT: v_mov_b32_e32 v19, v32621; GFX10-NEXT: v_mov_b32_e32 v20, v42622; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v16, v14, 02623; GFX10-NEXT: v_mov_b32_e32 v21, v52624; GFX10-NEXT: v_mov_b32_e32 v0, v62625; GFX10-NEXT: v_mov_b32_e32 v22, v72626; GFX10-NEXT: v_mul_lo_u32 v31, v17, v142627; GFX10-NEXT: v_mul_lo_u32 v29, v20, v112628; GFX10-NEXT: v_mul_lo_u32 v30, v16, v152629; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v17, v13, v[1:2]2630; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v16, v12, 02631; GFX10-NEXT: v_mul_lo_u32 v27, v0, v92632; GFX10-NEXT: v_mad_u64_u32 v[5:6], s4, v18, v12, v[3:4]2633; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v17, v11, v[1:2]2634; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s42635; GFX10-NEXT: v_mad_u64_u32 v[25:26], s4, v16, v10, 02636; GFX10-NEXT: v_mad_u64_u32 v[1:2], s5, v19, v11, v[5:6]2637; GFX10-NEXT: v_mad_u64_u32 v[5:6], vcc_lo, v18, v10, v[3:4]2638; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo2639; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v20, v10, v[1:2]2640; GFX10-NEXT: v_mad_u64_u32 v[1:2], vcc_lo, v19, v9, v[5:6]2641; GFX10-NEXT: v_mad_u64_u32 v[23:24], s4, v21, v9, v[3:4]2642; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo2643; GFX10-NEXT: v_mad_u64_u32 v[4:5], vcc_lo, v20, v8, v[1:2]2644; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v0, v8, v[23:24]2645; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v17, v9, v[25:26]2646; GFX10-NEXT: v_add_co_ci_u32_e32 v25, vcc_lo, 0, v3, vcc_lo2647; GFX10-NEXT: v_cndmask_b32_e64 v28, 0, 1, s42648; GFX10-NEXT: v_mul_lo_u32 v26, v21, v102649; GFX10-NEXT: v_mad_u64_u32 v[23:24], vcc_lo, v16, v13, v[5:6]2650; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v18, v8, v[0:1]2651; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, v16, v8, 02652; GFX10-NEXT: v_add_co_ci_u32_e64 v28, s4, 0, v28, s42653; GFX10-NEXT: v_mad_u64_u32 v[5:6], s5, v17, v12, v[23:24]2654; GFX10-NEXT: v_mad_u64_u32 v[23:24], s6, v16, v11, v[3:4]2655; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s62656; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v18, v11, v[5:6]2657; GFX10-NEXT: v_mad_u64_u32 v[5:6], s6, v17, v10, v[23:24]2658; GFX10-NEXT: v_mul_lo_u32 v23, v19, v122659; GFX10-NEXT: v_mul_lo_u32 v24, v18, v132660; GFX10-NEXT: v_mad_u64_u32 v[11:12], s7, v19, v10, v[3:4]2661; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s6, 0, v14, s62662; GFX10-NEXT: v_mad_u64_u32 v[3:4], s6, v18, v9, v[5:6]2663; GFX10-NEXT: v_add_co_ci_u32_e64 v14, s6, 0, v10, s62664; GFX10-NEXT: v_mad_u64_u32 v[5:6], s6, v20, v9, v[11:12]2665; GFX10-NEXT: v_mad_u64_u32 v[10:11], s8, v16, v9, v[1:2]2666; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s82667; GFX10-NEXT: v_mad_u64_u32 v[12:13], s8, v19, v8, v[3:4]2668; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s8, 0, v14, s82669; GFX10-NEXT: v_mad_u64_u32 v[14:15], s8, v21, v8, v[5:6]2670; GFX10-NEXT: v_mad_u64_u32 v[1:2], s9, v17, v8, v[10:11]2671; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s9, v9, v12, s92672; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s9, v28, v13, s92673; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s9, v16, v14, s92674; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s9, v25, v15, s92675; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s9, v7, v30, s92676; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s8, v7, v31, s82677; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s6, v7, v24, s62678; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s6, v7, v23, s72679; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v7, v29, s42680; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v7, v26, s52681; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v27, vcc_lo2682; GFX10-NEXT: v_mad_u64_u32 v[7:8], s4, v22, v8, v[7:8]2683; GFX10-NEXT: s_setpc_b64 s[30:31]2684;2685; GFX11-LABEL: v_mul_i256:2686; GFX11: ; %bb.0:2687; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2688; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v12689; GFX11-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v32690; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v21, v52691; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v16, v14, 02692; GFX11-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v23, v72693; GFX11-NEXT: v_mov_b32_e32 v22, v82694; GFX11-NEXT: v_mad_u64_u32 v[26:27], null, v16, v10, 02695; GFX11-NEXT: v_mul_lo_u32 v28, v0, v92696; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v17, v13, v[1:2]2697; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v16, v12, 02698; GFX11-NEXT: v_mul_lo_u32 v30, v20, v112699; GFX11-NEXT: v_mul_lo_u32 v15, v16, v152700; GFX11-NEXT: v_mul_lo_u32 v14, v17, v142701; GFX11-NEXT: v_mad_u64_u32 v[5:6], null, v18, v12, v[3:4]2702; GFX11-NEXT: v_mad_u64_u32 v[3:4], s0, v17, v11, v[1:2]2703; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1, s02704; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v19, v11, v[5:6]2705; GFX11-NEXT: v_mad_u64_u32 v[5:6], vcc_lo, v18, v10, v[3:4]2706; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo2707; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v20, v10, v[1:2]2708; GFX11-NEXT: v_mad_u64_u32 v[1:2], vcc_lo, v19, v9, v[5:6]2709; GFX11-NEXT: v_mad_u64_u32 v[24:25], null, v21, v9, v[3:4]2710; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v7, vcc_lo2711; GFX11-NEXT: v_mad_u64_u32 v[4:5], vcc_lo, v20, v22, v[1:2]2712; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v0, v22, v[24:25]2713; GFX11-NEXT: v_mad_u64_u32 v[0:1], s0, v17, v9, v[26:27]2714; GFX11-NEXT: v_add_co_ci_u32_e64 v26, null, 0, v3, vcc_lo2715; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, s02716; GFX11-NEXT: v_mul_lo_u32 v27, v21, v102717; GFX11-NEXT: v_mad_u64_u32 v[24:25], vcc_lo, v16, v13, v[5:6]2718; GFX11-NEXT: v_mad_u64_u32 v[2:3], s0, v18, v22, v[0:1]2719; GFX11-NEXT: v_add_co_ci_u32_e64 v29, null, 0, v8, s02720; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v16, v22, 02721; GFX11-NEXT: v_mad_u64_u32 v[5:6], s1, v17, v12, v[24:25]2722; GFX11-NEXT: v_mad_u64_u32 v[24:25], s2, v16, v11, v[3:4]2723; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, s22724; GFX11-NEXT: v_mad_u64_u32 v[3:4], s0, v18, v11, v[5:6]2725; GFX11-NEXT: v_mad_u64_u32 v[5:6], s2, v17, v10, v[24:25]2726; GFX11-NEXT: v_mul_lo_u32 v24, v19, v122727; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, 0, v8, s22728; GFX11-NEXT: v_mul_lo_u32 v25, v18, v132729; GFX11-NEXT: v_mad_u64_u32 v[11:12], s3, v19, v10, v[3:4]2730; GFX11-NEXT: v_mad_u64_u32 v[3:4], s2, v18, v9, v[5:6]2731; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v8, s22732; GFX11-NEXT: v_mad_u64_u32 v[5:6], s2, v20, v9, v[11:12]2733; GFX11-NEXT: v_mad_u64_u32 v[10:11], s4, v16, v9, v[1:2]2734; GFX11-NEXT: v_cndmask_b32_e64 v16, 0, 1, s42735; GFX11-NEXT: v_mad_u64_u32 v[8:9], s4, v19, v22, v[3:4]2736; GFX11-NEXT: v_add_co_ci_u32_e64 v18, null, 0, v13, s42737; GFX11-NEXT: v_mad_u64_u32 v[12:13], s4, v21, v22, v[5:6]2738; GFX11-NEXT: v_mad_u64_u32 v[1:2], s5, v17, v22, v[10:11]2739; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s5, v16, v8, s52740; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s5, v29, v9, s52741; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s5, v18, v12, s52742; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s5, v26, v13, s52743; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v15, s52744; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v14, s42745; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v25, s22746; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v24, s32747; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v30, s02748; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v27, s12749; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, v7, v28, vcc_lo2750; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v23, v22, v[9:10]2751; GFX11-NEXT: s_setpc_b64 s[30:31]2752;2753; GFX12-LABEL: v_mul_i256:2754; GFX12: ; %bb.0:2755; GFX12-NEXT: s_wait_loadcnt_dscnt 0x02756; GFX12-NEXT: s_wait_expcnt 0x02757; GFX12-NEXT: s_wait_samplecnt 0x02758; GFX12-NEXT: s_wait_bvhcnt 0x02759; GFX12-NEXT: s_wait_kmcnt 0x02760; GFX12-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v12761; GFX12-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v32762; GFX12-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v21, v52763; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)2764; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v16, v14, 02765; GFX12-NEXT: v_mov_b32_e32 v0, v62766; GFX12-NEXT: v_mov_b32_e32 v22, v72767; GFX12-NEXT: v_mad_co_u64_u32 v[25:26], null, v16, v10, 02768; GFX12-NEXT: v_mul_lo_u32 v31, v17, v142769; GFX12-NEXT: v_mul_lo_u32 v27, v0, v92770; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v17, v13, v[1:2]2771; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v16, v12, 02772; GFX12-NEXT: v_mul_lo_u32 v29, v20, v112773; GFX12-NEXT: v_mul_lo_u32 v30, v16, v152774; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2775; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v18, v12, v[3:4]2776; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], s0, v17, v11, v[1:2]2777; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2778; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, s02779; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2780; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v19, v11, v[5:6]2781; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], vcc_lo, v18, v10, v[3:4]2782; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)2783; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2784; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo2785; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v20, v10, v[1:2]2786; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2787; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], vcc_lo, v19, v9, v[5:6]2788; GFX12-NEXT: v_mad_co_u64_u32 v[23:24], null, v21, v9, v[3:4]2789; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)2790; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v7, vcc_lo2791; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2792; GFX12-NEXT: v_mad_co_u64_u32 v[4:5], vcc_lo, v20, v8, v[1:2]2793; GFX12-NEXT: v_mad_co_u64_u32 v[6:7], null, v0, v8, v[23:24]2794; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], s0, v17, v9, v[25:26]2795; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)2796; GFX12-NEXT: v_add_co_ci_u32_e64 v25, null, 0, v3, vcc_lo2797; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2798; GFX12-NEXT: v_cndmask_b32_e64 v28, 0, 1, s02799; GFX12-NEXT: v_mul_lo_u32 v26, v21, v102800; GFX12-NEXT: v_mad_co_u64_u32 v[23:24], vcc_lo, v16, v13, v[5:6]2801; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], s0, v18, v8, v[0:1]2802; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2803; GFX12-NEXT: v_add_co_ci_u32_e64 v28, null, 0, v28, s02804; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v16, v8, 02805; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2806; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], s1, v17, v12, v[23:24]2807; GFX12-NEXT: v_mad_co_u64_u32 v[23:24], s2, v16, v11, v[3:4]2808; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2809; GFX12-NEXT: v_cndmask_b32_e64 v14, 0, 1, s22810; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2811; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], s0, v18, v11, v[5:6]2812; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], s2, v17, v10, v[23:24]2813; GFX12-NEXT: v_mul_lo_u32 v23, v19, v122814; GFX12-NEXT: v_mul_lo_u32 v24, v18, v132815; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)2816; GFX12-NEXT: v_mad_co_u64_u32 v[11:12], s3, v19, v10, v[3:4]2817; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2818; GFX12-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v14, s22819; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], s2, v18, v9, v[5:6]2820; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2821; GFX12-NEXT: v_add_co_ci_u32_e64 v14, null, 0, v10, s22822; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)2823; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], s2, v20, v9, v[11:12]2824; GFX12-NEXT: v_mad_co_u64_u32 v[10:11], s4, v16, v9, v[1:2]2825; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2826; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, s42827; GFX12-NEXT: v_mad_co_u64_u32 v[12:13], s4, v19, v8, v[3:4]2828; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2829; GFX12-NEXT: v_add_co_ci_u32_e64 v16, null, 0, v14, s42830; GFX12-NEXT: v_mad_co_u64_u32 v[14:15], s4, v21, v8, v[5:6]2831; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], s5, v17, v8, v[10:11]2832; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2833; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)2834; GFX12-NEXT: v_add_co_ci_u32_e64 v3, s5, v9, v12, s52835; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2836; GFX12-NEXT: v_add_co_ci_u32_e64 v4, s5, v28, v13, s52837; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2838; GFX12-NEXT: v_add_co_ci_u32_e64 v5, s5, v16, v14, s52839; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2840; GFX12-NEXT: v_add_co_ci_u32_e64 v6, s5, v25, v15, s52841; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)2842; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v30, s52843; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2844; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v31, s42845; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v24, s22846; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2847; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v23, s32848; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v29, s02849; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)2850; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v26, s12851; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)2852; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v27, vcc_lo2853; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)2854; GFX12-NEXT: v_mad_co_u64_u32 v[7:8], null, v22, v8, v[7:8]2855; GFX12-NEXT: s_setpc_b64 s[30:31]2856;2857; GFX1250-LABEL: v_mul_i256:2858; GFX1250: ; %bb.0:2859; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02860; GFX1250-NEXT: s_wait_kmcnt 0x02861; GFX1250-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v12862; GFX1250-NEXT: v_mul_lo_u32 v30, v4, v112863; GFX1250-NEXT: v_mul_lo_u32 v29, v5, v102864; GFX1250-NEXT: v_mul_lo_u32 v31, v3, v122865; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)2866; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v16, v14, 02867; GFX1250-NEXT: v_mul_lo_u32 v32, v2, v132868; GFX1250-NEXT: v_mad_nc_u64_u32 v[18:19], v17, v13, v[0:1]2869; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v16, v12, 02870; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2871; GFX1250-NEXT: v_mad_nc_u64_u32 v[20:21], v2, v12, v[18:19]2872; GFX1250-NEXT: v_mad_co_u64_u32 v[18:19], s0, v17, v11, v[0:1]2873; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)2874; GFX1250-NEXT: v_cndmask_b32_e64 v22, 0, 1, s02875; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v3, v11, v[20:21]2876; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)2877; GFX1250-NEXT: v_mad_co_u64_u32 v[20:21], vcc_lo, v2, v10, v[18:19]2878; GFX1250-NEXT: v_add_co_ci_u32_e64 v22, null, 0, v22, vcc_lo2879; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2880; GFX1250-NEXT: v_mad_nc_u64_u32 v[18:19], v4, v10, v[0:1]2881; GFX1250-NEXT: v_mad_co_u64_u32 v[0:1], vcc_lo, v3, v9, v[20:21]2882; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)2883; GFX1250-NEXT: v_add_co_ci_u32_e64 v26, null, 0, v22, vcc_lo2884; GFX1250-NEXT: v_mad_nc_u64_u32 v[20:21], v5, v9, v[18:19]2885; GFX1250-NEXT: v_mad_nc_u64_u32 v[18:19], v16, v10, 02886; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)2887; GFX1250-NEXT: v_mad_co_u64_u32 v[22:23], vcc_lo, v4, v8, v[0:1]2888; GFX1250-NEXT: v_add_co_ci_u32_e64 v28, null, 0, v26, vcc_lo2889; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2890; GFX1250-NEXT: v_mad_nc_u64_u32 v[24:25], v6, v8, v[20:21]2891; GFX1250-NEXT: v_mad_co_u64_u32 v[0:1], s0, v17, v9, v[18:19]2892; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)2893; GFX1250-NEXT: v_dual_mov_b32 v18, v23 :: v_dual_mov_b32 v19, v242894; GFX1250-NEXT: v_mul_lo_u32 v24, v6, v92895; GFX1250-NEXT: v_cndmask_b32_e64 v6, 0, 1, s02896; GFX1250-NEXT: v_mad_co_u64_u32 v[20:21], vcc_lo, v16, v13, v[18:19]2897; GFX1250-NEXT: v_mad_co_u64_u32 v[18:19], s0, v2, v8, v[0:1]2898; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)2899; GFX1250-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v6, s02900; GFX1250-NEXT: v_mad_co_u64_u32 v[0:1], s0, v17, v12, v[20:21]2901; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2902; GFX1250-NEXT: v_dual_mov_b32 v20, v19 :: v_dual_mov_b32 v21, v222903; GFX1250-NEXT: v_mov_b32_e32 v13, v182904; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)2905; GFX1250-NEXT: v_mad_co_u64_u32 v[22:23], s2, v16, v11, v[20:21]2906; GFX1250-NEXT: v_mad_co_u64_u32 v[20:21], s1, v2, v11, v[0:1]2907; GFX1250-NEXT: v_cndmask_b32_e64 v11, 0, 1, s22908; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v16, v8, 02909; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)2910; GFX1250-NEXT: v_mad_co_u64_u32 v[26:27], s2, v17, v10, v[22:23]2911; GFX1250-NEXT: v_add_co_ci_u32_e64 v33, null, 0, v11, s22912; GFX1250-NEXT: v_mad_co_u64_u32 v[22:23], s3, v3, v10, v[20:21]2913; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)2914; GFX1250-NEXT: v_mov_b32_e32 v12, v12915; GFX1250-NEXT: v_mad_co_u64_u32 v[10:11], s2, v2, v9, v[26:27]2916; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)2917; GFX1250-NEXT: v_mad_co_u64_u32 v[20:21], s6, v16, v9, v[12:13]2918; GFX1250-NEXT: v_mad_co_u64_u32 v[18:19], s4, v4, v9, v[22:23]2919; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v33, s22920; GFX1250-NEXT: v_mul_lo_u32 v2, v16, v152921; GFX1250-NEXT: v_mul_lo_u32 v9, v17, v142922; GFX1250-NEXT: v_mad_co_u64_u32 v[12:13], s2, v3, v8, v[10:11]2923; GFX1250-NEXT: v_cndmask_b32_e64 v3, 0, 1, s62924; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, s22925; GFX1250-NEXT: v_mad_co_u64_u32 v[10:11], s5, v5, v8, v[18:19]2926; GFX1250-NEXT: v_mad_co_u64_u32 v[14:15], s2, v17, v8, v[20:21]2927; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2928; GFX1250-NEXT: v_add_co_ci_u32_e64 v3, s2, v3, v12, s22929; GFX1250-NEXT: v_add_co_ci_u32_e64 v4, s2, v6, v13, s22930; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2931; GFX1250-NEXT: v_add_co_ci_u32_e64 v5, s2, v1, v10, s22932; GFX1250-NEXT: v_add_co_ci_u32_e64 v6, s2, v28, v11, s22933; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2934; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v25, v2, s22935; GFX1250-NEXT: v_mov_b32_e32 v2, v152936; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v9, s52937; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2938; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v32, s42939; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v31, s32940; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2941; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v30, s12942; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v29, s02943; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2944; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v24, vcc_lo2945; GFX1250-NEXT: v_mad_u32 v7, v7, v8, v12946; GFX1250-NEXT: v_mov_b32_e32 v1, v142947; GFX1250-NEXT: s_set_pc_i64 s[30:31]2948 %result = mul i256 %num, %den2949 ret i256 %result2950}2951 2952define amdgpu_ps void @s_mul_u64_zext_with_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {2953; GFX7-LABEL: s_mul_u64_zext_with_vregs:2954; GFX7: ; %bb.0:2955; GFX7-NEXT: s_mov_b32 s2, 02956; GFX7-NEXT: s_mov_b32 s3, 0xf0002957; GFX7-NEXT: s_mov_b64 s[0:1], 02958; GFX7-NEXT: buffer_load_dword v4, v[2:3], s[0:3], 0 addr642959; GFX7-NEXT: v_mov_b32_e32 v5, 0x502960; GFX7-NEXT: s_waitcnt vmcnt(0)2961; GFX7-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v5, 02962; GFX7-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr642963; GFX7-NEXT: s_endpgm2964;2965; GFX8-LABEL: s_mul_u64_zext_with_vregs:2966; GFX8: ; %bb.0:2967; GFX8-NEXT: flat_load_dword v4, v[2:3]2968; GFX8-NEXT: v_mov_b32_e32 v5, 0x502969; GFX8-NEXT: s_waitcnt vmcnt(0)2970; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v5, 02971; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]2972; GFX8-NEXT: s_endpgm2973;2974; GFX9-LABEL: s_mul_u64_zext_with_vregs:2975; GFX9: ; %bb.0:2976; GFX9-NEXT: global_load_dword v4, v[2:3], off2977; GFX9-NEXT: v_mov_b32_e32 v5, 0x502978; GFX9-NEXT: s_waitcnt vmcnt(0)2979; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v5, 02980; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off2981; GFX9-NEXT: s_endpgm2982;2983; GFX10-LABEL: s_mul_u64_zext_with_vregs:2984; GFX10: ; %bb.0:2985; GFX10-NEXT: global_load_dword v4, v[2:3], off2986; GFX10-NEXT: s_waitcnt vmcnt(0)2987; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, 0x50, v4, 02988; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off2989; GFX10-NEXT: s_endpgm2990;2991; GFX11-LABEL: s_mul_u64_zext_with_vregs:2992; GFX11: ; %bb.0:2993; GFX11-NEXT: global_load_b32 v4, v[2:3], off2994; GFX11-NEXT: s_waitcnt vmcnt(0)2995; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0x50, v4, 02996; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off2997; GFX11-NEXT: s_endpgm2998;2999; GFX12-LABEL: s_mul_u64_zext_with_vregs:3000; GFX12: ; %bb.0:3001; GFX12-NEXT: global_load_b32 v4, v[2:3], off3002; GFX12-NEXT: s_wait_loadcnt 0x03003; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, 0x50, v4, 03004; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off3005; GFX12-NEXT: s_endpgm3006;3007; GFX1250-LABEL: s_mul_u64_zext_with_vregs:3008; GFX1250: ; %bb.0:3009; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13010; GFX1250-NEXT: global_load_b32 v4, v[2:3], off3011; GFX1250-NEXT: s_wait_loadcnt 0x03012; GFX1250-NEXT: v_mad_nc_u64_u32 v[2:3], 0x50, v4, 03013; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off3014; GFX1250-NEXT: s_endpgm3015 %val = load i32, ptr addrspace(1) %in, align 43016 %ext = zext i32 %val to i643017 %mul = mul i64 %ext, 803018 store i64 %mul, ptr addrspace(1) %out, align 83019 ret void3020}3021 3022define amdgpu_kernel void @s_mul_u64_zext_with_sregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {3023; GFX7-LABEL: s_mul_u64_zext_with_sregs:3024; GFX7: ; %bb.0:3025; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x93026; GFX7-NEXT: v_mov_b32_e32 v0, 0x503027; GFX7-NEXT: s_waitcnt lgkmcnt(0)3028; GFX7-NEXT: s_load_dword s3, s[2:3], 0x03029; GFX7-NEXT: s_mov_b32 s2, -13030; GFX7-NEXT: s_waitcnt lgkmcnt(0)3031; GFX7-NEXT: v_mul_hi_u32 v0, s3, v03032; GFX7-NEXT: s_mul_i32 s4, s3, 0x503033; GFX7-NEXT: s_mov_b32 s3, 0xf0003034; GFX7-NEXT: v_readfirstlane_b32 s5, v03035; GFX7-NEXT: v_mov_b32_e32 v0, s43036; GFX7-NEXT: v_mov_b32_e32 v1, s53037; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 03038; GFX7-NEXT: s_endpgm3039;3040; GFX8-LABEL: s_mul_u64_zext_with_sregs:3041; GFX8: ; %bb.0:3042; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x243043; GFX8-NEXT: v_mov_b32_e32 v0, 0x503044; GFX8-NEXT: s_waitcnt lgkmcnt(0)3045; GFX8-NEXT: s_load_dword s2, s[2:3], 0x03046; GFX8-NEXT: v_mov_b32_e32 v3, s13047; GFX8-NEXT: v_mov_b32_e32 v2, s03048; GFX8-NEXT: s_waitcnt lgkmcnt(0)3049; GFX8-NEXT: v_mul_hi_u32 v0, s2, v03050; GFX8-NEXT: s_mulk_i32 s2, 0x503051; GFX8-NEXT: v_readfirstlane_b32 s3, v03052; GFX8-NEXT: v_mov_b32_e32 v0, s23053; GFX8-NEXT: v_mov_b32_e32 v1, s33054; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]3055; GFX8-NEXT: s_endpgm3056;3057; GFX9-LABEL: s_mul_u64_zext_with_sregs:3058; GFX9: ; %bb.0:3059; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x243060; GFX9-NEXT: v_mov_b32_e32 v2, 03061; GFX9-NEXT: s_waitcnt lgkmcnt(0)3062; GFX9-NEXT: s_load_dword s3, s[2:3], 0x03063; GFX9-NEXT: s_waitcnt lgkmcnt(0)3064; GFX9-NEXT: s_mul_i32 s2, s3, 0x503065; GFX9-NEXT: s_mul_hi_u32 s3, s3, 0x503066; GFX9-NEXT: v_mov_b32_e32 v0, s23067; GFX9-NEXT: v_mov_b32_e32 v1, s33068; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]3069; GFX9-NEXT: s_endpgm3070;3071; GFX10-LABEL: s_mul_u64_zext_with_sregs:3072; GFX10: ; %bb.0:3073; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x243074; GFX10-NEXT: v_mov_b32_e32 v2, 03075; GFX10-NEXT: s_waitcnt lgkmcnt(0)3076; GFX10-NEXT: s_load_dword s3, s[2:3], 0x03077; GFX10-NEXT: s_waitcnt lgkmcnt(0)3078; GFX10-NEXT: s_mul_i32 s2, s3, 0x503079; GFX10-NEXT: s_mul_hi_u32 s3, s3, 0x503080; GFX10-NEXT: v_mov_b32_e32 v0, s23081; GFX10-NEXT: v_mov_b32_e32 v1, s33082; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]3083; GFX10-NEXT: s_endpgm3084;3085; GFX11-LABEL: s_mul_u64_zext_with_sregs:3086; GFX11: ; %bb.0:3087; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x243088; GFX11-NEXT: v_mov_b32_e32 v2, 03089; GFX11-NEXT: s_waitcnt lgkmcnt(0)3090; GFX11-NEXT: s_load_b32 s3, s[2:3], 0x03091; GFX11-NEXT: s_waitcnt lgkmcnt(0)3092; GFX11-NEXT: s_mul_i32 s2, s3, 0x503093; GFX11-NEXT: s_mul_hi_u32 s3, s3, 0x503094; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33095; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]3096; GFX11-NEXT: s_endpgm3097;3098; GFX12-LABEL: s_mul_u64_zext_with_sregs:3099; GFX12: ; %bb.0:3100; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x243101; GFX12-NEXT: v_mov_b32_e32 v2, 03102; GFX12-NEXT: s_wait_kmcnt 0x03103; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x03104; GFX12-NEXT: s_mov_b32 s3, 03105; GFX12-NEXT: s_wait_kmcnt 0x03106; GFX12-NEXT: s_mul_u64 s[2:3], s[2:3], 0x503107; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3108; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33109; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]3110; GFX12-NEXT: s_endpgm3111;3112; GFX1250-LABEL: s_mul_u64_zext_with_sregs:3113; GFX1250: ; %bb.0:3114; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13115; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x243116; GFX1250-NEXT: v_mov_b32_e32 v2, 03117; GFX1250-NEXT: s_wait_kmcnt 0x03118; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x03119; GFX1250-NEXT: s_wait_xcnt 0x03120; GFX1250-NEXT: s_mov_b32 s3, 03121; GFX1250-NEXT: s_wait_kmcnt 0x03122; GFX1250-NEXT: s_mul_u64 s[2:3], s[2:3], 0x503123; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3124; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]3125; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]3126; GFX1250-NEXT: s_endpgm3127 %val = load i32, ptr addrspace(1) %in, align 43128 %ext = zext i32 %val to i643129 %mul = mul i64 %ext, 803130 store i64 %mul, ptr addrspace(1) %out, align 83131 ret void3132}3133 3134define amdgpu_ps void @s_mul_u64_sext_with_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {3135; GFX7-LABEL: s_mul_u64_sext_with_vregs:3136; GFX7: ; %bb.0:3137; GFX7-NEXT: s_mov_b32 s2, 03138; GFX7-NEXT: s_mov_b32 s3, 0xf0003139; GFX7-NEXT: s_mov_b64 s[0:1], 03140; GFX7-NEXT: buffer_load_dword v4, v[2:3], s[0:3], 0 addr643141; GFX7-NEXT: v_mov_b32_e32 v6, 0x503142; GFX7-NEXT: s_waitcnt vmcnt(0)3143; GFX7-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v6, 03144; GFX7-NEXT: v_ashrrev_i32_e32 v7, 31, v43145; GFX7-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v6, v[3:4]3146; GFX7-NEXT: v_mov_b32_e32 v3, v43147; GFX7-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr643148; GFX7-NEXT: s_endpgm3149;3150; GFX8-LABEL: s_mul_u64_sext_with_vregs:3151; GFX8: ; %bb.0:3152; GFX8-NEXT: flat_load_dword v4, v[2:3]3153; GFX8-NEXT: v_mov_b32_e32 v6, 0x503154; GFX8-NEXT: s_waitcnt vmcnt(0)3155; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v6, 03156; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v43157; GFX8-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v7, v6, v[3:4]3158; GFX8-NEXT: v_mov_b32_e32 v3, v43159; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]3160; GFX8-NEXT: s_endpgm3161;3162; GFX9-LABEL: s_mul_u64_sext_with_vregs:3163; GFX9: ; %bb.0:3164; GFX9-NEXT: global_load_dword v4, v[2:3], off3165; GFX9-NEXT: v_mov_b32_e32 v6, 0x503166; GFX9-NEXT: s_waitcnt vmcnt(0)3167; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v6, 03168; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v43169; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v7, v6, v[3:4]3170; GFX9-NEXT: v_mov_b32_e32 v3, v43171; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off3172; GFX9-NEXT: s_endpgm3173;3174; GFX10-LABEL: s_mul_u64_sext_with_vregs:3175; GFX10: ; %bb.0:3176; GFX10-NEXT: global_load_dword v4, v[2:3], off3177; GFX10-NEXT: s_waitcnt vmcnt(0)3178; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, 0x50, v4, 03179; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v43180; GFX10-NEXT: v_mad_u64_u32 v[3:4], s0, 0x50, v4, v[3:4]3181; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off3182; GFX10-NEXT: s_endpgm3183;3184; GFX11-LABEL: s_mul_u64_sext_with_vregs:3185; GFX11: ; %bb.0:3186; GFX11-NEXT: global_load_b32 v4, v[2:3], off3187; GFX11-NEXT: s_waitcnt vmcnt(0)3188; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0x50, v4, 03189; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v43190; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, 0x50, v6, v[3:4]3191; GFX11-NEXT: v_mov_b32_e32 v3, v43192; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off3193; GFX11-NEXT: s_endpgm3194;3195; GFX12-LABEL: s_mul_u64_sext_with_vregs:3196; GFX12: ; %bb.0:3197; GFX12-NEXT: global_load_b32 v4, v[2:3], off3198; GFX12-NEXT: s_wait_loadcnt 0x03199; GFX12-NEXT: v_mad_co_i64_i32 v[2:3], null, 0x50, v4, 03200; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off3201; GFX12-NEXT: s_endpgm3202;3203; GFX1250-LABEL: s_mul_u64_sext_with_vregs:3204; GFX1250: ; %bb.0:3205; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13206; GFX1250-NEXT: global_load_b32 v4, v[2:3], off3207; GFX1250-NEXT: s_wait_loadcnt 0x03208; GFX1250-NEXT: v_mad_nc_i64_i32 v[2:3], 0x50, v4, 03209; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off3210; GFX1250-NEXT: s_endpgm3211 %val = load i32, ptr addrspace(1) %in, align 43212 %ext = sext i32 %val to i643213 %mul = mul i64 %ext, 803214 store i64 %mul, ptr addrspace(1) %out, align 83215 ret void3216}3217 3218define amdgpu_kernel void @s_mul_u64_sext_with_sregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {3219; GFX7-LABEL: s_mul_u64_sext_with_sregs:3220; GFX7: ; %bb.0:3221; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x93222; GFX7-NEXT: v_mov_b32_e32 v0, 0x503223; GFX7-NEXT: s_waitcnt lgkmcnt(0)3224; GFX7-NEXT: s_load_dword s3, s[2:3], 0x03225; GFX7-NEXT: s_mov_b32 s2, -13226; GFX7-NEXT: s_waitcnt lgkmcnt(0)3227; GFX7-NEXT: v_mul_hi_u32 v0, s3, v03228; GFX7-NEXT: s_ashr_i32 s5, s3, 313229; GFX7-NEXT: s_mul_i32 s4, s3, 0x503230; GFX7-NEXT: s_mulk_i32 s5, 0x503231; GFX7-NEXT: v_readfirstlane_b32 s3, v03232; GFX7-NEXT: s_add_u32 s5, s5, s33233; GFX7-NEXT: v_mov_b32_e32 v0, s43234; GFX7-NEXT: v_mov_b32_e32 v1, s53235; GFX7-NEXT: s_mov_b32 s3, 0xf0003236; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 03237; GFX7-NEXT: s_endpgm3238;3239; GFX8-LABEL: s_mul_u64_sext_with_sregs:3240; GFX8: ; %bb.0:3241; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x243242; GFX8-NEXT: v_mov_b32_e32 v0, 0x503243; GFX8-NEXT: s_waitcnt lgkmcnt(0)3244; GFX8-NEXT: s_load_dword s2, s[2:3], 0x03245; GFX8-NEXT: v_mov_b32_e32 v3, s13246; GFX8-NEXT: v_mov_b32_e32 v2, s03247; GFX8-NEXT: s_waitcnt lgkmcnt(0)3248; GFX8-NEXT: v_mul_hi_u32 v0, s2, v03249; GFX8-NEXT: s_ashr_i32 s3, s2, 313250; GFX8-NEXT: s_mulk_i32 s2, 0x503251; GFX8-NEXT: s_mulk_i32 s3, 0x503252; GFX8-NEXT: v_readfirstlane_b32 s4, v03253; GFX8-NEXT: s_add_u32 s3, s3, s43254; GFX8-NEXT: v_mov_b32_e32 v0, s23255; GFX8-NEXT: v_mov_b32_e32 v1, s33256; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]3257; GFX8-NEXT: s_endpgm3258;3259; GFX9-LABEL: s_mul_u64_sext_with_sregs:3260; GFX9: ; %bb.0:3261; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x243262; GFX9-NEXT: v_mov_b32_e32 v2, 03263; GFX9-NEXT: s_waitcnt lgkmcnt(0)3264; GFX9-NEXT: s_load_dword s3, s[2:3], 0x03265; GFX9-NEXT: s_waitcnt lgkmcnt(0)3266; GFX9-NEXT: s_ashr_i32 s4, s3, 313267; GFX9-NEXT: s_mul_i32 s2, s3, 0x503268; GFX9-NEXT: s_mul_hi_u32 s3, s3, 0x503269; GFX9-NEXT: s_mulk_i32 s4, 0x503270; GFX9-NEXT: s_add_u32 s3, s4, s33271; GFX9-NEXT: v_mov_b32_e32 v0, s23272; GFX9-NEXT: v_mov_b32_e32 v1, s33273; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]3274; GFX9-NEXT: s_endpgm3275;3276; GFX10-LABEL: s_mul_u64_sext_with_sregs:3277; GFX10: ; %bb.0:3278; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x243279; GFX10-NEXT: v_mov_b32_e32 v2, 03280; GFX10-NEXT: s_waitcnt lgkmcnt(0)3281; GFX10-NEXT: s_load_dword s2, s[2:3], 0x03282; GFX10-NEXT: s_waitcnt lgkmcnt(0)3283; GFX10-NEXT: s_ashr_i32 s3, s2, 313284; GFX10-NEXT: s_mul_hi_u32 s4, s2, 0x503285; GFX10-NEXT: s_mulk_i32 s3, 0x503286; GFX10-NEXT: s_mulk_i32 s2, 0x503287; GFX10-NEXT: s_add_i32 s3, s4, s33288; GFX10-NEXT: v_mov_b32_e32 v0, s23289; GFX10-NEXT: v_mov_b32_e32 v1, s33290; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]3291; GFX10-NEXT: s_endpgm3292;3293; GFX11-LABEL: s_mul_u64_sext_with_sregs:3294; GFX11: ; %bb.0:3295; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x243296; GFX11-NEXT: v_mov_b32_e32 v2, 03297; GFX11-NEXT: s_waitcnt lgkmcnt(0)3298; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x03299; GFX11-NEXT: s_waitcnt lgkmcnt(0)3300; GFX11-NEXT: s_ashr_i32 s3, s2, 313301; GFX11-NEXT: s_mul_hi_u32 s4, s2, 0x503302; GFX11-NEXT: s_mulk_i32 s3, 0x503303; GFX11-NEXT: s_mulk_i32 s2, 0x503304; GFX11-NEXT: s_add_i32 s3, s4, s33305; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33306; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]3307; GFX11-NEXT: s_endpgm3308;3309; GFX12-LABEL: s_mul_u64_sext_with_sregs:3310; GFX12: ; %bb.0:3311; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x243312; GFX12-NEXT: v_mov_b32_e32 v2, 03313; GFX12-NEXT: s_wait_kmcnt 0x03314; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x03315; GFX12-NEXT: s_wait_kmcnt 0x03316; GFX12-NEXT: s_ashr_i32 s3, s2, 313317; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)3318; GFX12-NEXT: s_mul_u64 s[2:3], s[2:3], 0x503319; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33320; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]3321; GFX12-NEXT: s_endpgm3322;3323; GFX1250-LABEL: s_mul_u64_sext_with_sregs:3324; GFX1250: ; %bb.0:3325; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13326; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x243327; GFX1250-NEXT: v_mov_b32_e32 v2, 03328; GFX1250-NEXT: s_wait_kmcnt 0x03329; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x03330; GFX1250-NEXT: s_wait_kmcnt 0x03331; GFX1250-NEXT: s_ashr_i32 s3, s2, 313332; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)3333; GFX1250-NEXT: s_mul_u64 s[2:3], s[2:3], 0x503334; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]3335; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]3336; GFX1250-NEXT: s_endpgm3337 %val = load i32, ptr addrspace(1) %in, align 43338 %ext = sext i32 %val to i643339 %mul = mul i64 %ext, 803340 store i64 %mul, ptr addrspace(1) %out, align 83341 ret void3342}3343