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1# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - -run-pass=machine-cse %s | FileCheck %s2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - -passes=machine-cse %s | FileCheck %s3 4# LLVM's current definition of `isConvergent` does not necessarily prove that5# non-local CSE is illegal. The following test extends the definition of6# `isConvergent` to assume a convergent instruction is dependent not only on7# additional conditions, but also on fewer conditions. LLVM does not have a8# MachineInstr attribute which expresses this extended definition, so it's9# necessary to use `isConvergent` to prevent illegally CSE-ing the subset of10# `isConvergent` instructions which do fall into this extended definition.11 12# This is a coverage test for the MachineCSE change. It does not reproduce an13# actual bug in the AMDGPU backend. The current open source GPU backends as is14# do not appear to allow a reasonably simple test case that provably and15# undeniably functionally breaks without the associated MachineCSE changes.16 17# The test checks that we don't CSE non-local convergent instrs. Otherwise,18# reusing defs of convergent instrs from different control flow scopes can19# cause illegal codegen. Previously, the swizzle in bb2 would be CSE-ed in20# favor of using the swizzle in bb1 despite bb2 being a different BBs.21 22# CHECK-LABEL: name: no_cse23# CHECK: bb.1.if.then24# CHECK: [[SWIZZLE1:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[SRC:%[0-9]+]], 100, 0, implicit $exec25# CHECK-NEXT: V_ADD_CO_U32_e64 [[SWIZZLE1]], {{%[0-9]+}}, 0, implicit $exec26# CHECK-NEXT: S_CMP_LT_I32 {{.*}} implicit-def $scc27# CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc28# CHECK-NEXT: S_BRANCH %bb.229# CHECK: bb.2.if.then.if.then30# CHECK: [[SWIZZLE2:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[SRC]], 100, 0, implicit $exec31# CHECK-NEXT: V_ADD_CO_U32_e64 [[SWIZZLE2]], {{%[0-9]+}}, 0, implicit $exec32 33--- |34 define amdgpu_kernel void @no_cse(ptr addrspace(1), i32, i1) {35 entry:36 unreachable37 if.then:38 unreachable39 if.then.if.then:40 unreachable41 if.then.phi:42 unreachable43 exit:44 unreachable45 }46...47---48name: no_cse49tracksRegLiveness: true50body: |51 bb.0.entry:52 liveins: $sgpr4_sgpr553 %0:sgpr_64(p4) = COPY $sgpr4_sgpr554 %1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0(p4), 0, 055 %2:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0(p4), 2, 056 %3:sreg_64 = COPY %157 %4:sreg_32 = COPY %2.sub158 %5:sreg_32 = S_MOV_B32 4259 S_CMP_EQ_U32 %4, %5, implicit-def $scc60 %6:vgpr_32 = COPY %5, implicit $exec61 S_CBRANCH_SCC1 %bb.4, implicit $scc62 S_BRANCH %bb.163 64 bb.1.if.then:65 %7:sreg_32 = COPY %2.sub066 %8:vgpr_32 = COPY %767 %9:vgpr_32 = DS_SWIZZLE_B32 %8, 100, 0, implicit $exec68 %10:vgpr_32, %21:sreg_32 = V_ADD_CO_U32_e64 %9, %5, 0, implicit $exec69 S_CMP_LT_I32 %7, %5, implicit-def $scc70 S_CBRANCH_SCC1 %bb.3, implicit $scc71 S_BRANCH %bb.272 73 bb.2.if.then.if.then:74 %11:sreg_32 = S_MOV_B32 6475 %12:vgpr_32 = DS_SWIZZLE_B32 %8, 100, 0, implicit $exec76 %13:vgpr_32, %24:sreg_32 = V_ADD_CO_U32_e64 %12, %11, 0, implicit $exec77 78 bb.3.if.then.phi:79 %14:vgpr_32 = PHI %10, %bb.1, %13, %bb.280 81 bb.4.exit:82 %15:vgpr_32 = PHI %6, %bb.0, %14, %bb.383 %16:vreg_64 = COPY %384 FLAT_STORE_DWORD %16, %15, 0, 0, implicit $exec, implicit $flat_scr85 S_ENDPGM 086 87...88