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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s5; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s6 7define amdgpu_ps i32 @s_orn2_i32(i32 inreg %src0, i32 inreg %src1) {8; GCN-LABEL: s_orn2_i32:9; GCN: ; %bb.0:10; GCN-NEXT: s_orn2_b32 s0, s2, s311; GCN-NEXT: ; return to shader part epilog12;13; GFX10-LABEL: s_orn2_i32:14; GFX10: ; %bb.0:15; GFX10-NEXT: s_orn2_b32 s0, s2, s316; GFX10-NEXT: ; return to shader part epilog17;18; GFX11-LABEL: s_orn2_i32:19; GFX11: ; %bb.0:20; GFX11-NEXT: s_or_not1_b32 s0, s2, s321; GFX11-NEXT: ; return to shader part epilog22 %not.src1 = xor i32 %src1, -123 %or = or i32 %src0, %not.src124 ret i32 %or25}26 27define amdgpu_ps i32 @s_orn2_i32_commute(i32 inreg %src0, i32 inreg %src1) {28; GCN-LABEL: s_orn2_i32_commute:29; GCN: ; %bb.0:30; GCN-NEXT: s_orn2_b32 s0, s2, s331; GCN-NEXT: ; return to shader part epilog32;33; GFX10-LABEL: s_orn2_i32_commute:34; GFX10: ; %bb.0:35; GFX10-NEXT: s_orn2_b32 s0, s2, s336; GFX10-NEXT: ; return to shader part epilog37;38; GFX11-LABEL: s_orn2_i32_commute:39; GFX11: ; %bb.0:40; GFX11-NEXT: s_or_not1_b32 s0, s2, s341; GFX11-NEXT: ; return to shader part epilog42 %not.src1 = xor i32 %src1, -143 %or = or i32 %not.src1, %src044 ret i32 %or45}46 47define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_use(i32 inreg %src0, i32 inreg %src1) {48; GCN-LABEL: s_orn2_i32_multi_use:49; GCN: ; %bb.0:50; GCN-NEXT: s_not_b32 s1, s351; GCN-NEXT: s_orn2_b32 s0, s2, s352; GCN-NEXT: ; return to shader part epilog53;54; GFX10-LABEL: s_orn2_i32_multi_use:55; GFX10: ; %bb.0:56; GFX10-NEXT: s_orn2_b32 s0, s2, s357; GFX10-NEXT: s_not_b32 s1, s358; GFX10-NEXT: ; return to shader part epilog59;60; GFX11-LABEL: s_orn2_i32_multi_use:61; GFX11: ; %bb.0:62; GFX11-NEXT: s_or_not1_b32 s0, s2, s363; GFX11-NEXT: s_not_b32 s1, s364; GFX11-NEXT: ; return to shader part epilog65 %not.src1 = xor i32 %src1, -166 %or = or i32 %src0, %not.src167 %insert.0 = insertvalue { i32, i32 } poison, i32 %or, 068 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 169 ret { i32, i32 } %insert.170}71 72define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_foldable_use(i32 inreg %src0, i32 inreg %src1, i32 inreg %src2) {73; GCN-LABEL: s_orn2_i32_multi_foldable_use:74; GCN: ; %bb.0:75; GCN-NEXT: s_orn2_b32 s0, s2, s476; GCN-NEXT: s_orn2_b32 s1, s3, s477; GCN-NEXT: ; return to shader part epilog78;79; GFX10-LABEL: s_orn2_i32_multi_foldable_use:80; GFX10: ; %bb.0:81; GFX10-NEXT: s_orn2_b32 s0, s2, s482; GFX10-NEXT: s_orn2_b32 s1, s3, s483; GFX10-NEXT: ; return to shader part epilog84;85; GFX11-LABEL: s_orn2_i32_multi_foldable_use:86; GFX11: ; %bb.0:87; GFX11-NEXT: s_or_not1_b32 s0, s2, s488; GFX11-NEXT: s_or_not1_b32 s1, s3, s489; GFX11-NEXT: ; return to shader part epilog90 %not.src2 = xor i32 %src2, -191 %or0 = or i32 %src0, %not.src292 %or1 = or i32 %src1, %not.src293 %insert.0 = insertvalue { i32, i32 } poison, i32 %or0, 094 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %or1, 195 ret { i32, i32 } %insert.196}97 98define i32 @v_orn2_i32(i32 %src0, i32 %src1) {99; GCN-LABEL: v_orn2_i32:100; GCN: ; %bb.0:101; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)102; GCN-NEXT: v_bfi_b32 v0, v1, v0, -1103; GCN-NEXT: s_setpc_b64 s[30:31]104;105; GFX10PLUS-LABEL: v_orn2_i32:106; GFX10PLUS: ; %bb.0:107; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; GFX10PLUS-NEXT: v_bfi_b32 v0, v1, v0, -1109; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]110 %not.src1 = xor i32 %src1, -1111 %or = or i32 %src0, %not.src1112 ret i32 %or113}114 115define amdgpu_ps float @v_orn2_i32_sv(i32 inreg %src0, i32 %src1) {116; GCN-LABEL: v_orn2_i32_sv:117; GCN: ; %bb.0:118; GCN-NEXT: v_bfi_b32 v0, v0, s2, -1119; GCN-NEXT: ; return to shader part epilog120;121; GFX10PLUS-LABEL: v_orn2_i32_sv:122; GFX10PLUS: ; %bb.0:123; GFX10PLUS-NEXT: v_bfi_b32 v0, v0, s2, -1124; GFX10PLUS-NEXT: ; return to shader part epilog125 %not.src1 = xor i32 %src1, -1126 %or = or i32 %src0, %not.src1127 %cast = bitcast i32 %or to float128 ret float %cast129}130 131define amdgpu_ps float @v_orn2_i32_vs(i32 %src0, i32 inreg %src1) {132; GCN-LABEL: v_orn2_i32_vs:133; GCN: ; %bb.0:134; GCN-NEXT: v_bfi_b32 v0, s2, v0, -1135; GCN-NEXT: ; return to shader part epilog136;137; GFX10PLUS-LABEL: v_orn2_i32_vs:138; GFX10PLUS: ; %bb.0:139; GFX10PLUS-NEXT: v_bfi_b32 v0, s2, v0, -1140; GFX10PLUS-NEXT: ; return to shader part epilog141 %not.src1 = xor i32 %src1, -1142 %or = or i32 %src0, %not.src1143 %cast = bitcast i32 %or to float144 ret float %cast145}146 147define amdgpu_ps i64 @s_orn2_i64(i64 inreg %src0, i64 inreg %src1) {148; GCN-LABEL: s_orn2_i64:149; GCN: ; %bb.0:150; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]151; GCN-NEXT: ; return to shader part epilog152;153; GFX10-LABEL: s_orn2_i64:154; GFX10: ; %bb.0:155; GFX10-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]156; GFX10-NEXT: ; return to shader part epilog157;158; GFX11-LABEL: s_orn2_i64:159; GFX11: ; %bb.0:160; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5]161; GFX11-NEXT: ; return to shader part epilog162 %not.src1 = xor i64 %src1, -1163 %or = or i64 %src0, %not.src1164 ret i64 %or165}166 167define amdgpu_ps i64 @s_orn2_i64_commute(i64 inreg %src0, i64 inreg %src1) {168; GCN-LABEL: s_orn2_i64_commute:169; GCN: ; %bb.0:170; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]171; GCN-NEXT: ; return to shader part epilog172;173; GFX10-LABEL: s_orn2_i64_commute:174; GFX10: ; %bb.0:175; GFX10-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]176; GFX10-NEXT: ; return to shader part epilog177;178; GFX11-LABEL: s_orn2_i64_commute:179; GFX11: ; %bb.0:180; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5]181; GFX11-NEXT: ; return to shader part epilog182 %not.src1 = xor i64 %src1, -1183 %or = or i64 %not.src1, %src0184 ret i64 %or185}186 187define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_foldable_use(i64 inreg %src0, i64 inreg %src1, i64 inreg %src2) {188; GCN-LABEL: s_orn2_i64_multi_foldable_use:189; GCN: ; %bb.0:190; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[6:7]191; GCN-NEXT: s_orn2_b64 s[2:3], s[4:5], s[6:7]192; GCN-NEXT: ; return to shader part epilog193;194; GFX10-LABEL: s_orn2_i64_multi_foldable_use:195; GFX10: ; %bb.0:196; GFX10-NEXT: s_orn2_b64 s[0:1], s[2:3], s[6:7]197; GFX10-NEXT: s_orn2_b64 s[2:3], s[4:5], s[6:7]198; GFX10-NEXT: ; return to shader part epilog199;200; GFX11-LABEL: s_orn2_i64_multi_foldable_use:201; GFX11: ; %bb.0:202; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[6:7]203; GFX11-NEXT: s_or_not1_b64 s[2:3], s[4:5], s[6:7]204; GFX11-NEXT: ; return to shader part epilog205 %not.src2 = xor i64 %src2, -1206 %or0 = or i64 %src0, %not.src2207 %or1 = or i64 %src1, %not.src2208 %insert.0 = insertvalue { i64, i64 } poison, i64 %or0, 0209 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %or1, 1210 ret { i64, i64 } %insert.1211}212 213define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_use(i64 inreg %src0, i64 inreg %src1) {214; GCN-LABEL: s_orn2_i64_multi_use:215; GCN: ; %bb.0:216; GCN-NEXT: s_not_b64 s[6:7], s[4:5]217; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]218; GCN-NEXT: s_mov_b32 s2, s6219; GCN-NEXT: s_mov_b32 s3, s7220; GCN-NEXT: ; return to shader part epilog221;222; GFX10-LABEL: s_orn2_i64_multi_use:223; GFX10: ; %bb.0:224; GFX10-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]225; GFX10-NEXT: s_not_b64 s[2:3], s[4:5]226; GFX10-NEXT: ; return to shader part epilog227;228; GFX11-LABEL: s_orn2_i64_multi_use:229; GFX11: ; %bb.0:230; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5]231; GFX11-NEXT: s_not_b64 s[2:3], s[4:5]232; GFX11-NEXT: ; return to shader part epilog233 %not.src1 = xor i64 %src1, -1234 %or = or i64 %src0, %not.src1235 %insert.0 = insertvalue { i64, i64 } poison, i64 %or, 0236 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1237 ret { i64, i64 } %insert.1238}239 240define i64 @v_orn2_i64(i64 %src0, i64 %src1) {241; GCN-LABEL: v_orn2_i64:242; GCN: ; %bb.0:243; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)244; GCN-NEXT: v_bfi_b32 v0, v2, v0, -1245; GCN-NEXT: v_bfi_b32 v1, v3, v1, -1246; GCN-NEXT: s_setpc_b64 s[30:31]247;248; GFX10PLUS-LABEL: v_orn2_i64:249; GFX10PLUS: ; %bb.0:250; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)251; GFX10PLUS-NEXT: v_bfi_b32 v0, v2, v0, -1252; GFX10PLUS-NEXT: v_bfi_b32 v1, v3, v1, -1253; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]254 %not.src1 = xor i64 %src1, -1255 %or = or i64 %src0, %not.src1256 ret i64 %or257}258 259define amdgpu_ps <2 x float> @v_orn2_i64_sv(i64 inreg %src0, i64 %src1) {260; GCN-LABEL: v_orn2_i64_sv:261; GCN: ; %bb.0:262; GCN-NEXT: v_bfi_b32 v0, v0, s2, -1263; GCN-NEXT: v_bfi_b32 v1, v1, s3, -1264; GCN-NEXT: ; return to shader part epilog265;266; GFX10PLUS-LABEL: v_orn2_i64_sv:267; GFX10PLUS: ; %bb.0:268; GFX10PLUS-NEXT: v_bfi_b32 v0, v0, s2, -1269; GFX10PLUS-NEXT: v_bfi_b32 v1, v1, s3, -1270; GFX10PLUS-NEXT: ; return to shader part epilog271 %not.src1 = xor i64 %src1, -1272 %or = or i64 %src0, %not.src1273 %cast = bitcast i64 %or to <2 x float>274 ret <2 x float> %cast275}276 277define amdgpu_ps <2 x float> @v_orn2_i64_vs(i64 %src0, i64 inreg %src1) {278; GCN-LABEL: v_orn2_i64_vs:279; GCN: ; %bb.0:280; GCN-NEXT: s_not_b64 s[0:1], s[2:3]281; GCN-NEXT: v_or_b32_e32 v0, s0, v0282; GCN-NEXT: v_or_b32_e32 v1, s1, v1283; GCN-NEXT: ; return to shader part epilog284;285; GFX10PLUS-LABEL: v_orn2_i64_vs:286; GFX10PLUS: ; %bb.0:287; GFX10PLUS-NEXT: s_not_b64 s[0:1], s[2:3]288; GFX10PLUS-NEXT: v_or_b32_e32 v0, s0, v0289; GFX10PLUS-NEXT: v_or_b32_e32 v1, s1, v1290; GFX10PLUS-NEXT: ; return to shader part epilog291 %not.src1 = xor i64 %src1, -1292 %or = or i64 %src0, %not.src1293 %cast = bitcast i64 %or to <2 x float>294 ret <2 x float> %cast295}296 297define amdgpu_ps <2 x i32> @s_orn2_v2i32(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {298; GCN-LABEL: s_orn2_v2i32:299; GCN: ; %bb.0:300; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]301; GCN-NEXT: ; return to shader part epilog302;303; GFX10-LABEL: s_orn2_v2i32:304; GFX10: ; %bb.0:305; GFX10-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]306; GFX10-NEXT: ; return to shader part epilog307;308; GFX11-LABEL: s_orn2_v2i32:309; GFX11: ; %bb.0:310; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5]311; GFX11-NEXT: ; return to shader part epilog312 %not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1>313 %or = or <2 x i32> %src0, %not.src1314 ret <2 x i32> %or315}316 317define amdgpu_ps <2 x i32> @s_orn2_v2i32_commute(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {318; GCN-LABEL: s_orn2_v2i32_commute:319; GCN: ; %bb.0:320; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]321; GCN-NEXT: ; return to shader part epilog322;323; GFX10-LABEL: s_orn2_v2i32_commute:324; GFX10: ; %bb.0:325; GFX10-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]326; GFX10-NEXT: ; return to shader part epilog327;328; GFX11-LABEL: s_orn2_v2i32_commute:329; GFX11: ; %bb.0:330; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5]331; GFX11-NEXT: ; return to shader part epilog332 %not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1>333 %or = or <2 x i32> %not.src1, %src0334 ret <2 x i32> %or335}336 337define amdgpu_ps i16 @s_orn2_i16(i16 inreg %src0, i16 inreg %src1) {338; GCN-LABEL: s_orn2_i16:339; GCN: ; %bb.0:340; GCN-NEXT: s_orn2_b32 s0, s2, s3341; GCN-NEXT: ; return to shader part epilog342;343; GFX10-LABEL: s_orn2_i16:344; GFX10: ; %bb.0:345; GFX10-NEXT: s_orn2_b32 s0, s2, s3346; GFX10-NEXT: ; return to shader part epilog347;348; GFX11-LABEL: s_orn2_i16:349; GFX11: ; %bb.0:350; GFX11-NEXT: s_or_not1_b32 s0, s2, s3351; GFX11-NEXT: ; return to shader part epilog352 %not.src1 = xor i16 %src1, -1353 %or = or i16 %src0, %not.src1354 ret i16 %or355}356 357define amdgpu_ps i16 @s_orn2_i16_commute(i16 inreg %src0, i16 inreg %src1) {358; GCN-LABEL: s_orn2_i16_commute:359; GCN: ; %bb.0:360; GCN-NEXT: s_orn2_b32 s0, s2, s3361; GCN-NEXT: ; return to shader part epilog362;363; GFX10-LABEL: s_orn2_i16_commute:364; GFX10: ; %bb.0:365; GFX10-NEXT: s_orn2_b32 s0, s2, s3366; GFX10-NEXT: ; return to shader part epilog367;368; GFX11-LABEL: s_orn2_i16_commute:369; GFX11: ; %bb.0:370; GFX11-NEXT: s_or_not1_b32 s0, s2, s3371; GFX11-NEXT: ; return to shader part epilog372 %not.src1 = xor i16 %src1, -1373 %or = or i16 %not.src1, %src0374 ret i16 %or375}376 377define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) {378; GCN-LABEL: s_orn2_i16_multi_use:379; GCN: ; %bb.0:380; GCN-NEXT: s_not_b32 s1, s3381; GCN-NEXT: s_orn2_b32 s0, s2, s3382; GCN-NEXT: ; return to shader part epilog383;384; GFX10-LABEL: s_orn2_i16_multi_use:385; GFX10: ; %bb.0:386; GFX10-NEXT: s_orn2_b32 s0, s2, s3387; GFX10-NEXT: s_not_b32 s1, s3388; GFX10-NEXT: ; return to shader part epilog389;390; GFX11-LABEL: s_orn2_i16_multi_use:391; GFX11: ; %bb.0:392; GFX11-NEXT: s_or_not1_b32 s0, s2, s3393; GFX11-NEXT: s_not_b32 s1, s3394; GFX11-NEXT: ; return to shader part epilog395 %not.src1 = xor i16 %src1, -1396 %or = or i16 %src0, %not.src1397 %insert.0 = insertvalue { i16, i16 } poison, i16 %or, 0398 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1399 ret { i16, i16 } %insert.1400}401 402define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i16 inreg %src1, i16 inreg %src2) {403; GCN-LABEL: s_orn2_i16_multi_foldable_use:404; GCN: ; %bb.0:405; GCN-NEXT: s_orn2_b32 s0, s2, s4406; GCN-NEXT: s_orn2_b32 s1, s3, s4407; GCN-NEXT: ; return to shader part epilog408;409; GFX10-LABEL: s_orn2_i16_multi_foldable_use:410; GFX10: ; %bb.0:411; GFX10-NEXT: s_orn2_b32 s0, s2, s4412; GFX10-NEXT: s_orn2_b32 s1, s3, s4413; GFX10-NEXT: ; return to shader part epilog414;415; GFX11-LABEL: s_orn2_i16_multi_foldable_use:416; GFX11: ; %bb.0:417; GFX11-NEXT: s_or_not1_b32 s0, s2, s4418; GFX11-NEXT: s_or_not1_b32 s1, s3, s4419; GFX11-NEXT: ; return to shader part epilog420 %not.src2 = xor i16 %src2, -1421 %or0 = or i16 %src0, %not.src2422 %or1 = or i16 %src1, %not.src2423 %insert.0 = insertvalue { i16, i16 } poison, i16 %or0, 0424 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %or1, 1425 ret { i16, i16 } %insert.1426}427 428define i16 @v_orn2_i16(i16 %src0, i16 %src1) {429; GCN-LABEL: v_orn2_i16:430; GCN: ; %bb.0:431; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GCN-NEXT: v_xor_b32_e32 v1, -1, v1433; GCN-NEXT: v_or_b32_e32 v0, v0, v1434; GCN-NEXT: s_setpc_b64 s[30:31]435;436; GFX10PLUS-LABEL: v_orn2_i16:437; GFX10PLUS: ; %bb.0:438; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)439; GFX10PLUS-NEXT: v_xor_b32_e32 v1, -1, v1440; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v1441; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]442 %not.src1 = xor i16 %src1, -1443 %or = or i16 %src0, %not.src1444 ret i16 %or445}446 447define amdgpu_ps float @v_orn2_i16_sv(i16 inreg %src0, i16 %src1) {448; GCN-LABEL: v_orn2_i16_sv:449; GCN: ; %bb.0:450; GCN-NEXT: v_xor_b32_e32 v0, -1, v0451; GCN-NEXT: v_or_b32_e32 v0, s2, v0452; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0453; GCN-NEXT: ; return to shader part epilog454;455; GFX10PLUS-LABEL: v_orn2_i16_sv:456; GFX10PLUS: ; %bb.0:457; GFX10PLUS-NEXT: v_xor_b32_e32 v0, -1, v0458; GFX10PLUS-NEXT: v_or_b32_e32 v0, s2, v0459; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0460; GFX10PLUS-NEXT: ; return to shader part epilog461 %not.src1 = xor i16 %src1, -1462 %or = or i16 %src0, %not.src1463 %zext = zext i16 %or to i32464 %cast.zext = bitcast i32 %zext to float465 ret float %cast.zext466}467 468define amdgpu_ps float @v_orn2_i16_vs(i16 %src0, i16 inreg %src1) {469; GCN-LABEL: v_orn2_i16_vs:470; GCN: ; %bb.0:471; GCN-NEXT: s_not_b32 s0, s2472; GCN-NEXT: v_or_b32_e32 v0, s0, v0473; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0474; GCN-NEXT: ; return to shader part epilog475;476; GFX10PLUS-LABEL: v_orn2_i16_vs:477; GFX10PLUS: ; %bb.0:478; GFX10PLUS-NEXT: s_not_b32 s0, s2479; GFX10PLUS-NEXT: v_or_b32_e32 v0, s0, v0480; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0481; GFX10PLUS-NEXT: ; return to shader part epilog482 %not.src1 = xor i16 %src1, -1483 %or = or i16 %src0, %not.src1484 %zext = zext i16 %or to i32485 %cast.zext = bitcast i32 %zext to float486 ret float %cast.zext487}488 489define amdgpu_ps i32 @s_orn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {490; GFX6-LABEL: s_orn2_v2i16:491; GFX6: ; %bb.0:492; GFX6-NEXT: s_lshl_b32 s0, s3, 16493; GFX6-NEXT: s_and_b32 s1, s2, 0xffff494; GFX6-NEXT: s_or_b32 s0, s0, s1495; GFX6-NEXT: s_lshl_b32 s1, s5, 16496; GFX6-NEXT: s_and_b32 s2, s4, 0xffff497; GFX6-NEXT: s_or_b32 s1, s1, s2498; GFX6-NEXT: s_xor_b32 s1, s1, -1499; GFX6-NEXT: s_or_b32 s0, s0, s1500; GFX6-NEXT: ; return to shader part epilog501;502; GFX9-LABEL: s_orn2_v2i16:503; GFX9: ; %bb.0:504; GFX9-NEXT: s_orn2_b32 s0, s2, s3505; GFX9-NEXT: ; return to shader part epilog506;507; GFX10-LABEL: s_orn2_v2i16:508; GFX10: ; %bb.0:509; GFX10-NEXT: s_orn2_b32 s0, s2, s3510; GFX10-NEXT: ; return to shader part epilog511;512; GFX11-LABEL: s_orn2_v2i16:513; GFX11: ; %bb.0:514; GFX11-NEXT: s_or_not1_b32 s0, s2, s3515; GFX11-NEXT: ; return to shader part epilog516 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>517 %or = or <2 x i16> %src0, %not.src1518 %cast = bitcast <2 x i16> %or to i32519 ret i32 %cast520}521 522define amdgpu_ps i32 @s_orn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {523; GFX6-LABEL: s_orn2_v2i16_commute:524; GFX6: ; %bb.0:525; GFX6-NEXT: s_lshl_b32 s0, s3, 16526; GFX6-NEXT: s_and_b32 s1, s2, 0xffff527; GFX6-NEXT: s_or_b32 s0, s0, s1528; GFX6-NEXT: s_lshl_b32 s1, s5, 16529; GFX6-NEXT: s_and_b32 s2, s4, 0xffff530; GFX6-NEXT: s_or_b32 s1, s1, s2531; GFX6-NEXT: s_xor_b32 s1, s1, -1532; GFX6-NEXT: s_or_b32 s0, s1, s0533; GFX6-NEXT: ; return to shader part epilog534;535; GFX9-LABEL: s_orn2_v2i16_commute:536; GFX9: ; %bb.0:537; GFX9-NEXT: s_orn2_b32 s0, s2, s3538; GFX9-NEXT: ; return to shader part epilog539;540; GFX10-LABEL: s_orn2_v2i16_commute:541; GFX10: ; %bb.0:542; GFX10-NEXT: s_orn2_b32 s0, s2, s3543; GFX10-NEXT: ; return to shader part epilog544;545; GFX11-LABEL: s_orn2_v2i16_commute:546; GFX11: ; %bb.0:547; GFX11-NEXT: s_or_not1_b32 s0, s2, s3548; GFX11-NEXT: ; return to shader part epilog549 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>550 %or = or <2 x i16> %not.src1, %src0551 %cast = bitcast <2 x i16> %or to i32552 ret i32 %cast553}554 555define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {556; GFX6-LABEL: s_orn2_v2i16_multi_use:557; GFX6: ; %bb.0:558; GFX6-NEXT: s_lshl_b32 s0, s3, 16559; GFX6-NEXT: s_and_b32 s1, s2, 0xffff560; GFX6-NEXT: s_or_b32 s0, s0, s1561; GFX6-NEXT: s_lshl_b32 s1, s5, 16562; GFX6-NEXT: s_and_b32 s2, s4, 0xffff563; GFX6-NEXT: s_or_b32 s1, s1, s2564; GFX6-NEXT: s_xor_b32 s1, s1, -1565; GFX6-NEXT: s_or_b32 s0, s0, s1566; GFX6-NEXT: ; return to shader part epilog567;568; GFX9-LABEL: s_orn2_v2i16_multi_use:569; GFX9: ; %bb.0:570; GFX9-NEXT: s_xor_b32 s1, s3, -1571; GFX9-NEXT: s_orn2_b32 s0, s2, s3572; GFX9-NEXT: ; return to shader part epilog573;574; GFX10-LABEL: s_orn2_v2i16_multi_use:575; GFX10: ; %bb.0:576; GFX10-NEXT: s_orn2_b32 s0, s2, s3577; GFX10-NEXT: s_xor_b32 s1, s3, -1578; GFX10-NEXT: ; return to shader part epilog579;580; GFX11-LABEL: s_orn2_v2i16_multi_use:581; GFX11: ; %bb.0:582; GFX11-NEXT: s_or_not1_b32 s0, s2, s3583; GFX11-NEXT: s_xor_b32 s1, s3, -1584; GFX11-NEXT: ; return to shader part epilog585 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>586 %or = or <2 x i16> %src0, %not.src1587 588 %cast.0 = bitcast <2 x i16> %or to i32589 %cast.1 = bitcast <2 x i16> %not.src1 to i32590 %insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0591 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1592 ret { i32, i32 } %insert.1593}594 595define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_foldable_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1, <2 x i16> inreg %src2) {596; GFX6-LABEL: s_orn2_v2i16_multi_foldable_use:597; GFX6: ; %bb.0:598; GFX6-NEXT: s_lshl_b32 s0, s3, 16599; GFX6-NEXT: s_and_b32 s1, s2, 0xffff600; GFX6-NEXT: s_or_b32 s0, s0, s1601; GFX6-NEXT: s_lshl_b32 s1, s5, 16602; GFX6-NEXT: s_and_b32 s2, s4, 0xffff603; GFX6-NEXT: s_or_b32 s1, s1, s2604; GFX6-NEXT: s_lshl_b32 s2, s7, 16605; GFX6-NEXT: s_and_b32 s3, s6, 0xffff606; GFX6-NEXT: s_or_b32 s2, s2, s3607; GFX6-NEXT: s_xor_b32 s2, s2, -1608; GFX6-NEXT: s_or_b32 s0, s0, s2609; GFX6-NEXT: s_or_b32 s1, s1, s2610; GFX6-NEXT: ; return to shader part epilog611;612; GFX9-LABEL: s_orn2_v2i16_multi_foldable_use:613; GFX9: ; %bb.0:614; GFX9-NEXT: s_orn2_b32 s0, s2, s4615; GFX9-NEXT: s_orn2_b32 s1, s3, s4616; GFX9-NEXT: ; return to shader part epilog617;618; GFX10-LABEL: s_orn2_v2i16_multi_foldable_use:619; GFX10: ; %bb.0:620; GFX10-NEXT: s_orn2_b32 s0, s2, s4621; GFX10-NEXT: s_orn2_b32 s1, s3, s4622; GFX10-NEXT: ; return to shader part epilog623;624; GFX11-LABEL: s_orn2_v2i16_multi_foldable_use:625; GFX11: ; %bb.0:626; GFX11-NEXT: s_or_not1_b32 s0, s2, s4627; GFX11-NEXT: s_or_not1_b32 s1, s3, s4628; GFX11-NEXT: ; return to shader part epilog629 %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>630 %or0 = or <2 x i16> %src0, %not.src2631 %or1 = or <2 x i16> %src1, %not.src2632 633 %cast.0 = bitcast <2 x i16> %or0 to i32634 %cast.1 = bitcast <2 x i16> %or1 to i32635 %insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0636 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1637 ret { i32, i32 } %insert.1638}639 640define <2 x i16> @v_orn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {641; GFX6-LABEL: v_orn2_v2i16:642; GFX6: ; %bb.0:643; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)644; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1645; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0646; GFX6-NEXT: v_or_b32_e32 v0, v1, v0647; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3648; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2649; GFX6-NEXT: v_or_b32_e32 v1, v1, v2650; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1651; GFX6-NEXT: v_or_b32_e32 v0, v0, v1652; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0653; GFX6-NEXT: s_setpc_b64 s[30:31]654;655; GFX9-LABEL: v_orn2_v2i16:656; GFX9: ; %bb.0:657; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)658; GFX9-NEXT: v_xor_b32_e32 v1, -1, v1659; GFX9-NEXT: v_or_b32_e32 v0, v0, v1660; GFX9-NEXT: s_setpc_b64 s[30:31]661;662; GFX10PLUS-LABEL: v_orn2_v2i16:663; GFX10PLUS: ; %bb.0:664; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)665; GFX10PLUS-NEXT: v_xor_b32_e32 v1, -1, v1666; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v1667; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]668 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>669 %or = or <2 x i16> %src0, %not.src1670 ret <2 x i16> %or671}672 673define amdgpu_ps i48 @s_orn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {674; GFX6-LABEL: s_orn2_v3i16:675; GFX6: ; %bb.0:676; GFX6-NEXT: s_and_b32 s6, s6, 0xffff677; GFX6-NEXT: s_mov_b32 s0, -1678; GFX6-NEXT: s_and_b32 s5, s5, 0xffff679; GFX6-NEXT: s_lshl_b32 s6, s6, 16680; GFX6-NEXT: s_and_b32 s3, s3, 0xffff681; GFX6-NEXT: s_mov_b32 s1, 0xffff682; GFX6-NEXT: s_or_b32 s6, s5, s6683; GFX6-NEXT: s_and_b32 s7, s7, 0xffff684; GFX6-NEXT: s_and_b32 s2, s2, 0xffff685; GFX6-NEXT: s_lshl_b32 s3, s3, 16686; GFX6-NEXT: s_xor_b64 s[0:1], s[6:7], s[0:1]687; GFX6-NEXT: s_or_b32 s2, s2, s3688; GFX6-NEXT: s_and_b32 s3, s4, 0xffff689; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]690; GFX6-NEXT: s_lshr_b32 s2, s0, 16691; GFX6-NEXT: s_and_b32 s0, s0, 0xffff692; GFX6-NEXT: s_lshl_b32 s2, s2, 16693; GFX6-NEXT: s_or_b32 s0, s0, s2694; GFX6-NEXT: s_and_b32 s1, s1, 0xffff695; GFX6-NEXT: ; return to shader part epilog696;697; GFX9-LABEL: s_orn2_v3i16:698; GFX9: ; %bb.0:699; GFX9-NEXT: s_mov_b64 s[0:1], -1700; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]701; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]702; GFX9-NEXT: s_lshr_b32 s2, s0, 16703; GFX9-NEXT: s_and_b32 s0, s0, 0xffff704; GFX9-NEXT: s_lshl_b32 s2, s2, 16705; GFX9-NEXT: s_or_b32 s0, s0, s2706; GFX9-NEXT: s_and_b32 s1, s1, 0xffff707; GFX9-NEXT: ; return to shader part epilog708;709; GFX10PLUS-LABEL: s_orn2_v3i16:710; GFX10PLUS: ; %bb.0:711; GFX10PLUS-NEXT: s_mov_b64 s[0:1], -1712; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]713; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]714; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16715; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff716; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 16717; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff718; GFX10PLUS-NEXT: s_or_b32 s0, s0, s2719; GFX10PLUS-NEXT: ; return to shader part epilog720 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>721 %or = or <3 x i16> %src0, %not.src1722 %cast = bitcast <3 x i16> %or to i48723 ret i48 %cast724}725 726define amdgpu_ps i48 @s_orn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {727; GFX6-LABEL: s_orn2_v3i16_commute:728; GFX6: ; %bb.0:729; GFX6-NEXT: s_and_b32 s6, s6, 0xffff730; GFX6-NEXT: s_mov_b32 s0, -1731; GFX6-NEXT: s_and_b32 s5, s5, 0xffff732; GFX6-NEXT: s_lshl_b32 s6, s6, 16733; GFX6-NEXT: s_and_b32 s3, s3, 0xffff734; GFX6-NEXT: s_mov_b32 s1, 0xffff735; GFX6-NEXT: s_or_b32 s6, s5, s6736; GFX6-NEXT: s_and_b32 s7, s7, 0xffff737; GFX6-NEXT: s_and_b32 s2, s2, 0xffff738; GFX6-NEXT: s_lshl_b32 s3, s3, 16739; GFX6-NEXT: s_xor_b64 s[0:1], s[6:7], s[0:1]740; GFX6-NEXT: s_or_b32 s2, s2, s3741; GFX6-NEXT: s_and_b32 s3, s4, 0xffff742; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]743; GFX6-NEXT: s_lshr_b32 s2, s0, 16744; GFX6-NEXT: s_and_b32 s0, s0, 0xffff745; GFX6-NEXT: s_lshl_b32 s2, s2, 16746; GFX6-NEXT: s_or_b32 s0, s0, s2747; GFX6-NEXT: s_and_b32 s1, s1, 0xffff748; GFX6-NEXT: ; return to shader part epilog749;750; GFX9-LABEL: s_orn2_v3i16_commute:751; GFX9: ; %bb.0:752; GFX9-NEXT: s_mov_b64 s[0:1], -1753; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]754; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]755; GFX9-NEXT: s_lshr_b32 s2, s0, 16756; GFX9-NEXT: s_and_b32 s0, s0, 0xffff757; GFX9-NEXT: s_lshl_b32 s2, s2, 16758; GFX9-NEXT: s_or_b32 s0, s0, s2759; GFX9-NEXT: s_and_b32 s1, s1, 0xffff760; GFX9-NEXT: ; return to shader part epilog761;762; GFX10PLUS-LABEL: s_orn2_v3i16_commute:763; GFX10PLUS: ; %bb.0:764; GFX10PLUS-NEXT: s_mov_b64 s[0:1], -1765; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]766; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]767; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16768; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff769; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 16770; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff771; GFX10PLUS-NEXT: s_or_b32 s0, s0, s2772; GFX10PLUS-NEXT: ; return to shader part epilog773 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>774 %or = or <3 x i16> %not.src1, %src0775 %cast = bitcast <3 x i16> %or to i48776 ret i48 %cast777}778 779define amdgpu_ps { i48, i48 } @s_orn2_v3i16_multi_use(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {780; GFX6-LABEL: s_orn2_v3i16_multi_use:781; GFX6: ; %bb.0:782; GFX6-NEXT: s_and_b32 s6, s6, 0xffff783; GFX6-NEXT: s_mov_b32 s0, -1784; GFX6-NEXT: s_and_b32 s5, s5, 0xffff785; GFX6-NEXT: s_lshl_b32 s6, s6, 16786; GFX6-NEXT: s_mov_b32 s1, 0xffff787; GFX6-NEXT: s_or_b32 s6, s5, s6788; GFX6-NEXT: s_and_b32 s7, s7, 0xffff789; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]790; GFX6-NEXT: s_and_b32 s1, s3, 0xffff791; GFX6-NEXT: s_and_b32 s0, s2, 0xffff792; GFX6-NEXT: s_lshl_b32 s1, s1, 16793; GFX6-NEXT: s_or_b32 s0, s0, s1794; GFX6-NEXT: s_and_b32 s1, s4, 0xffff795; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]796; GFX6-NEXT: s_lshr_b32 s2, s0, 16797; GFX6-NEXT: s_lshr_b32 s5, s6, 16798; GFX6-NEXT: s_and_b32 s0, s0, 0xffff799; GFX6-NEXT: s_lshl_b32 s2, s2, 16800; GFX6-NEXT: s_or_b32 s0, s0, s2801; GFX6-NEXT: s_and_b32 s2, s6, 0xffff802; GFX6-NEXT: s_lshl_b32 s3, s5, 16803; GFX6-NEXT: s_and_b32 s1, s1, 0xffff804; GFX6-NEXT: s_or_b32 s2, s2, s3805; GFX6-NEXT: s_and_b32 s3, s7, 0xffff806; GFX6-NEXT: ; return to shader part epilog807;808; GFX9-LABEL: s_orn2_v3i16_multi_use:809; GFX9: ; %bb.0:810; GFX9-NEXT: s_mov_b64 s[0:1], -1811; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]812; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]813; GFX9-NEXT: s_lshr_b32 s2, s0, 16814; GFX9-NEXT: s_lshr_b32 s6, s4, 16815; GFX9-NEXT: s_and_b32 s0, s0, 0xffff816; GFX9-NEXT: s_lshl_b32 s2, s2, 16817; GFX9-NEXT: s_or_b32 s0, s0, s2818; GFX9-NEXT: s_and_b32 s2, s4, 0xffff819; GFX9-NEXT: s_lshl_b32 s3, s6, 16820; GFX9-NEXT: s_and_b32 s1, s1, 0xffff821; GFX9-NEXT: s_or_b32 s2, s2, s3822; GFX9-NEXT: s_and_b32 s3, s5, 0xffff823; GFX9-NEXT: ; return to shader part epilog824;825; GFX10PLUS-LABEL: s_orn2_v3i16_multi_use:826; GFX10PLUS: ; %bb.0:827; GFX10PLUS-NEXT: s_mov_b64 s[0:1], -1828; GFX10PLUS-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]829; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]830; GFX10PLUS-NEXT: s_lshr_b32 s3, s4, 16831; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16832; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff833; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 16834; GFX10PLUS-NEXT: s_lshl_b32 s3, s3, 16835; GFX10PLUS-NEXT: s_or_b32 s0, s0, s2836; GFX10PLUS-NEXT: s_and_b32 s2, s4, 0xffff837; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff838; GFX10PLUS-NEXT: s_or_b32 s2, s2, s3839; GFX10PLUS-NEXT: s_and_b32 s3, s5, 0xffff840; GFX10PLUS-NEXT: ; return to shader part epilog841 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>842 %or = or <3 x i16> %src0, %not.src1843 %cast.0 = bitcast <3 x i16> %or to i48844 %cast.1 = bitcast <3 x i16> %not.src1 to i48845 %insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0846 %insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1847 ret { i48, i48 } %insert.1848}849 850define <3 x i16> @v_orn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {851; GFX6-LABEL: v_orn2_v3i16:852; GFX6: ; %bb.0:853; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)854; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4855; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3856; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4857; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1858; GFX6-NEXT: v_or_b32_e32 v3, v3, v4859; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0860; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1861; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5862; GFX6-NEXT: v_xor_b32_e32 v3, -1, v3863; GFX6-NEXT: v_or_b32_e32 v0, v0, v1864; GFX6-NEXT: v_xor_b32_e32 v4, 0xfff5, v4865; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2866; GFX6-NEXT: v_or_b32_e32 v0, v0, v3867; GFX6-NEXT: v_or_b32_e32 v2, v1, v4868; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0869; GFX6-NEXT: s_setpc_b64 s[30:31]870;871; GFX9-LABEL: v_orn2_v3i16:872; GFX9: ; %bb.0:873; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)874; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2875; GFX9-NEXT: v_xor_b32_e32 v3, -11, v3876; GFX9-NEXT: v_or_b32_e32 v0, v0, v2877; GFX9-NEXT: v_or_b32_e32 v1, v1, v3878; GFX9-NEXT: s_setpc_b64 s[30:31]879;880; GFX10PLUS-LABEL: v_orn2_v3i16:881; GFX10PLUS: ; %bb.0:882; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)883; GFX10PLUS-NEXT: v_xor_b32_e32 v2, -1, v2884; GFX10PLUS-NEXT: v_xor_b32_e32 v3, -11, v3885; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v2886; GFX10PLUS-NEXT: v_or_b32_e32 v1, v1, v3887; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]888 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -11>889 %or = or <3 x i16> %src0, %not.src1890 ret <3 x i16> %or891}892 893define amdgpu_ps i64 @s_orn2_v4i16(<4 x i16> inreg %src0, <4 x i16> inreg %src1) {894; GFX6-LABEL: s_orn2_v4i16:895; GFX6: ; %bb.0:896; GFX6-NEXT: s_lshl_b32 s0, s3, 16897; GFX6-NEXT: s_and_b32 s1, s2, 0xffff898; GFX6-NEXT: s_or_b32 s0, s0, s1899; GFX6-NEXT: s_lshl_b32 s1, s5, 16900; GFX6-NEXT: s_and_b32 s2, s4, 0xffff901; GFX6-NEXT: s_or_b32 s1, s1, s2902; GFX6-NEXT: s_lshl_b32 s2, s7, 16903; GFX6-NEXT: s_and_b32 s3, s6, 0xffff904; GFX6-NEXT: s_or_b32 s2, s2, s3905; GFX6-NEXT: s_lshl_b32 s3, s9, 16906; GFX6-NEXT: s_and_b32 s4, s8, 0xffff907; GFX6-NEXT: s_or_b32 s3, s3, s4908; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], -1909; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]910; GFX6-NEXT: ; return to shader part epilog911;912; GFX9-LABEL: s_orn2_v4i16:913; GFX9: ; %bb.0:914; GFX9-NEXT: s_mov_b32 s0, -1915; GFX9-NEXT: s_mov_b32 s1, s0916; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]917; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]918; GFX9-NEXT: ; return to shader part epilog919;920; GFX10PLUS-LABEL: s_orn2_v4i16:921; GFX10PLUS: ; %bb.0:922; GFX10PLUS-NEXT: s_mov_b32 s0, -1923; GFX10PLUS-NEXT: s_mov_b32 s1, s0924; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]925; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]926; GFX10PLUS-NEXT: ; return to shader part epilog927 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>928 %or = or <4 x i16> %src0, %not.src1929 %cast = bitcast <4 x i16> %or to i64930 ret i64 %cast931}932 933define amdgpu_ps i64 @s_orn2_v4i16_commute(<4 x i16> inreg %src0, <4 x i16> inreg %src1) {934; GFX6-LABEL: s_orn2_v4i16_commute:935; GFX6: ; %bb.0:936; GFX6-NEXT: s_lshl_b32 s0, s3, 16937; GFX6-NEXT: s_and_b32 s1, s2, 0xffff938; GFX6-NEXT: s_or_b32 s0, s0, s1939; GFX6-NEXT: s_lshl_b32 s1, s5, 16940; GFX6-NEXT: s_and_b32 s2, s4, 0xffff941; GFX6-NEXT: s_or_b32 s1, s1, s2942; GFX6-NEXT: s_lshl_b32 s2, s7, 16943; GFX6-NEXT: s_and_b32 s3, s6, 0xffff944; GFX6-NEXT: s_or_b32 s2, s2, s3945; GFX6-NEXT: s_lshl_b32 s3, s9, 16946; GFX6-NEXT: s_and_b32 s4, s8, 0xffff947; GFX6-NEXT: s_or_b32 s3, s3, s4948; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], -1949; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]950; GFX6-NEXT: ; return to shader part epilog951;952; GFX9-LABEL: s_orn2_v4i16_commute:953; GFX9: ; %bb.0:954; GFX9-NEXT: s_mov_b32 s0, -1955; GFX9-NEXT: s_mov_b32 s1, s0956; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]957; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]958; GFX9-NEXT: ; return to shader part epilog959;960; GFX10PLUS-LABEL: s_orn2_v4i16_commute:961; GFX10PLUS: ; %bb.0:962; GFX10PLUS-NEXT: s_mov_b32 s0, -1963; GFX10PLUS-NEXT: s_mov_b32 s1, s0964; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]965; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]966; GFX10PLUS-NEXT: ; return to shader part epilog967 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>968 %or = or <4 x i16> %not.src1, %src0969 %cast = bitcast <4 x i16> %or to i64970 ret i64 %cast971}972 973define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_use(<4 x i16> inreg %src0, <4 x i16> inreg %src1) {974; GFX6-LABEL: s_orn2_v4i16_multi_use:975; GFX6: ; %bb.0:976; GFX6-NEXT: s_lshl_b32 s0, s3, 16977; GFX6-NEXT: s_and_b32 s1, s2, 0xffff978; GFX6-NEXT: s_or_b32 s0, s0, s1979; GFX6-NEXT: s_lshl_b32 s1, s5, 16980; GFX6-NEXT: s_and_b32 s2, s4, 0xffff981; GFX6-NEXT: s_or_b32 s1, s1, s2982; GFX6-NEXT: s_lshl_b32 s2, s7, 16983; GFX6-NEXT: s_and_b32 s3, s6, 0xffff984; GFX6-NEXT: s_or_b32 s2, s2, s3985; GFX6-NEXT: s_lshl_b32 s3, s9, 16986; GFX6-NEXT: s_and_b32 s4, s8, 0xffff987; GFX6-NEXT: s_or_b32 s3, s3, s4988; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], -1989; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]990; GFX6-NEXT: ; return to shader part epilog991;992; GFX9-LABEL: s_orn2_v4i16_multi_use:993; GFX9: ; %bb.0:994; GFX9-NEXT: s_mov_b32 s0, -1995; GFX9-NEXT: s_mov_b32 s1, s0996; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]997; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]998; GFX9-NEXT: s_mov_b32 s2, s4999; GFX9-NEXT: s_mov_b32 s3, s51000; GFX9-NEXT: ; return to shader part epilog1001;1002; GFX10PLUS-LABEL: s_orn2_v4i16_multi_use:1003; GFX10PLUS: ; %bb.0:1004; GFX10PLUS-NEXT: s_mov_b32 s0, -11005; GFX10PLUS-NEXT: s_mov_b32 s1, s01006; GFX10PLUS-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]1007; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]1008; GFX10PLUS-NEXT: s_mov_b32 s2, s41009; GFX10PLUS-NEXT: s_mov_b32 s3, s51010; GFX10PLUS-NEXT: ; return to shader part epilog1011 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>1012 %or = or <4 x i16> %src0, %not.src11013 1014 %cast.0 = bitcast <4 x i16> %or to i641015 %cast.1 = bitcast <4 x i16> %not.src1 to i641016 %insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 01017 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 11018 ret { i64, i64 } %insert.11019}1020 1021define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_foldable_use(<4 x i16> inreg %src0, <4 x i16> inreg %src1, <4 x i16> inreg %src2) {1022; GFX6-LABEL: s_orn2_v4i16_multi_foldable_use:1023; GFX6: ; %bb.0:1024; GFX6-NEXT: s_lshl_b32 s0, s3, 161025; GFX6-NEXT: s_and_b32 s1, s2, 0xffff1026; GFX6-NEXT: s_or_b32 s0, s0, s11027; GFX6-NEXT: s_lshl_b32 s1, s5, 161028; GFX6-NEXT: s_and_b32 s2, s4, 0xffff1029; GFX6-NEXT: s_or_b32 s1, s1, s21030; GFX6-NEXT: s_lshl_b32 s2, s7, 161031; GFX6-NEXT: s_and_b32 s3, s6, 0xffff1032; GFX6-NEXT: s_or_b32 s2, s2, s31033; GFX6-NEXT: s_lshl_b32 s3, s9, 161034; GFX6-NEXT: s_and_b32 s4, s8, 0xffff1035; GFX6-NEXT: s_or_b32 s3, s3, s41036; GFX6-NEXT: s_lshl_b32 s4, s11, 161037; GFX6-NEXT: s_and_b32 s5, s10, 0xffff1038; GFX6-NEXT: s_or_b32 s4, s4, s51039; GFX6-NEXT: s_lshl_b32 s5, s13, 161040; GFX6-NEXT: s_and_b32 s6, s12, 0xffff1041; GFX6-NEXT: s_or_b32 s5, s5, s61042; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], -11043; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]1044; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]1045; GFX6-NEXT: ; return to shader part epilog1046;1047; GFX9-LABEL: s_orn2_v4i16_multi_foldable_use:1048; GFX9: ; %bb.0:1049; GFX9-NEXT: s_mov_b32 s0, -11050; GFX9-NEXT: s_mov_b32 s1, s01051; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]1052; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7]1053; GFX9-NEXT: s_or_b64 s[2:3], s[4:5], s[6:7]1054; GFX9-NEXT: ; return to shader part epilog1055;1056; GFX10PLUS-LABEL: s_orn2_v4i16_multi_foldable_use:1057; GFX10PLUS: ; %bb.0:1058; GFX10PLUS-NEXT: s_mov_b32 s0, -11059; GFX10PLUS-NEXT: s_mov_b32 s1, s01060; GFX10PLUS-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]1061; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7]1062; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[4:5], s[6:7]1063; GFX10PLUS-NEXT: ; return to shader part epilog1064 %not.src2 = xor <4 x i16> %src2, <i16 -1, i16 -1, i16 -1, i16 -1>1065 %or0 = or <4 x i16> %src0, %not.src21066 %or1 = or <4 x i16> %src1, %not.src21067 1068 %cast.0 = bitcast <4 x i16> %or0 to i641069 %cast.1 = bitcast <4 x i16> %or1 to i641070 %insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 01071 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 11072 ret { i64, i64 } %insert.11073}1074 1075define <4 x i16> @v_orn2_v4i16(<4 x i16> %src0, <4 x i16> %src1) {1076; GFX6-LABEL: v_orn2_v4i16:1077; GFX6: ; %bb.0:1078; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1079; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v11080; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v01081; GFX6-NEXT: v_or_b32_e32 v0, v1, v01082; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v31083; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v21084; GFX6-NEXT: v_or_b32_e32 v1, v1, v21085; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v51086; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v41087; GFX6-NEXT: v_or_b32_e32 v2, v2, v31088; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v71089; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v61090; GFX6-NEXT: v_or_b32_e32 v3, v3, v41091; GFX6-NEXT: v_xor_b32_e32 v2, -1, v21092; GFX6-NEXT: v_xor_b32_e32 v3, -1, v31093; GFX6-NEXT: v_or_b32_e32 v0, v0, v21094; GFX6-NEXT: v_or_b32_e32 v2, v1, v31095; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v01096; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v21097; GFX6-NEXT: s_setpc_b64 s[30:31]1098;1099; GFX9-LABEL: v_orn2_v4i16:1100; GFX9: ; %bb.0:1101; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1102; GFX9-NEXT: v_xor_b32_e32 v2, -1, v21103; GFX9-NEXT: v_xor_b32_e32 v3, -1, v31104; GFX9-NEXT: v_or_b32_e32 v0, v0, v21105; GFX9-NEXT: v_or_b32_e32 v1, v1, v31106; GFX9-NEXT: s_setpc_b64 s[30:31]1107;1108; GFX10PLUS-LABEL: v_orn2_v4i16:1109; GFX10PLUS: ; %bb.0:1110; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1111; GFX10PLUS-NEXT: v_xor_b32_e32 v2, -1, v21112; GFX10PLUS-NEXT: v_xor_b32_e32 v3, -1, v31113; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v21114; GFX10PLUS-NEXT: v_or_b32_e32 v1, v1, v31115; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1116 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>1117 %or = or <4 x i16> %src0, %not.src11118 ret <4 x i16> %or1119}1120