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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s3 4---5name: test_reassoc_infinite_loop6legalized: true7tracksRegLiveness: true8body: |9 bb.1:10 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr411 12 ; CHECK-LABEL: name: test_reassoc_infinite_loop13 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr414 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr016 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 217 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]18 ; CHECK-NEXT: $vgpr0 = COPY [[ADD]](s32)19 ; CHECK-NEXT: SI_RETURN implicit $vgpr020 %0:_(s32) = COPY $vgpr021 %1:_(s32) = G_CONSTANT i32 022 %2:_(s32) = G_CONSTANT i32 123 %3:_(s1) = G_ICMP intpred(eq), %1(s32), %124 %4:_(s32) = G_SELECT %3(s1), %2, %125 %5:_(s32) = COPY %4(s32)26 %6:_(s32) = G_ADD %0, %527 %7:_(s32) = G_ADD %6, %228 $vgpr0 = COPY %7(s32)29 SI_RETURN implicit $vgpr030...31