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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s3 4# Post-legalizer should not generate illegal extending loads5---6name: zextload_from_inreg7tracksRegLiveness: true8legalized: true9body: |10 bb.0:11 liveins: $vgpr0_vgpr112 ; CHECK-LABEL: name: zextload_from_inreg13 ; CHECK: liveins: $vgpr0_vgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr116 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)17 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LOAD]](s64)18 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s32)19 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)20 %0:_(p1) = COPY $vgpr0_vgpr121 %1:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)22 %k:_(s64) = G_CONSTANT i64 429496729523 %2:_(s64) = G_AND %1, %k24 $vgpr0_vgpr1 = COPY %225...26 27# Legal to fold into zextload28---29name: zext_inreg_8_zextload_s3230tracksRegLiveness: true31legalized: true32body: |33 bb.0:34 liveins: $vgpr0_vgpr135 ; CHECK-LABEL: name: zext_inreg_8_zextload_s3236 ; CHECK: liveins: $vgpr0_vgpr137 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr139 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)40 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)41 %0:_(p1) = COPY $vgpr0_vgpr142 %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)43 %k:_(s32) = G_CONSTANT i32 25544 %2:_(s32) = G_AND %1, %k45 $vgpr0 = COPY %246...47 48---49name: zext_inreg_7_zextload_s3250tracksRegLiveness: true51legalized: true52body: |53 bb.0:54 liveins: $vgpr0_vgpr155 ; CHECK-LABEL: name: zext_inreg_7_zextload_s3256 ; CHECK: liveins: $vgpr0_vgpr157 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr159 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)60 ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 12761 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k62 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)63 %0:_(p1) = COPY $vgpr0_vgpr164 %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)65 %k:_(s32) = G_CONSTANT i32 12766 %2:_(s32) = G_AND %1, %k67 $vgpr0 = COPY %268...69 70---71name: zext_inreg_9_zextload_s3272tracksRegLiveness: true73legalized: true74body: |75 bb.0:76 liveins: $vgpr0_vgpr177 ; CHECK-LABEL: name: zext_inreg_9_zextload_s3278 ; CHECK: liveins: $vgpr0_vgpr179 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr181 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)82 ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 51183 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k84 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)85 %0:_(p1) = COPY $vgpr0_vgpr186 %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)87 %k:_(s32) = G_CONSTANT i32 51188 %2:_(s32) = G_AND %1, %k89 $vgpr0 = COPY %290...91 92# Legal to fold into zextload93---94name: zext_inreg_16_zextload_s3295tracksRegLiveness: true96legalized: true97body: |98 bb.0:99 liveins: $vgpr0_vgpr1100 ; CHECK-LABEL: name: zext_inreg_16_zextload_s32101 ; CHECK: liveins: $vgpr0_vgpr1102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1104 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)105 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)106 %0:_(p1) = COPY $vgpr0_vgpr1107 %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)108 %k:_(s32) = G_CONSTANT i32 65535109 %2:_(s32) = G_AND %1, %k110 $vgpr0 = COPY %2111...112 113---114name: zext_inreg_8_zextload_s8115tracksRegLiveness: true116legalized: true117body: |118 bb.0:119 liveins: $vgpr0_vgpr1120 ; CHECK-LABEL: name: zext_inreg_8_zextload_s8121 ; CHECK: liveins: $vgpr0_vgpr1122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1124 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)125 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)126 %0:_(p1) = COPY $vgpr0_vgpr1127 %1:_(s32) = G_LOAD %0 :: (load (s8), align 1, addrspace 1)128 %k:_(s32) = G_CONSTANT i32 255129 %2:_(s32) = G_AND %1, %k130 $vgpr0 = COPY %2131...132 133---134name: zext_inreg_8_zextload_s8_volatile135tracksRegLiveness: true136legalized: true137body: |138 bb.0:139 liveins: $vgpr0_vgpr1140 ; CHECK-LABEL: name: zext_inreg_8_zextload_s8_volatile141 ; CHECK: liveins: $vgpr0_vgpr1142 ; CHECK-NEXT: {{ $}}143 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1144 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s8), addrspace 1)145 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)146 %0:_(p1) = COPY $vgpr0_vgpr1147 %1:_(s32) = G_LOAD %0 :: (volatile load (s8), align 1, addrspace 1)148 %k:_(s32) = G_CONSTANT i32 255149 %2:_(s32) = G_AND %1, %k150 $vgpr0 = COPY %2151...152 153---154name: zext_inreg_16_zextload_s16155tracksRegLiveness: true156legalized: true157body: |158 bb.0:159 liveins: $vgpr0_vgpr1160 ; CHECK-LABEL: name: zext_inreg_16_zextload_s16161 ; CHECK: liveins: $vgpr0_vgpr1162 ; CHECK-NEXT: {{ $}}163 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1164 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)165 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)166 %0:_(p1) = COPY $vgpr0_vgpr1167 %1:_(s32) = G_LOAD %0 :: (load (s16), align 2, addrspace 1)168 %k:_(s32) = G_CONSTANT i32 65535169 %2:_(s32) = G_AND %1, %k170 $vgpr0 = COPY %2171...172 173---174name: zext_inreg_16_zextload_s16_volatile175tracksRegLiveness: true176legalized: true177body: |178 bb.0:179 liveins: $vgpr0_vgpr1180 ; CHECK-LABEL: name: zext_inreg_16_zextload_s16_volatile181 ; CHECK: liveins: $vgpr0_vgpr1182 ; CHECK-NEXT: {{ $}}183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1184 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s16), addrspace 1)185 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)186 %0:_(p1) = COPY $vgpr0_vgpr1187 %1:_(s32) = G_LOAD %0 :: (volatile load (s16), align 2, addrspace 1)188 %k:_(s32) = G_CONSTANT i32 65535189 %2:_(s32) = G_AND %1, %k190 $vgpr0 = COPY %2191...192