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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s4 5---6name:  bfe_sext_inreg_ashr_s327legalized:       true8tracksRegLiveness: true9 10body: |11  bb.0.entry:12    liveins: $vgpr013 14    ; GCN-LABEL: name: bfe_sext_inreg_ashr_s3215    ; GCN: liveins: $vgpr016    ; GCN-NEXT: {{  $}}17    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr018    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 419    ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1620    ; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[C]](s32), [[C1]]21    ; GCN-NEXT: $vgpr0 = COPY [[SBFX]](s32)22    %0:_(s32) = COPY $vgpr023    %1:_(s32) = G_CONSTANT i32 424    %2:_(s32) = G_ASHR %0, %1(s32)25    %3:_(s32) = COPY %2(s32)26    %4:_(s32) = G_SEXT_INREG %3, 1627    $vgpr0 = COPY %4(s32)28...29 30---31name:  bfe_sext_inreg_lshr_s3232legalized:       true33tracksRegLiveness: true34 35body: |36  bb.0.entry:37    liveins: $vgpr038 39    ; GCN-LABEL: name: bfe_sext_inreg_lshr_s3240    ; GCN: liveins: $vgpr041    ; GCN-NEXT: {{  $}}42    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr043    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 444    ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1645    ; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[C]](s32), [[C1]]46    ; GCN-NEXT: $vgpr0 = COPY [[SBFX]](s32)47    %0:_(s32) = COPY $vgpr048    %1:_(s32) = G_CONSTANT i32 449    %2:_(s32) = G_LSHR %0, %1(s32)50    %3:_(s32) = COPY %2(s32)51    %4:_(s32) = G_SEXT_INREG %3, 1652    $vgpr0 = COPY %4(s32)53...54 55---56name:  bfe_sext_inreg_ashr_s6457legalized:       true58tracksRegLiveness: true59 60body: |61  bb.0.entry:62    liveins: $vgpr0_vgpr163 64    ; GCN-LABEL: name: bfe_sext_inreg_ashr_s6465    ; GCN: liveins: $vgpr0_vgpr166    ; GCN-NEXT: {{  $}}67    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr168    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 469    ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1670    ; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s64) = G_SBFX [[COPY]], [[C]](s32), [[C1]]71    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SBFX]](s64)72    %0:_(s64) = COPY $vgpr0_vgpr173    %1:_(s32) = G_CONSTANT i32 474    %2:_(s64) = G_ASHR %0, %1(s32)75    %3:_(s64) = COPY %2(s64)76    %4:_(s64) = G_SEXT_INREG %3, 1677    $vgpr0_vgpr1 = COPY %4(s64)78...79 80---81name:  toobig_sext_inreg_ashr_s3282legalized:       true83tracksRegLiveness: true84 85body: |86  bb.0.entry:87    liveins: $vgpr088 89    ; GCN-LABEL: name: toobig_sext_inreg_ashr_s3290    ; GCN: liveins: $vgpr091    ; GCN-NEXT: {{  $}}92    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr093    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1694    ; GCN-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)95    ; GCN-NEXT: $vgpr0 = COPY [[ASHR]](s32)96    %0:_(s32) = COPY $vgpr097    %1:_(s32) = G_CONSTANT i32 1698    %2:_(s32) = G_ASHR %0, %1(s32)99    %3:_(s32) = COPY %2(s32)100    %4:_(s32) = G_SEXT_INREG %3, 20101    $vgpr0 = COPY %4(s32)102...103 104---105name:  toobig_sext_inreg_ashr_s64106legalized:       true107tracksRegLiveness: true108 109body: |110  bb.0.entry:111    liveins: $vgpr0_vgpr1112 113    ; GCN-LABEL: name: toobig_sext_inreg_ashr_s64114    ; GCN: liveins: $vgpr0_vgpr1115    ; GCN-NEXT: {{  $}}116    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1117    ; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)118    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31119    ; GCN-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)120    ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8121    ; GCN-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)122    ; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR]](s32)123    ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV]], 32124    ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)125    %0:_(s64) = COPY $vgpr0_vgpr1126    %1:_(s32) = G_CONSTANT i32 40127    %2:_(s64) = G_ASHR %0, %1(s32)128    %3:_(s64) = COPY %2(s64)129    %4:_(s64) = G_SEXT_INREG %3, 32130    $vgpr0_vgpr1 = COPY %4(s64)131...132 133---134name:  var_sext_inreg_ashr_s32135legalized:       true136tracksRegLiveness: true137 138body: |139  bb.0.entry:140    liveins: $vgpr0, $vgpr1141 142    ; GCN-LABEL: name: var_sext_inreg_ashr_s32143    ; GCN: liveins: $vgpr0, $vgpr1144    ; GCN-NEXT: {{  $}}145    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0146    ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1147    ; GCN-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)148    ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASHR]], 10149    ; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)150    %0:_(s32) = COPY $vgpr0151    %1:_(s32) = COPY $vgpr1152    %2:_(s32) = G_ASHR %0, %1(s32)153    %3:_(s32) = COPY %2(s32)154    %4:_(s32) = G_SEXT_INREG %3, 10155    $vgpr0 = COPY %4(s32)156...157