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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: sext_inreg_i32_8_and_neg2556legalized: true7tracksRegLiveness: true8body: |9 bb.0:10 liveins: $vgpr0_vgpr111 12 ; CHECK-LABEL: name: sext_inreg_i32_8_and_neg25513 ; CHECK: liveins: $vgpr0_vgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr116 ; CHECK-NEXT: %load:_(s32) = G_LOAD %ptr(p1) :: (volatile load (s32), addrspace 1)17 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 118 ; CHECK-NEXT: %inreg:_(s32) = G_AND %load, [[C]]19 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)20 %ptr:_(p1) = COPY $vgpr0_vgpr121 %load:_(s32) = G_LOAD %ptr :: (volatile load (s32), addrspace 1, align 4)22 %mask:_(s32) = G_CONSTANT i32 -25523 %and:_(s32) = G_AND %load, %mask24 %inreg:_(s32) = G_SEXT_INREG %and, 825 $vgpr0 = COPY %inreg26 27...28 29---30name: sext_inreg_i32_8_and_25531legalized: true32tracksRegLiveness: true33body: |34 bb.0:35 liveins: $vgpr0_vgpr136 37 ; CHECK-LABEL: name: sext_inreg_i32_8_and_25538 ; CHECK: liveins: $vgpr0_vgpr139 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr141 ; CHECK-NEXT: %load:_(s32) = G_LOAD %ptr(p1) :: (volatile load (s32), addrspace 1)42 ; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 25543 ; CHECK-NEXT: %and:_(s32) = G_AND %load, %mask44 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %and, 845 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)46 %ptr:_(p1) = COPY $vgpr0_vgpr147 %load:_(s32) = G_LOAD %ptr :: (volatile load (s32), addrspace 1, align 4)48 %mask:_(s32) = G_CONSTANT i32 25549 %and:_(s32) = G_AND %load, %mask50 %inreg:_(s32) = G_SEXT_INREG %and, 851 $vgpr0 = COPY %inreg52 53...54 55---56name: sext_inreg_v2i32_8_and_neg25557legalized: true58tracksRegLiveness: true59body: |60 bb.0:61 liveins: $vgpr0_vgpr162 63 ; CHECK-LABEL: name: sext_inreg_v2i32_8_and_neg25564 ; CHECK: liveins: $vgpr0_vgpr165 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr167 ; CHECK-NEXT: %load:_(<2 x s32>) = G_LOAD %ptr(p1) :: (volatile load (<2 x s32>), addrspace 1)68 ; CHECK-NEXT: %mask_elt:_(s32) = G_CONSTANT i32 -25569 ; CHECK-NEXT: %mask:_(<2 x s32>) = G_BUILD_VECTOR %mask_elt(s32), %mask_elt(s32)70 ; CHECK-NEXT: %and:_(<2 x s32>) = G_AND %load, %mask71 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25572 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)73 ; CHECK-NEXT: %inreg:_(<2 x s32>) = G_AND %and, [[BUILD_VECTOR]]74 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(<2 x s32>)75 %ptr:_(p1) = COPY $vgpr0_vgpr176 %load:_(<2 x s32>) = G_LOAD %ptr :: (volatile load (<2 x s32>), addrspace 1, align 8)77 %mask_elt:_(s32) = G_CONSTANT i32 -25578 %mask:_(<2 x s32>) = G_BUILD_VECTOR %mask_elt, %mask_elt79 %and:_(<2 x s32>) = G_AND %load, %mask80 %inreg:_(<2 x s32>) = G_SEXT_INREG %and, 881 $vgpr0_vgpr1 = COPY %inreg82 83...84 85---86name: sext_inreg_v2i32_8_and_25587legalized: true88tracksRegLiveness: true89body: |90 bb.0:91 liveins: $vgpr0_vgpr192 93 ; CHECK-LABEL: name: sext_inreg_v2i32_8_and_25594 ; CHECK: liveins: $vgpr0_vgpr195 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr197 ; CHECK-NEXT: %load:_(<2 x s32>) = G_LOAD %ptr(p1) :: (volatile load (<2 x s32>), addrspace 1)98 ; CHECK-NEXT: %mask_elt:_(s32) = G_CONSTANT i32 25599 ; CHECK-NEXT: %mask:_(<2 x s32>) = G_BUILD_VECTOR %mask_elt(s32), %mask_elt(s32)100 ; CHECK-NEXT: %and:_(<2 x s32>) = G_AND %load, %mask101 ; CHECK-NEXT: %inreg:_(<2 x s32>) = G_SEXT_INREG %and, 8102 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(<2 x s32>)103 %ptr:_(p1) = COPY $vgpr0_vgpr1104 %load:_(<2 x s32>) = G_LOAD %ptr :: (volatile load (<2 x s32>), addrspace 1, align 8)105 %mask_elt:_(s32) = G_CONSTANT i32 255106 %mask:_(<2 x s32>) = G_BUILD_VECTOR %mask_elt, %mask_elt107 %and:_(<2 x s32>) = G_AND %load, %mask108 %inreg:_(<2 x s32>) = G_SEXT_INREG %and, 8109 $vgpr0_vgpr1 = COPY %inreg110 111...112