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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s3 4---5name: shuffle_vector_to_extract6tracksRegLiveness: true7body: |8 bb.0:9 liveins: $vgpr0, $vgpr110 11 ; CHECK-LABEL: name: shuffle_vector_to_extract12 ; CHECK: liveins: $vgpr0, $vgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr116 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)17 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)18 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[UV6]](s16), [[UV7]](s16)19 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s16>), [[COPY1]](p3) :: (store (<4 x s16>), addrspace 3)20 ; CHECK-NEXT: SI_RETURN21 %0:_(p3) = COPY $vgpr022 %1:_(p3) = COPY $vgpr123 %2:_(<8 x s16>) = G_IMPLICIT_DEF24 %3:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)25 %4:_(<4 x s16>) = G_SHUFFLE_VECTOR %3(<8 x s16>), %2, shufflemask(4, 5, 6, 7)26 G_STORE %4(<4 x s16>), %1(p3) :: (store (<4 x s16>), addrspace 3)27 SI_RETURN28...29 30---31name: shuffle_vector_to_extract232tracksRegLiveness: true33body: |34 bb.0:35 liveins: $vgpr0, $vgpr136 37 ; CHECK-LABEL: name: shuffle_vector_to_extract238 ; CHECK: liveins: $vgpr0, $vgpr139 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr041 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr142 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)43 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)44 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[UV3]](s16), [[UV4]](s16)45 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s16>), [[COPY1]](p3) :: (store (<2 x s16>), addrspace 3)46 ; CHECK-NEXT: SI_RETURN47 %0:_(p3) = COPY $vgpr048 %1:_(p3) = COPY $vgpr149 %2:_(<8 x s16>) = G_IMPLICIT_DEF50 %3:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)51 %4:_(<2 x s16>) = G_SHUFFLE_VECTOR %3(<8 x s16>), %2, shufflemask(3, 4)52 G_STORE %4(<2 x s16>), %1(p3) :: (store (<2 x s16>), addrspace 3)53 SI_RETURN54 55...56 57---58name: shuffle_vector_to_extract_odd_elements59tracksRegLiveness: true60body: |61 bb.0:62 liveins: $vgpr0, $vgpr163 64 ; CHECK-LABEL: name: shuffle_vector_to_extract_odd_elements65 ; CHECK: liveins: $vgpr0, $vgpr166 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr068 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr169 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)70 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)71 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16)72 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<3 x s16>), [[COPY1]](p3) :: (store (<3 x s16>), align 8, addrspace 3)73 ; CHECK-NEXT: SI_RETURN74 %0:_(p3) = COPY $vgpr075 %1:_(p3) = COPY $vgpr176 %2:_(<8 x s16>) = G_IMPLICIT_DEF77 %3:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)78 %4:_(<3 x s16>) = G_SHUFFLE_VECTOR %3(<8 x s16>), %2, shufflemask(0, 1, 2)79 G_STORE %4(<3 x s16>), %1(p3) :: (store (<3 x s16>), addrspace 3)80 SI_RETURN81...82 83 84---85name: shuffle_vector_to_extract_minus_1_no_conversion86tracksRegLiveness: true87body: |88 bb.0:89 liveins: $vgpr0, $vgpr190 91 ; CHECK-LABEL: name: shuffle_vector_to_extract_minus_1_no_conversion92 ; CHECK: liveins: $vgpr0, $vgpr193 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr095 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr196 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)97 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)98 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF99 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[DEF]](s16), [[UV7]](s16)100 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s16>), [[COPY1]](p3) :: (store (<4 x s16>), addrspace 3)101 ; CHECK-NEXT: SI_RETURN102 %0:_(p3) = COPY $vgpr0103 %1:_(p3) = COPY $vgpr1104 %2:_(<8 x s16>) = G_IMPLICIT_DEF105 %3:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)106 %4:_(<4 x s16>) = G_SHUFFLE_VECTOR %3(<8 x s16>), %2, shufflemask(4, 5, -1, 7)107 G_STORE %4(<4 x s16>), %1(p3) :: (store (<4 x s16>), addrspace 3)108 SI_RETURN109...110 111---112name: shuffle_vector_to_extract_across_vectors_no_conversion113tracksRegLiveness: true114body: |115 bb.0:116 liveins: $vgpr0, $vgpr1117 118 ; CHECK-LABEL: name: shuffle_vector_to_extract_across_vectors_no_conversion119 ; CHECK: liveins: $vgpr0, $vgpr1120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0122 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1123 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)124 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)125 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF126 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV6]](s16), [[UV7]](s16), [[DEF]](s16), [[DEF]](s16)127 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s16>), [[COPY1]](p3) :: (store (<4 x s16>), addrspace 3)128 ; CHECK-NEXT: SI_RETURN129 %0:_(p3) = COPY $vgpr0130 %1:_(p3) = COPY $vgpr1131 %2:_(<8 x s16>) = G_IMPLICIT_DEF132 %3:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)133 %4:_(<4 x s16>) = G_SHUFFLE_VECTOR %3(<8 x s16>), %2, shufflemask(6, 7, 8, 9)134 G_STORE %4(<4 x s16>), %1(p3) :: (store (<4 x s16>), addrspace 3)135 SI_RETURN136...137 138 139---140name: shuffle_vector_to_copy141tracksRegLiveness: true142body: |143 bb.0:144 liveins: $vgpr0, $vgpr1145 ; CHECK-LABEL: name: shuffle_vector_to_copy146 ; CHECK: liveins: $vgpr0, $vgpr1147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0149 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1150 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8151 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)152 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p3) :: (load (s16), addrspace 3)153 ; CHECK-NEXT: G_STORE [[LOAD]](s16), [[COPY1]](p3) :: (store (s16), addrspace 3)154 ; CHECK-NEXT: SI_RETURN155 %0:_(p3) = COPY $vgpr0156 %1:_(p3) = COPY $vgpr1157 %2:_(<8 x s16>) = G_IMPLICIT_DEF158 %3:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)159 %idx:_(s32) = G_CONSTANT i32 4160 %4:_(s16) = G_EXTRACT_VECTOR_ELT %3(<8 x s16>), %idx161 G_STORE %4(s16), %1(p3) :: (store (s16), addrspace 3)162 SI_RETURN163...164