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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck %s3 4define amdgpu_ps void @readanylane_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {5; CHECK-LABEL: readanylane_to_virtual_vgpr:6; CHECK: ; %bb.0:7; CHECK-NEXT: v_mov_b32_e32 v0, 08; CHECK-NEXT: global_load_dword v1, v0, s[0:1] glc dlc9; CHECK-NEXT: s_waitcnt vmcnt(0)10; CHECK-NEXT: global_store_dword v0, v1, s[2:3]11; CHECK-NEXT: s_endpgm12 %load = load volatile float, ptr addrspace(1) %ptr013 store float %load, ptr addrspace(1) %ptr114 ret void15}16 17define amdgpu_ps float @readanylane_to_physical_vgpr(ptr addrspace(1) inreg %ptr) {18; CHECK-LABEL: readanylane_to_physical_vgpr:19; CHECK: ; %bb.0:20; CHECK-NEXT: v_mov_b32_e32 v0, 021; CHECK-NEXT: global_load_dword v0, v0, s[0:1] glc dlc22; CHECK-NEXT: s_waitcnt vmcnt(0)23; CHECK-NEXT: ; return to shader part epilog24 %load = load volatile float, ptr addrspace(1) %ptr25 ret float %load26}27 28define amdgpu_ps void @readanylane_to_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {29; CHECK-LABEL: readanylane_to_bitcast_to_virtual_vgpr:30; CHECK: ; %bb.0:31; CHECK-NEXT: v_mov_b32_e32 v0, 032; CHECK-NEXT: global_load_dword v1, v0, s[0:1] glc dlc33; CHECK-NEXT: s_waitcnt vmcnt(0)34; CHECK-NEXT: global_store_dword v0, v1, s[2:3]35; CHECK-NEXT: s_endpgm36 %load = load volatile <2 x i16>, ptr addrspace(1) %ptr037 %bitcast = bitcast <2 x i16> %load to i3238 store i32 %bitcast, ptr addrspace(1) %ptr139 ret void40}41 42define amdgpu_ps float @readanylane_to_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {43; CHECK-LABEL: readanylane_to_bitcast_to_physical_vgpr:44; CHECK: ; %bb.0:45; CHECK-NEXT: v_mov_b32_e32 v0, 046; CHECK-NEXT: global_load_dword v0, v0, s[0:1] glc dlc47; CHECK-NEXT: s_waitcnt vmcnt(0)48; CHECK-NEXT: ; return to shader part epilog49 %load = load volatile <2 x i16>, ptr addrspace(1) %ptr050 %bitcast = bitcast <2 x i16> %load to float51 ret float %bitcast52}53 54define amdgpu_ps void @unmerge_readanylane_merge_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {55; CHECK-LABEL: unmerge_readanylane_merge_to_virtual_vgpr:56; CHECK: ; %bb.0:57; CHECK-NEXT: v_mov_b32_e32 v2, 058; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc59; CHECK-NEXT: s_waitcnt vmcnt(0)60; CHECK-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]61; CHECK-NEXT: s_endpgm62 %load = load volatile i64, ptr addrspace(1) %ptr063 store i64 %load, ptr addrspace(1) %ptr164 ret void65}66 67;define amdgpu_ps double @unmerge_readanylane_merge_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {68; %load = load volatile double, ptr addrspace(1) %ptr069; ret double %load70;}71 72define amdgpu_ps void @unmerge_readanylane_merge_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {73; CHECK-LABEL: unmerge_readanylane_merge_bitcast_to_virtual_vgpr:74; CHECK: ; %bb.0:75; CHECK-NEXT: v_mov_b32_e32 v2, 076; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc77; CHECK-NEXT: s_waitcnt vmcnt(0)78; CHECK-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]79; CHECK-NEXT: s_endpgm80 %load = load volatile <2 x i32>, ptr addrspace(1) %ptr081 %bitcast = bitcast <2 x i32> %load to double82 store double %bitcast, ptr addrspace(1) %ptr183 ret void84}85 86;define amdgpu_ps double @unmerge_readanylane_merge_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {87; %load = load volatile <2 x i32>, ptr addrspace(1) %ptr088; %bitcast = bitcast <2 x i32> %load to double89; ret double %bitcast90;}91 92define amdgpu_ps void @unmerge_readanylane_merge_extract_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {93; CHECK-LABEL: unmerge_readanylane_merge_extract_to_virtual_vgpr:94; CHECK: ; %bb.0:95; CHECK-NEXT: v_mov_b32_e32 v2, 096; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc97; CHECK-NEXT: s_waitcnt vmcnt(0)98; CHECK-NEXT: global_store_dword v2, v1, s[2:3]99; CHECK-NEXT: s_endpgm100 %load = load volatile <2 x i32>, ptr addrspace(1) %ptr0101 %extracted = extractelement <2 x i32> %load, i32 1102 store i32 %extracted, ptr addrspace(1) %ptr1103 ret void104}105 106define amdgpu_ps float @unmerge_readanylane_merge_extract_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {107; CHECK-LABEL: unmerge_readanylane_merge_extract_to_physical_vgpr:108; CHECK: ; %bb.0:109; CHECK-NEXT: v_mov_b32_e32 v0, 0110; CHECK-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc111; CHECK-NEXT: s_waitcnt vmcnt(0)112; CHECK-NEXT: v_mov_b32_e32 v0, v1113; CHECK-NEXT: ; return to shader part epilog114 %load = load volatile <2 x float>, ptr addrspace(1) %ptr0115 %extracted = extractelement <2 x float> %load, i32 1116 ret float %extracted117}118 119define amdgpu_ps void @unmerge_readanylane_merge_extract_bitcast_to_virtual_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {120; CHECK-LABEL: unmerge_readanylane_merge_extract_bitcast_to_virtual_vgpr:121; CHECK: ; %bb.0:122; CHECK-NEXT: v_mov_b32_e32 v2, 0123; CHECK-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc124; CHECK-NEXT: s_waitcnt vmcnt(0)125; CHECK-NEXT: global_store_dword v2, v0, s[2:3]126; CHECK-NEXT: s_endpgm127 %load = load volatile <4 x i16>, ptr addrspace(1) %ptr0128 %extracted = shufflevector <4 x i16> %load, <4 x i16> %load, <2 x i32> <i32 0, i32 1>129 %bitcast = bitcast <2 x i16> %extracted to float130 store float %bitcast, ptr addrspace(1) %ptr1131 ret void132}133 134define amdgpu_ps float @unmerge_readanylane_merge_extract_bitcast_to_physical_vgpr(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {135; CHECK-LABEL: unmerge_readanylane_merge_extract_bitcast_to_physical_vgpr:136; CHECK: ; %bb.0:137; CHECK-NEXT: v_mov_b32_e32 v0, 0138; CHECK-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc139; CHECK-NEXT: s_waitcnt vmcnt(0)140; CHECK-NEXT: ; return to shader part epilog141 %load = load volatile <4 x i16>, ptr addrspace(1) %ptr0142 %extracted = shufflevector <4 x i16> %load, <4 x i16> %load, <2 x i32> <i32 0, i32 1>143 %bitcast = bitcast <2 x i16> %extracted to float144 ret float %bitcast145}146