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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=GFX124---5name: test_fmed3_f32_known_nnan_ieee_true6legalized: true7regBankSelected: true8tracksRegLiveness: true9machineFunctionInfo:10 mode:11 ieee: true12 dx10-clamp: true13body: |14 bb.1 :15 liveins: $vgpr016 17 ; CHECK-LABEL: name: test_fmed3_f32_known_nnan_ieee_true18 ; CHECK: liveins: $vgpr019 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr021 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+0022 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)23 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]24 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]25 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)26 ;27 ; GFX12-LABEL: name: test_fmed3_f32_known_nnan_ieee_true28 ; GFX12: liveins: $vgpr029 ; GFX12-NEXT: {{ $}}30 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr031 ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+0032 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)33 ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]34 ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]35 ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)36 %0:vgpr(s32) = COPY $vgpr037 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+0038 %8:vgpr(s32) = COPY %2(s32)39 %3:vgpr(s32) = G_FMUL %0, %840 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+0041 %5:sgpr(s32) = G_FCONSTANT float 0.000000e+0042 %9:vgpr(s32) = COPY %5(s32)43 %10:vgpr(s32) = COPY %6(s32)44 %4:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %9(s32), %10(s32)45 $vgpr0 = COPY %4(s32)46...47 48---49name: test_fmed3_f16_known_nnan_ieee_false50legalized: true51regBankSelected: true52tracksRegLiveness: true53machineFunctionInfo:54 mode:55 ieee: false56 dx10-clamp: true57body: |58 bb.1 :59 liveins: $vgpr060 61 ; CHECK-LABEL: name: test_fmed3_f16_known_nnan_ieee_false62 ; CHECK: liveins: $vgpr063 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr065 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)66 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH400067 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)68 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]69 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]70 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16)71 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)72 ;73 ; GFX12-LABEL: name: test_fmed3_f16_known_nnan_ieee_false74 ; GFX12: liveins: $vgpr075 ; GFX12-NEXT: {{ $}}76 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr077 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)78 ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH400079 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)80 ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]81 ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]82 ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16)83 ; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)84 %2:vgpr(s32) = COPY $vgpr085 %0:vgpr(s16) = G_TRUNC %2(s32)86 %3:sgpr(s16) = G_FCONSTANT half 0xH400087 %10:vgpr(s16) = COPY %3(s16)88 %4:vgpr(s16) = G_FMUL %0, %1089 %7:sgpr(s16) = G_FCONSTANT half 0xH3C0090 %6:sgpr(s16) = G_FCONSTANT half 0xH000091 %11:vgpr(s16) = COPY %6(s16)92 %12:vgpr(s16) = COPY %7(s16)93 %5:vgpr(s16) = nnan G_AMDGPU_FMED3 %4(s16), %11(s16), %12(s16)94 %9:vgpr(s32) = G_ANYEXT %5(s16)95 $vgpr0 = COPY %9(s32)96...97 98---99name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true100legalized: true101regBankSelected: true102tracksRegLiveness: true103machineFunctionInfo:104 mode:105 ieee: true106 dx10-clamp: true107body: |108 bb.1 :109 liveins: $vgpr0110 111 ; CHECK-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true112 ; CHECK: liveins: $vgpr0113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0115 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01116 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]117 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)118 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]119 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]]120 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)121 ;122 ; GFX12-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true123 ; GFX12: liveins: $vgpr0124 ; GFX12-NEXT: {{ $}}125 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0126 ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01127 ; GFX12-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]128 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)129 ; GFX12-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]130 ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]]131 ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)132 %0:vgpr(s32) = COPY $vgpr0133 %2:sgpr(s32) = G_FCONSTANT float 1.000000e+01134 %8:vgpr(s32) = G_FCANONICALIZE %0135 %9:vgpr(s32) = COPY %2(s32)136 %3:vgpr(s32) = G_FMINNUM_IEEE %8, %9137 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00138 %5:sgpr(s32) = G_FCONSTANT float 0.000000e+00139 %10:vgpr(s32) = COPY %5(s32)140 %11:vgpr(s32) = COPY %6(s32)141 %4:vgpr(s32) = G_AMDGPU_FMED3 %3(s32), %10(s32), %11(s32)142 $vgpr0 = COPY %4(s32)143...144 145---146name: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true147legalized: true148regBankSelected: true149tracksRegLiveness: true150machineFunctionInfo:151 mode:152 ieee: true153 dx10-clamp: true154body: |155 bb.1 :156 liveins: $vgpr0157 158 ; CHECK-LABEL: name: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true159 ; CHECK: liveins: $vgpr0160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0162 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00163 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)164 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]165 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]166 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)167 ;168 ; GFX12-LABEL: name: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true169 ; GFX12: liveins: $vgpr0170 ; GFX12-NEXT: {{ $}}171 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0172 ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00173 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)174 ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]175 ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]176 ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)177 %0:vgpr(s32) = COPY $vgpr0178 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00179 %8:vgpr(s32) = COPY %2(s32)180 %3:vgpr(s32) = G_FMUL %0, %8181 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00182 %5:sgpr(s32) = G_FCONSTANT float 1.000000e+00183 %9:vgpr(s32) = COPY %5(s32)184 %10:vgpr(s32) = COPY %6(s32)185 %4:vgpr(s32) = G_AMDGPU_FMED3 %3(s32), %9(s32), %10(s32)186 $vgpr0 = COPY %4(s32)187...188 189# FixMe: add tests with attributes #3 = {"no-nans-fp-math"="true"}190 191---192name: test_fmed3_f32_maybe_NaN_ieee_false193legalized: true194regBankSelected: true195tracksRegLiveness: true196machineFunctionInfo:197 mode:198 ieee: false199 dx10-clamp: true200body: |201 bb.1 :202 liveins: $vgpr0203 204 ; CHECK-LABEL: name: test_fmed3_f32_maybe_NaN_ieee_false205 ; CHECK: liveins: $vgpr0206 ; CHECK-NEXT: {{ $}}207 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0208 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00209 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)210 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]211 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00212 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00213 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)214 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)215 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FMED3 [[FMUL]], [[COPY2]], [[COPY3]]216 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)217 ;218 ; GFX12-LABEL: name: test_fmed3_f32_maybe_NaN_ieee_false219 ; GFX12: liveins: $vgpr0220 ; GFX12-NEXT: {{ $}}221 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0222 ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00223 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)224 ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]225 ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]226 ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)227 %0:vgpr(s32) = COPY $vgpr0228 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00229 %8:vgpr(s32) = COPY %2(s32)230 %3:vgpr(s32) = G_FMUL %0, %8231 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00232 %5:sgpr(s32) = G_FCONSTANT float 1.000000e+00233 %9:vgpr(s32) = COPY %5(s32)234 %10:vgpr(s32) = COPY %6(s32)235 %4:vgpr(s32) = G_AMDGPU_FMED3 %3(s32), %9(s32), %10(s32)236 $vgpr0 = COPY %4(s32)237...238 239---240name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false241legalized: true242regBankSelected: true243tracksRegLiveness: true244machineFunctionInfo:245 mode:246 ieee: true247 dx10-clamp: false248body: |249 bb.1 :250 liveins: $vgpr0251 252 ; CHECK-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false253 ; CHECK: liveins: $vgpr0254 ; CHECK-NEXT: {{ $}}255 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0256 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01257 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]258 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)259 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]260 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00261 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00262 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)263 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)264 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FMED3 [[FMINNUM_IEEE]], [[COPY2]], [[COPY3]]265 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)266 ;267 ; GFX12-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false268 ; GFX12: liveins: $vgpr0269 ; GFX12-NEXT: {{ $}}270 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0271 ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01272 ; GFX12-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]273 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)274 ; GFX12-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]275 ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]]276 ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)277 %0:vgpr(s32) = COPY $vgpr0278 %2:sgpr(s32) = G_FCONSTANT float 1.000000e+01279 %8:vgpr(s32) = G_FCANONICALIZE %0280 %9:vgpr(s32) = COPY %2(s32)281 %3:vgpr(s32) = G_FMINNUM_IEEE %8, %9282 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00283 %5:sgpr(s32) = G_FCONSTANT float 0.000000e+00284 %10:vgpr(s32) = COPY %5(s32)285 %11:vgpr(s32) = COPY %6(s32)286 %4:vgpr(s32) = G_AMDGPU_FMED3 %3(s32), %10(s32), %11(s32)287 $vgpr0 = COPY %4(s32)288...289 290---291name: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true292legalized: true293regBankSelected: true294tracksRegLiveness: true295machineFunctionInfo:296 mode:297 ieee: true298 dx10-clamp: true299body: |300 bb.1 :301 liveins: $vgpr0302 303 ; CHECK-LABEL: name: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true304 ; CHECK: liveins: $vgpr0305 ; CHECK-NEXT: {{ $}}306 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0307 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00308 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)309 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]310 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]311 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)312 ;313 ; GFX12-LABEL: name: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true314 ; GFX12: liveins: $vgpr0315 ; GFX12-NEXT: {{ $}}316 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0317 ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00318 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)319 ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]320 ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]321 ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)322 %0:vgpr(s32) = COPY $vgpr0323 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00324 %8:vgpr(s32) = COPY %2(s32)325 %3:vgpr(s32) = G_FMUL %0, %8326 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00327 %5:sgpr(s32) = G_FCONSTANT float 0.000000e+00328 %9:vgpr(s32) = COPY %5(s32)329 %10:vgpr(s32) = COPY %6(s32)330 %4:vgpr(s32) = G_AMDGPU_FMED3 %3(s32), %9(s32), %10(s32)331 $vgpr0 = COPY %4(s32)332...333