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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: test_min_max_ValK0_K1_f326legalized: true7regBankSelected: true8tracksRegLiveness: true9machineFunctionInfo:10 mode:11 ieee: true12 dx10-clamp: true13body: |14 bb.1 :15 liveins: $vgpr016 17 ; CHECK-LABEL: name: test_min_max_ValK0_K1_f3218 ; CHECK: liveins: $vgpr019 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr021 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+0022 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)23 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]24 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]25 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)26 %0:vgpr(s32) = COPY $vgpr027 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+0028 %9:vgpr(s32) = COPY %2(s32)29 %3:vgpr(s32) = G_FMUL %0, %930 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+0031 %10:vgpr(s32) = COPY %4(s32)32 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %1033 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+0034 %11:vgpr(s32) = COPY %6(s32)35 %7:vgpr(s32) = nnan G_FMINNUM_IEEE %5, %1136 $vgpr0 = COPY %7(s32)37...38 39---40name: test_min_max_K0Val_K1_f6441legalized: true42regBankSelected: true43tracksRegLiveness: true44machineFunctionInfo:45 mode:46 ieee: false47 dx10-clamp: true48body: |49 bb.1 :50 liveins: $vgpr0_vgpr151 52 ; CHECK-LABEL: name: test_min_max_K0Val_K1_f6453 ; CHECK: liveins: $vgpr0_vgpr154 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr156 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+0057 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)58 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s64) = G_FMUL [[COPY]], [[COPY1]]59 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s64) = nnan G_AMDGPU_CLAMP [[FMUL]]60 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_CLAMP]](s64)61 %0:vgpr(s64) = COPY $vgpr0_vgpr162 %4:sgpr(s64) = G_FCONSTANT double 2.000000e+0063 %13:vgpr(s64) = COPY %4(s64)64 %5:vgpr(s64) = G_FMUL %0, %1365 %6:sgpr(s64) = G_FCONSTANT double 0.000000e+0066 %14:vgpr(s64) = COPY %6(s64)67 %7:vgpr(s64) = nnan G_FMAXNUM %14, %568 %8:sgpr(s64) = G_FCONSTANT double 1.000000e+0069 %15:vgpr(s64) = COPY %8(s64)70 %9:vgpr(s64) = nnan G_FMINNUM %7, %1571 $vgpr0_vgpr1 = COPY %9(s64)72...73 74---75name: test_min_K1max_ValK0_f1676legalized: true77regBankSelected: true78tracksRegLiveness: true79machineFunctionInfo:80 mode:81 ieee: true82 dx10-clamp: true83body: |84 bb.1 :85 liveins: $vgpr086 87 ; CHECK-LABEL: name: test_min_K1max_ValK0_f1688 ; CHECK: liveins: $vgpr089 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr091 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)92 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH400093 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)94 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]95 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[FMUL]]96 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = G_AMDGPU_CLAMP [[FCANONICALIZE]]97 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16)98 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)99 %2:vgpr(s32) = COPY $vgpr0100 %0:vgpr(s16) = G_TRUNC %2(s32)101 %3:sgpr(s16) = G_FCONSTANT half 0xH4000102 %12:vgpr(s16) = COPY %3(s16)103 %4:vgpr(s16) = G_FMUL %0, %12104 %5:sgpr(s16) = G_FCONSTANT half 0xH0000105 %11:vgpr(s16) = G_FCANONICALIZE %4106 %13:vgpr(s16) = COPY %5(s16)107 %6:vgpr(s16) = G_FMAXNUM_IEEE %11, %13108 %7:sgpr(s16) = G_FCONSTANT half 0xH3C00109 %14:vgpr(s16) = COPY %7(s16)110 %8:vgpr(s16) = G_FMINNUM_IEEE %14, %6111 %10:vgpr(s32) = G_ANYEXT %8(s16)112 $vgpr0 = COPY %10(s32)113...114 115---116name: test_min_K1max_K0Val_f16117legalized: true118regBankSelected: true119tracksRegLiveness: true120machineFunctionInfo:121 mode:122 ieee: false123 dx10-clamp: true124body: |125 bb.1 :126 liveins: $vgpr0127 128 ; CHECK-LABEL: name: test_min_K1max_K0Val_f16129 ; CHECK: liveins: $vgpr0130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0132 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000133 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)134 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)135 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)136 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]]137 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_AMDGPU_CLAMP [[FMUL]]138 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>)139 %0:vgpr(<2 x s16>) = COPY $vgpr0140 %3:sgpr(s16) = G_FCONSTANT half 0xH4000141 %12:sgpr(s32) = G_ANYEXT %3(s16)142 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %12(s32), %12(s32)143 %6:sgpr(s16) = G_FCONSTANT half 0xH0000144 %13:sgpr(s32) = G_ANYEXT %6(s16)145 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %13(s32), %13(s32)146 %9:sgpr(s16) = G_FCONSTANT half 0xH3C00147 %14:sgpr(s32) = G_ANYEXT %9(s16)148 %8:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %14(s32), %14(s32)149 %15:vgpr(<2 x s16>) = COPY %2(<2 x s16>)150 %4:vgpr(<2 x s16>) = G_FMUL %0, %15151 %16:vgpr(<2 x s16>) = COPY %5(<2 x s16>)152 %7:vgpr(<2 x s16>) = nnan G_FMAXNUM %16, %4153 %17:vgpr(<2 x s16>) = COPY %8(<2 x s16>)154 %10:vgpr(<2 x s16>) = nnan G_FMINNUM %17, %7155 $vgpr0 = COPY %10(<2 x s16>)156...157 158---159name: test_min_max_splat_padded_with_undef160legalized: true161regBankSelected: true162tracksRegLiveness: true163machineFunctionInfo:164 mode:165 ieee: true166 dx10-clamp: true167body: |168 bb.1 :169 liveins: $vgpr0170 171 ; CHECK-LABEL: name: test_min_max_splat_padded_with_undef172 ; CHECK: liveins: $vgpr0173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0175 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000176 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)177 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)178 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)179 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]]180 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(<2 x s16>) = G_FCANONICALIZE [[FMUL]]181 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_CLAMP [[FCANONICALIZE]]182 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>)183 %0:vgpr(<2 x s16>) = COPY $vgpr0184 %3:sgpr(s16) = G_FCONSTANT half 0xH4000185 %17:sgpr(s32) = G_ANYEXT %3(s16)186 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %17(s32), %17(s32)187 %6:sgpr(s16) = G_FCONSTANT half 0xH0000188 %18:sgpr(s32) = G_ANYEXT %6(s16)189 %19:sgpr(s32) = G_IMPLICIT_DEF190 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %18(s32), %19(s32)191 %10:sgpr(s16) = G_FCONSTANT half 0xH3C00192 %20:sgpr(s32) = G_ANYEXT %10(s16)193 %9:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %20(s32), %19(s32)194 %21:vgpr(<2 x s16>) = COPY %2(<2 x s16>)195 %4:vgpr(<2 x s16>) = G_FMUL %0, %21196 %16:vgpr(<2 x s16>) = G_FCANONICALIZE %4197 %22:vgpr(<2 x s16>) = COPY %5(<2 x s16>)198 %8:vgpr(<2 x s16>) = G_FMAXNUM_IEEE %22, %16199 %23:vgpr(<2 x s16>) = COPY %9(<2 x s16>)200 %11:vgpr(<2 x s16>) = G_FMINNUM_IEEE %23, %8201 $vgpr0 = COPY %11(<2 x s16>)202...203 204---205name: test_max_min_ValK1_K0_f32206machineFunctionInfo:207 mode:208 ieee: true209 dx10-clamp: true210body: |211 bb.1 :212 liveins: $vgpr0213 214 ; CHECK-LABEL: name: test_max_min_ValK1_K0_f32215 ; CHECK: liveins: $vgpr0216 ; CHECK-NEXT: {{ $}}217 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0218 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00219 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)220 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]221 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]222 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)223 %0:vgpr(s32) = COPY $vgpr0224 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00225 %9:vgpr(s32) = COPY %2(s32)226 %3:vgpr(s32) = G_FMUL %0, %9227 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00228 %10:vgpr(s32) = COPY %4(s32)229 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %10230 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00231 %11:vgpr(s32) = COPY %6(s32)232 %7:vgpr(s32) = nnan G_FMAXNUM_IEEE %5, %11233 $vgpr0 = COPY %7(s32)234...235 236---237name: test_max_min_K1Val_K0_f64238legalized: true239regBankSelected: true240tracksRegLiveness: true241machineFunctionInfo:242 mode:243 ieee: false244 dx10-clamp: true245body: |246 bb.1 :247 liveins: $vgpr0_vgpr1248 249 ; CHECK-LABEL: name: test_max_min_K1Val_K0_f64250 ; CHECK: liveins: $vgpr0_vgpr1251 ; CHECK-NEXT: {{ $}}252 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1253 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00254 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)255 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s64) = G_FMUL [[COPY]], [[COPY1]]256 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s64) = nnan G_AMDGPU_CLAMP [[FMUL]]257 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_CLAMP]](s64)258 %0:vgpr(s64) = COPY $vgpr0_vgpr1259 %4:sgpr(s64) = G_FCONSTANT double 2.000000e+00260 %13:vgpr(s64) = COPY %4(s64)261 %5:vgpr(s64) = G_FMUL %0, %13262 %6:sgpr(s64) = G_FCONSTANT double 1.000000e+00263 %14:vgpr(s64) = COPY %6(s64)264 %7:vgpr(s64) = nnan G_FMINNUM %14, %5265 %8:sgpr(s64) = G_FCONSTANT double 0.000000e+00266 %15:vgpr(s64) = COPY %8(s64)267 %9:vgpr(s64) = nnan G_FMAXNUM %7, %15268 $vgpr0_vgpr1 = COPY %9(s64)269...270 271---272name: test_max_K0min_ValK1_f16273legalized: true274regBankSelected: true275tracksRegLiveness: true276machineFunctionInfo:277 mode:278 ieee: true279 dx10-clamp: true280body: |281 bb.1 :282 liveins: $vgpr0283 284 ; CHECK-LABEL: name: test_max_K0min_ValK1_f16285 ; CHECK: liveins: $vgpr0286 ; CHECK-NEXT: {{ $}}287 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0288 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)289 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000290 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)291 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]292 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]293 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16)294 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)295 %2:vgpr(s32) = COPY $vgpr0296 %0:vgpr(s16) = G_TRUNC %2(s32)297 %3:sgpr(s16) = G_FCONSTANT half 0xH4000298 %11:vgpr(s16) = COPY %3(s16)299 %4:vgpr(s16) = G_FMUL %0, %11300 %5:sgpr(s16) = G_FCONSTANT half 0xH3C00301 %12:vgpr(s16) = COPY %5(s16)302 %6:vgpr(s16) = nnan G_FMINNUM_IEEE %4, %12303 %7:sgpr(s16) = G_FCONSTANT half 0xH0000304 %13:vgpr(s16) = COPY %7(s16)305 %8:vgpr(s16) = nnan G_FMAXNUM_IEEE %13, %6306 %10:vgpr(s32) = G_ANYEXT %8(s16)307 $vgpr0 = COPY %10(s32)308...309 310---311name: test_max_K0min_K1Val_v2f16312legalized: true313regBankSelected: true314tracksRegLiveness: true315machineFunctionInfo:316 mode:317 ieee: false318 dx10-clamp: true319body: |320 bb.1 :321 liveins: $vgpr0322 323 ; CHECK-LABEL: name: test_max_K0min_K1Val_v2f16324 ; CHECK: liveins: $vgpr0325 ; CHECK-NEXT: {{ $}}326 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0327 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000328 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)329 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)330 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)331 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]]332 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_AMDGPU_CLAMP [[FMUL]]333 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>)334 %0:vgpr(<2 x s16>) = COPY $vgpr0335 %3:sgpr(s16) = G_FCONSTANT half 0xH4000336 %13:sgpr(s32) = G_ANYEXT %3(s16)337 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %13(s32), %13(s32)338 %6:sgpr(s16) = G_FCONSTANT half 0xH3C00339 %14:sgpr(s32) = G_ANYEXT %6(s16)340 %15:sgpr(s32) = G_IMPLICIT_DEF341 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %14(s32), %15(s32)342 %10:sgpr(s16) = G_FCONSTANT half 0xH0000343 %16:sgpr(s32) = G_ANYEXT %10(s16)344 %9:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %15(s32), %16(s32)345 %17:vgpr(<2 x s16>) = COPY %2(<2 x s16>)346 %4:vgpr(<2 x s16>) = G_FMUL %0, %17347 %18:vgpr(<2 x s16>) = COPY %5(<2 x s16>)348 %8:vgpr(<2 x s16>) = nnan G_FMINNUM %18, %4349 %19:vgpr(<2 x s16>) = COPY %9(<2 x s16>)350 %11:vgpr(<2 x s16>) = nnan G_FMAXNUM %19, %8351 $vgpr0 = COPY %11(<2 x s16>)352...353 354# FixMe: add tests with attributes #3 = {"no-nans-fp-math"="true"}355 356---357name: test_min_max_K0_gt_K1358legalized: true359regBankSelected: true360tracksRegLiveness: true361machineFunctionInfo:362 mode:363 ieee: true364 dx10-clamp: true365body: |366 bb.1 :367 liveins: $vgpr0368 369 ; CHECK-LABEL: name: test_min_max_K0_gt_K1370 ; CHECK: liveins: $vgpr0371 ; CHECK-NEXT: {{ $}}372 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0373 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00374 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)375 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]376 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00377 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)378 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]379 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)380 %0:vgpr(s32) = COPY $vgpr0381 %2:sgpr(s32) = G_FCONSTANT float 1.000000e+00382 %7:vgpr(s32) = COPY %2(s32)383 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7384 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00385 %8:vgpr(s32) = COPY %4(s32)386 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8387 $vgpr0 = COPY %5(s32)388...389 390---391name: test_max_min_K0_gt_K1392legalized: true393regBankSelected: true394tracksRegLiveness: true395machineFunctionInfo:396 mode:397 ieee: true398 dx10-clamp: true399body: |400 bb.1 :401 liveins: $vgpr0402 403 ; CHECK-LABEL: name: test_max_min_K0_gt_K1404 ; CHECK: liveins: $vgpr0405 ; CHECK-NEXT: {{ $}}406 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0407 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00408 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)409 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]410 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00411 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)412 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]413 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)414 %0:vgpr(s32) = COPY $vgpr0415 %2:sgpr(s32) = G_FCONSTANT float 0.000000e+00416 %7:vgpr(s32) = COPY %2(s32)417 %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7418 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00419 %8:vgpr(s32) = COPY %4(s32)420 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8421 $vgpr0 = COPY %5(s32)422...423 424---425name: test_min_max_maybe_NaN_input_ieee_false426legalized: true427regBankSelected: true428tracksRegLiveness: true429machineFunctionInfo:430 mode:431 ieee: false432 dx10-clamp: true433body: |434 bb.1 :435 liveins: $vgpr0436 437 ; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_false438 ; CHECK: liveins: $vgpr0439 ; CHECK-NEXT: {{ $}}440 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0441 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00442 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)443 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]444 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00445 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)446 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMUL]], [[COPY2]]447 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00448 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)449 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY3]]450 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)451 %0:vgpr(s32) = COPY $vgpr0452 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00453 %9:vgpr(s32) = COPY %2(s32)454 %3:vgpr(s32) = G_FMUL %0, %9455 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00456 %10:vgpr(s32) = COPY %4(s32)457 %5:vgpr(s32) = G_FMAXNUM %3, %10458 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00459 %11:vgpr(s32) = COPY %6(s32)460 %7:vgpr(s32) = G_FMINNUM %5, %11461 $vgpr0 = COPY %7(s32)462...463 464---465name: test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false466legalized: true467regBankSelected: true468tracksRegLiveness: true469machineFunctionInfo:470 mode:471 ieee: true472 dx10-clamp: false473body: |474 bb.1 :475 liveins: $vgpr0476 477 ; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false478 ; CHECK: liveins: $vgpr0479 ; CHECK-NEXT: {{ $}}480 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0481 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00482 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)483 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]484 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00485 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[FMUL]]486 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)487 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00488 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)489 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FMED3 [[FCANONICALIZE]], [[COPY2]], [[COPY3]]490 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)491 %0:vgpr(s32) = COPY $vgpr0492 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00493 %10:vgpr(s32) = COPY %2(s32)494 %3:vgpr(s32) = G_FMUL %0, %10495 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00496 %9:vgpr(s32) = G_FCANONICALIZE %3497 %11:vgpr(s32) = COPY %4(s32)498 %5:vgpr(s32) = G_FMAXNUM_IEEE %9, %11499 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00500 %12:vgpr(s32) = COPY %6(s32)501 %7:vgpr(s32) = G_FMINNUM_IEEE %5, %12502 $vgpr0 = COPY %7(s32)503...504 505---506name: test_max_min_maybe_NaN_input_ieee_true507legalized: true508regBankSelected: true509tracksRegLiveness: true510machineFunctionInfo:511 mode:512 ieee: true513 dx10-clamp: true514body: |515 bb.1 :516 liveins: $vgpr0517 518 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_true519 ; CHECK: liveins: $vgpr0520 ; CHECK-NEXT: {{ $}}521 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0522 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00523 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)524 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]525 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00526 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[FMUL]]527 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)528 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY2]]529 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00530 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)531 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY3]]532 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)533 %0:vgpr(s32) = COPY $vgpr0534 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00535 %10:vgpr(s32) = COPY %2(s32)536 %3:vgpr(s32) = G_FMUL %0, %10537 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00538 %9:vgpr(s32) = G_FCANONICALIZE %3539 %11:vgpr(s32) = COPY %4(s32)540 %5:vgpr(s32) = G_FMINNUM_IEEE %9, %11541 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00542 %12:vgpr(s32) = COPY %6(s32)543 %7:vgpr(s32) = G_FMAXNUM_IEEE %5, %12544 $vgpr0 = COPY %7(s32)545...546 547---548name: test_max_min_maybe_NaN_input_ieee_false549legalized: true550regBankSelected: true551tracksRegLiveness: true552machineFunctionInfo:553 mode:554 ieee: false555 dx10-clamp: true556body: |557 bb.1 :558 liveins: $vgpr0559 560 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_false561 ; CHECK: liveins: $vgpr0562 ; CHECK-NEXT: {{ $}}563 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0564 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00565 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)566 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]567 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00568 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)569 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMUL]], [[COPY2]]570 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00571 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)572 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY3]]573 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)574 %0:vgpr(s32) = COPY $vgpr0575 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00576 %9:vgpr(s32) = COPY %2(s32)577 %3:vgpr(s32) = G_FMUL %0, %9578 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00579 %10:vgpr(s32) = COPY %4(s32)580 %5:vgpr(s32) = G_FMINNUM %3, %10581 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00582 %11:vgpr(s32) = COPY %6(s32)583 %7:vgpr(s32) = G_FMAXNUM %5, %11584 $vgpr0 = COPY %7(s32)585...586