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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: test_min_max_ValK0_K1_f326legalized: true7regBankSelected: true8tracksRegLiveness: true9machineFunctionInfo:10 mode:11 ieee: true12body: |13 bb.1:14 liveins: $vgpr015 16 ; CHECK-LABEL: name: test_min_max_ValK0_K1_f3217 ; CHECK: liveins: $vgpr018 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr020 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+0021 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)22 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+0023 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)24 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY1]], [[COPY2]]25 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)26 %0:vgpr(s32) = COPY $vgpr027 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+0028 %7:vgpr(s32) = COPY %2(s32)29 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %730 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+0031 %8:vgpr(s32) = COPY %4(s32)32 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %833 $vgpr0 = COPY %5(s32)34...35 36---37name: test_min_max_K0Val_K1_f3238legalized: true39regBankSelected: true40tracksRegLiveness: true41machineFunctionInfo:42 mode:43 ieee: false44body: |45 bb.1:46 liveins: $vgpr047 48 ; CHECK-LABEL: name: test_min_max_K0Val_K1_f3249 ; CHECK: liveins: $vgpr050 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr052 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+0053 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)54 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+0055 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)56 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY1]], [[COPY2]]57 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)58 %0:vgpr(s32) = COPY $vgpr059 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+0060 %7:vgpr(s32) = COPY %2(s32)61 %3:vgpr(s32) = nnan G_FMAXNUM %7, %062 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+0063 %8:vgpr(s32) = COPY %4(s32)64 %5:vgpr(s32) = nnan G_FMINNUM %3, %865 $vgpr0 = COPY %5(s32)66...67 68---69name: test_min_K1max_ValK0_f1670legalized: true71regBankSelected: true72tracksRegLiveness: true73machineFunctionInfo:74 mode:75 ieee: true76body: |77 bb.1:78 liveins: $vgpr079 80 ; CHECK-LABEL: name: test_min_K1max_ValK0_f1681 ; CHECK: liveins: $vgpr082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr084 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)85 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH400086 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[TRUNC]]87 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)88 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH440089 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)90 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = G_AMDGPU_FMED3 [[FCANONICALIZE]], [[COPY1]], [[COPY2]]91 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)92 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)93 %2:vgpr(s32) = COPY $vgpr094 %0:vgpr(s16) = G_TRUNC %2(s32)95 %3:sgpr(s16) = G_FCONSTANT half 0xH400096 %9:vgpr(s16) = G_FCANONICALIZE %097 %10:vgpr(s16) = COPY %3(s16)98 %4:vgpr(s16) = G_FMAXNUM_IEEE %9, %1099 %5:sgpr(s16) = G_FCONSTANT half 0xH4400100 %11:vgpr(s16) = COPY %5(s16)101 %6:vgpr(s16) = G_FMINNUM_IEEE %11, %4102 %8:vgpr(s32) = G_ANYEXT %6(s16)103 $vgpr0 = COPY %8(s32)104 105...106 107---108name: test_min_K1max_K0Val_f16109legalized: true110regBankSelected: true111tracksRegLiveness: true112machineFunctionInfo:113 mode:114 ieee: false115body: |116 bb.1:117 liveins: $vgpr0, $sgpr30_sgpr31118 119 ; CHECK-LABEL: name: test_min_K1max_K0Val_f16120 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0123 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)124 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000125 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)126 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400127 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)128 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY1]], [[COPY2]]129 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)130 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)131 %2:vgpr(s32) = COPY $vgpr0132 %0:vgpr(s16) = G_TRUNC %2(s32)133 %3:sgpr(s16) = G_FCONSTANT half 0xH4000134 %9:vgpr(s16) = COPY %3(s16)135 %4:vgpr(s16) = nnan G_FMAXNUM %9, %0136 %5:sgpr(s16) = G_FCONSTANT half 0xH4400137 %10:vgpr(s16) = COPY %5(s16)138 %6:vgpr(s16) = nnan G_FMINNUM %10, %4139 %8:vgpr(s32) = G_ANYEXT %6(s16)140 $vgpr0 = COPY %8(s32)141...142 143---144name: test_max_min_ValK1_K0_f32145legalized: true146regBankSelected: true147tracksRegLiveness: true148machineFunctionInfo:149 mode:150 ieee: true151body: |152 bb.1:153 liveins: $vgpr0154 155 ; CHECK-LABEL: name: test_max_min_ValK1_K0_f32156 ; CHECK: liveins: $vgpr0157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0159 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00160 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)161 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00162 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)163 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY2]], [[COPY1]]164 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)165 %0:vgpr(s32) = COPY $vgpr0166 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00167 %7:vgpr(s32) = COPY %2(s32)168 %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7169 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00170 %8:vgpr(s32) = COPY %4(s32)171 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8172 $vgpr0 = COPY %5(s32)173...174 175---176name: test_max_min_K1Val_K0_f32177legalized: true178regBankSelected: true179tracksRegLiveness: true180machineFunctionInfo:181 mode:182 ieee: false183body: |184 bb.1:185 liveins: $vgpr0186 187 ; CHECK-LABEL: name: test_max_min_K1Val_K0_f32188 ; CHECK: liveins: $vgpr0189 ; CHECK-NEXT: {{ $}}190 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0191 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00192 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)193 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00194 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)195 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY2]], [[COPY1]]196 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)197 %0:vgpr(s32) = COPY $vgpr0198 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00199 %7:vgpr(s32) = COPY %2(s32)200 %3:vgpr(s32) = nnan G_FMINNUM %7, %0201 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00202 %8:vgpr(s32) = COPY %4(s32)203 %5:vgpr(s32) = nnan G_FMAXNUM %3, %8204 $vgpr0 = COPY %5(s32)205...206 207---208name: test_max_K0min_ValK1_f16209legalized: true210regBankSelected: true211tracksRegLiveness: true212machineFunctionInfo:213 mode:214 ieee: true215body: |216 bb.1:217 liveins: $vgpr0218 219 ; CHECK-LABEL: name: test_max_K0min_ValK1_f16220 ; CHECK: liveins: $vgpr0221 ; CHECK-NEXT: {{ $}}222 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0223 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)224 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400225 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)226 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000227 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)228 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]]229 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)230 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)231 %2:vgpr(s32) = COPY $vgpr0232 %0:vgpr(s16) = G_TRUNC %2(s32)233 %3:sgpr(s16) = G_FCONSTANT half 0xH4400234 %9:vgpr(s16) = COPY %3(s16)235 %4:vgpr(s16) = nnan G_FMINNUM_IEEE %0, %9236 %5:sgpr(s16) = G_FCONSTANT half 0xH4000237 %10:vgpr(s16) = COPY %5(s16)238 %6:vgpr(s16) = nnan G_FMAXNUM_IEEE %10, %4239 %8:vgpr(s32) = G_ANYEXT %6(s16)240 $vgpr0 = COPY %8(s32)241...242 243---244name: test_max_K0min_K1Val_f16245legalized: true246regBankSelected: true247tracksRegLiveness: true248machineFunctionInfo:249 mode:250 ieee: false251body: |252 bb.1:253 liveins: $vgpr0, $sgpr30_sgpr31254 255 ; CHECK-LABEL: name: test_max_K0min_K1Val_f16256 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31257 ; CHECK-NEXT: {{ $}}258 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0259 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)260 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400261 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)262 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000263 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)264 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]]265 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)266 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)267 %2:vgpr(s32) = COPY $vgpr0268 %0:vgpr(s16) = G_TRUNC %2(s32)269 %3:sgpr(s16) = G_FCONSTANT half 0xH4400270 %9:vgpr(s16) = COPY %3(s16)271 %4:vgpr(s16) = nnan G_FMINNUM %9, %0272 %5:sgpr(s16) = G_FCONSTANT half 0xH4000273 %10:vgpr(s16) = COPY %5(s16)274 %6:vgpr(s16) = nnan G_FMAXNUM %10, %4275 %8:vgpr(s32) = G_ANYEXT %6(s16)276 $vgpr0 = COPY %8(s32)277...278 279# FixMe: add tests with attributes #2 = {"no-nans-fp-math"="true"}280 281---282name: test_min_max_K0_gt_K1283legalized: true284regBankSelected: true285tracksRegLiveness: true286machineFunctionInfo:287 mode:288 ieee: true289body: |290 bb.1:291 liveins: $vgpr0292 293 ; CHECK-LABEL: name: test_min_max_K0_gt_K1294 ; CHECK: liveins: $vgpr0295 ; CHECK-NEXT: {{ $}}296 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0297 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00298 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)299 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]300 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00301 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)302 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]303 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)304 %0:vgpr(s32) = COPY $vgpr0305 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00306 %7:vgpr(s32) = COPY %2(s32)307 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7308 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00309 %8:vgpr(s32) = COPY %4(s32)310 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8311 $vgpr0 = COPY %5(s32)312...313 314---315name: test_max_min_K0_gt_K1316legalized: true317regBankSelected: true318tracksRegLiveness: true319machineFunctionInfo:320 mode:321 ieee: true322body: |323 bb.1:324 liveins: $vgpr0325 326 ; CHECK-LABEL: name: test_max_min_K0_gt_K1327 ; CHECK: liveins: $vgpr0328 ; CHECK-NEXT: {{ $}}329 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0330 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00331 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)332 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]333 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00334 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)335 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]336 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)337 %0:vgpr(s32) = COPY $vgpr0338 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00339 %7:vgpr(s32) = COPY %2(s32)340 %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7341 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00342 %8:vgpr(s32) = COPY %4(s32)343 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8344 $vgpr0 = COPY %5(s32)345...346 347---348name: test_min_max_non_inline_const349legalized: true350regBankSelected: true351tracksRegLiveness: true352machineFunctionInfo:353 mode:354 ieee: true355body: |356 bb.1:357 liveins: $vgpr0358 359 ; CHECK-LABEL: name: test_min_max_non_inline_const360 ; CHECK: liveins: $vgpr0361 ; CHECK-NEXT: {{ $}}362 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0363 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00364 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)365 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]366 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 8.000000e+00367 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)368 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]369 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)370 %0:vgpr(s32) = COPY $vgpr0371 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00372 %7:vgpr(s32) = COPY %2(s32)373 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7374 %4:sgpr(s32) = G_FCONSTANT float 8.000000e+00375 %8:vgpr(s32) = COPY %4(s32)376 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8377 $vgpr0 = COPY %5(s32)378...379 380---381name: test_min_max_f64382legalized: true383regBankSelected: true384tracksRegLiveness: true385machineFunctionInfo:386 mode:387 ieee: true388body: |389 bb.1:390 liveins: $vgpr0_vgpr1391 392 ; CHECK-LABEL: name: test_min_max_f64393 ; CHECK: liveins: $vgpr0_vgpr1394 ; CHECK-NEXT: {{ $}}395 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1396 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00397 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)398 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]399 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 4.000000e+00400 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[C1]](s64)401 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]402 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64)403 %0:vgpr(s64) = COPY $vgpr0_vgpr1404 %4:sgpr(s64) = G_FCONSTANT double 2.000000e+00405 %11:vgpr(s64) = COPY %4(s64)406 %5:vgpr(s64) = nnan G_FMAXNUM_IEEE %0, %11407 %6:sgpr(s64) = G_FCONSTANT double 4.000000e+00408 %12:vgpr(s64) = COPY %6(s64)409 %7:vgpr(s64) = nnan G_FMINNUM_IEEE %5, %12410 $vgpr0_vgpr1 = COPY %7(s64)411...412 413---414name: test_min_max_v2f16415legalized: true416regBankSelected: true417tracksRegLiveness: true418machineFunctionInfo:419 mode:420 ieee: true421body: |422 bb.1:423 liveins: $vgpr0424 425 ; CHECK-LABEL: name: test_min_max_v2f16426 ; CHECK: liveins: $vgpr0427 ; CHECK-NEXT: {{ $}}428 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0429 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000430 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)431 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)432 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400433 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C1]](s16)434 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT1]](s32), [[ANYEXT1]](s32)435 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)436 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]437 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)438 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]439 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x s16>)440 %0:vgpr(<2 x s16>) = COPY $vgpr0441 %3:sgpr(s16) = G_FCONSTANT half 0xH4000442 %9:sgpr(s32) = G_ANYEXT %3(s16)443 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32)444 %6:sgpr(s16) = G_FCONSTANT half 0xH4400445 %10:sgpr(s32) = G_ANYEXT %6(s16)446 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32)447 %11:vgpr(<2 x s16>) = COPY %2(<2 x s16>)448 %4:vgpr(<2 x s16>) = nnan G_FMAXNUM_IEEE %0, %11449 %12:vgpr(<2 x s16>) = COPY %5(<2 x s16>)450 %7:vgpr(<2 x s16>) = nnan G_FMINNUM_IEEE %4, %12451 $vgpr0 = COPY %7(<2 x s16>)452...453 454---455name: test_min_max_maybe_NaN_input_ieee_false456legalized: true457regBankSelected: true458tracksRegLiveness: true459machineFunctionInfo:460 mode:461 ieee: false462body: |463 bb.1:464 liveins: $vgpr0465 466 ; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_false467 ; CHECK: liveins: $vgpr0468 ; CHECK-NEXT: {{ $}}469 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0470 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00471 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)472 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[COPY]], [[COPY1]]473 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00474 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)475 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY2]]476 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)477 %0:vgpr(s32) = COPY $vgpr0478 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00479 %7:vgpr(s32) = COPY %2(s32)480 %3:vgpr(s32) = G_FMAXNUM %0, %7481 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00482 %8:vgpr(s32) = COPY %4(s32)483 %5:vgpr(s32) = G_FMINNUM %3, %8484 $vgpr0 = COPY %5(s32)485...486 487---488name: test_max_min_maybe_NaN_input_ieee_false489legalized: true490regBankSelected: true491tracksRegLiveness: true492machineFunctionInfo:493 mode:494 ieee: false495body: |496 bb.1:497 liveins: $vgpr0498 499 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_false500 ; CHECK: liveins: $vgpr0501 ; CHECK-NEXT: {{ $}}502 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0503 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00504 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)505 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[COPY]], [[COPY1]]506 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00507 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)508 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY2]]509 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)510 %0:vgpr(s32) = COPY $vgpr0511 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00512 %7:vgpr(s32) = COPY %2(s32)513 %3:vgpr(s32) = G_FMINNUM %0, %7514 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00515 %8:vgpr(s32) = COPY %4(s32)516 %5:vgpr(s32) = G_FMAXNUM %3, %8517 $vgpr0 = COPY %5(s32)518...519 520---521name: test_max_min_maybe_NaN_input_ieee_true522legalized: true523regBankSelected: true524tracksRegLiveness: true525machineFunctionInfo:526 mode:527 ieee: true528body: |529 bb.1:530 liveins: $vgpr0531 532 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_true533 ; CHECK: liveins: $vgpr0534 ; CHECK-NEXT: {{ $}}535 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0536 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00537 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]538 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)539 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]540 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00541 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)542 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]543 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)544 %0:vgpr(s32) = COPY $vgpr0545 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00546 %7:vgpr(s32) = G_FCANONICALIZE %0547 %8:vgpr(s32) = COPY %2(s32)548 %3:vgpr(s32) = G_FMINNUM_IEEE %7, %8549 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00550 %9:vgpr(s32) = COPY %4(s32)551 %5:vgpr(s32) = G_FMAXNUM_IEEE %3, %9552 $vgpr0 = COPY %5(s32)553...554