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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s3 4# COM: Check that the pass doesn't crash.5 6---7name: test_inline_asm8legalized: true9regBankSelected: true10tracksRegLiveness: true11machineFunctionInfo:12 mode:13 ieee: true14 dx10-clamp: true15body: |16 bb.1 :17 liveins: $vgpr018 19 ; CHECK-LABEL: name: test_inline_asm20 ; CHECK: liveins: $vgpr021 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr023 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+0024 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)25 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]26 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+0027 ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %5(s32)28 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)29 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], %5, [[COPY2]]30 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)31 %0:vgpr(s32) = COPY $vgpr032 %1:sgpr(s32) = G_FCONSTANT float 2.000000e+0033 %2:vgpr(s32) = COPY %1(s32)34 %3:vgpr(s32) = G_FMUL %0, %235 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+0036 INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %5:vgpr_3237 %6:vgpr(s32) = COPY %4(s32)38 %7:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %5(s32), %6(s32)39 $vgpr0 = COPY %7(s32)40...41 42---43name: test_unmerge_values44legalized: true45regBankSelected: true46tracksRegLiveness: true47machineFunctionInfo:48 mode:49 ieee: true50 dx10-clamp: true51body: |52 bb.1 :53 liveins: $vgpr054 55 ; CHECK-LABEL: name: test_unmerge_values56 ; CHECK: liveins: $vgpr057 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr059 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+0060 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)61 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]62 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+0063 ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 064 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)65 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], [[C2]], [[COPY2]]66 ; CHECK-NEXT: $vgpr0 = COPY [[C2]](s32)67 %0:vgpr(s32) = COPY $vgpr068 %1:sgpr(s32) = G_FCONSTANT float 2.000000e+0069 %2:vgpr(s32) = COPY %1(s32)70 %3:vgpr(s32) = G_FMUL %0, %271 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+0072 %5:vgpr(s64) = G_CONSTANT i64 12345678973 %6:vgpr(s32), %7:vgpr(s32) = G_UNMERGE_VALUES %5(s64)74 %8:vgpr(s32) = COPY %4(s32)75 %9:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %7(s32), %8(s32)76 $vgpr0 = COPY %7(s32)77...78