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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: test_min_max_ValK0_K1_i327legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.1:12 liveins: $vgpr013 14 ; CHECK-LABEL: name: test_min_max_ValK0_K1_i3215 ; CHECK: liveins: $vgpr016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr018 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1219 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)20 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1721 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)22 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY1]], [[COPY2]]23 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)24 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr025 %0:vgpr(s32) = COPY $vgpr026 %2:sgpr(s32) = G_CONSTANT i32 -1227 %7:vgpr(s32) = COPY %2(s32)28 %3:vgpr(s32) = G_SMAX %0, %729 %4:sgpr(s32) = G_CONSTANT i32 1730 %8:vgpr(s32) = COPY %4(s32)31 %5:vgpr(s32) = G_SMIN %3, %832 $vgpr0 = COPY %5(s32)33 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr034...35 36---37name: min_max_ValK0_K1_i3238legalized: true39regBankSelected: true40tracksRegLiveness: true41body: |42 bb.1:43 liveins: $vgpr044 45 ; CHECK-LABEL: name: min_max_ValK0_K1_i3246 ; CHECK: liveins: $vgpr047 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr049 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1250 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)51 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1752 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)53 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY1]], [[COPY2]]54 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)55 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr056 %0:vgpr(s32) = COPY $vgpr057 %2:sgpr(s32) = G_CONSTANT i32 -1258 %7:vgpr(s32) = COPY %2(s32)59 %3:vgpr(s32) = G_SMAX %7, %060 %4:sgpr(s32) = G_CONSTANT i32 1761 %8:vgpr(s32) = COPY %4(s32)62 %5:vgpr(s32) = G_SMIN %3, %863 $vgpr0 = COPY %5(s32)64 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr065...66 67---68name: test_min_K1max_ValK0__i3269legalized: true70regBankSelected: true71tracksRegLiveness: true72body: |73 bb.1:74 liveins: $vgpr075 76 ; CHECK-LABEL: name: test_min_K1max_ValK0__i3277 ; CHECK: liveins: $vgpr078 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr080 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1281 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)82 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1783 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)84 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY1]], [[COPY2]]85 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)86 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr087 %0:vgpr(s32) = COPY $vgpr088 %2:sgpr(s32) = G_CONSTANT i32 -1289 %7:vgpr(s32) = COPY %2(s32)90 %3:vgpr(s32) = G_SMAX %0, %791 %4:sgpr(s32) = G_CONSTANT i32 1792 %8:vgpr(s32) = COPY %4(s32)93 %5:vgpr(s32) = G_SMIN %8, %394 $vgpr0 = COPY %5(s32)95 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr096...97 98---99name: test_min_K1max_K0Val__i32100legalized: true101regBankSelected: true102tracksRegLiveness: true103body: |104 bb.1:105 liveins: $vgpr0106 107 ; CHECK-LABEL: name: test_min_K1max_K0Val__i32108 ; CHECK: liveins: $vgpr0109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0111 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12112 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)113 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17114 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)115 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY1]], [[COPY2]]116 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)117 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0118 %0:vgpr(s32) = COPY $vgpr0119 %2:sgpr(s32) = G_CONSTANT i32 -12120 %7:vgpr(s32) = COPY %2(s32)121 %3:vgpr(s32) = G_SMAX %7, %0122 %4:sgpr(s32) = G_CONSTANT i32 17123 %8:vgpr(s32) = COPY %4(s32)124 %5:vgpr(s32) = G_SMIN %8, %3125 $vgpr0 = COPY %5(s32)126 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0127...128 129---130name: test_max_min_ValK1_K0_i32131legalized: true132regBankSelected: true133tracksRegLiveness: true134body: |135 bb.1:136 liveins: $vgpr0137 138 ; CHECK-LABEL: name: test_max_min_ValK1_K0_i32139 ; CHECK: liveins: $vgpr0140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0142 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17143 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)144 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12145 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)146 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY1]]147 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)148 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0149 %0:vgpr(s32) = COPY $vgpr0150 %2:sgpr(s32) = G_CONSTANT i32 17151 %7:vgpr(s32) = COPY %2(s32)152 %3:vgpr(s32) = G_SMIN %0, %7153 %4:sgpr(s32) = G_CONSTANT i32 -12154 %8:vgpr(s32) = COPY %4(s32)155 %5:vgpr(s32) = G_SMAX %3, %8156 $vgpr0 = COPY %5(s32)157 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0158...159 160---161name: test_max_min_K1Val_K0_i32162legalized: true163regBankSelected: true164tracksRegLiveness: true165body: |166 bb.1:167 liveins: $vgpr0168 169 ; CHECK-LABEL: name: test_max_min_K1Val_K0_i32170 ; CHECK: liveins: $vgpr0171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0173 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17174 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)175 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12176 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)177 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY1]]178 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)179 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0180 %0:vgpr(s32) = COPY $vgpr0181 %2:sgpr(s32) = G_CONSTANT i32 17182 %7:vgpr(s32) = COPY %2(s32)183 %3:vgpr(s32) = G_SMIN %7, %0184 %4:sgpr(s32) = G_CONSTANT i32 -12185 %8:vgpr(s32) = COPY %4(s32)186 %5:vgpr(s32) = G_SMAX %3, %8187 $vgpr0 = COPY %5(s32)188 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0189...190 191---192name: test_max_K0min_ValK1__i32193legalized: true194regBankSelected: true195tracksRegLiveness: true196body: |197 bb.1:198 liveins: $vgpr0199 200 ; CHECK-LABEL: name: test_max_K0min_ValK1__i32201 ; CHECK: liveins: $vgpr0202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0204 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17205 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)206 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12207 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)208 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY1]]209 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)210 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0211 %0:vgpr(s32) = COPY $vgpr0212 %2:sgpr(s32) = G_CONSTANT i32 17213 %7:vgpr(s32) = COPY %2(s32)214 %3:vgpr(s32) = G_SMIN %0, %7215 %4:sgpr(s32) = G_CONSTANT i32 -12216 %8:vgpr(s32) = COPY %4(s32)217 %5:vgpr(s32) = G_SMAX %8, %3218 $vgpr0 = COPY %5(s32)219 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0220...221 222---223name: test_max_K0min_K1Val__i32224legalized: true225regBankSelected: true226tracksRegLiveness: true227body: |228 bb.1:229 liveins: $vgpr0230 231 ; CHECK-LABEL: name: test_max_K0min_K1Val__i32232 ; CHECK: liveins: $vgpr0233 ; CHECK-NEXT: {{ $}}234 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0235 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17236 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)237 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12238 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)239 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY2]], [[COPY1]]240 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)241 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0242 %0:vgpr(s32) = COPY $vgpr0243 %2:sgpr(s32) = G_CONSTANT i32 17244 %7:vgpr(s32) = COPY %2(s32)245 %3:vgpr(s32) = G_SMIN %7, %0246 %4:sgpr(s32) = G_CONSTANT i32 -12247 %8:vgpr(s32) = COPY %4(s32)248 %5:vgpr(s32) = G_SMAX %8, %3249 $vgpr0 = COPY %5(s32)250 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0251...252 253---254name: test_max_K0min_K1Val__v2i16255legalized: true256regBankSelected: true257tracksRegLiveness: true258body: |259 bb.1:260 liveins: $vgpr0261 262 ; CHECK-LABEL: name: test_max_K0min_K1Val__v2i16263 ; CHECK: liveins: $vgpr0264 ; CHECK-NEXT: {{ $}}265 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0266 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17267 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)268 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12269 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)270 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)271 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_SMIN [[COPY1]], [[COPY]]272 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)273 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_SMAX [[COPY2]], [[SMIN]]274 ; CHECK-NEXT: $vgpr0 = COPY [[SMAX]](<2 x s16>)275 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0276 %0:vgpr(<2 x s16>) = COPY $vgpr0277 %9:sgpr(s32) = G_CONSTANT i32 17278 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32)279 %10:sgpr(s32) = G_CONSTANT i32 -12280 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32)281 %11:vgpr(<2 x s16>) = COPY %2(<2 x s16>)282 %4:vgpr(<2 x s16>) = G_SMIN %11, %0283 %12:vgpr(<2 x s16>) = COPY %5(<2 x s16>)284 %7:vgpr(<2 x s16>) = G_SMAX %12, %4285 $vgpr0 = COPY %7(<2 x s16>)286 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0287...288 289---290name: test_uniform_min_max291legalized: true292regBankSelected: true293tracksRegLiveness: true294body: |295 bb.1:296 liveins: $sgpr2297 298 ; CHECK-LABEL: name: test_uniform_min_max299 ; CHECK: liveins: $sgpr2300 ; CHECK-NEXT: {{ $}}301 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2302 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12303 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[C]]304 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17305 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SMAX]], [[C1]]306 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[SMIN]](s32)307 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)308 ; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32)309 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0310 %0:sgpr(s32) = COPY $sgpr2311 %3:sgpr(s32) = G_CONSTANT i32 -12312 %4:sgpr(s32) = G_SMAX %0, %3313 %5:sgpr(s32) = G_CONSTANT i32 17314 %6:sgpr(s32) = G_SMIN %4, %5315 %8:vgpr(s32) = COPY %6(s32)316 %7:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %8(s32)317 $sgpr0 = COPY %7(s32)318 SI_RETURN_TO_EPILOG implicit $sgpr0319...320 321---322name: test_non_inline_constant_i32323legalized: true324regBankSelected: true325tracksRegLiveness: true326body: |327 bb.1:328 liveins: $vgpr0329 330 ; CHECK-LABEL: name: test_non_inline_constant_i32331 ; CHECK: liveins: $vgpr0332 ; CHECK-NEXT: {{ $}}333 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0334 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12335 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)336 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65337 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)338 ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY1]], [[COPY2]]339 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)340 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0341 %0:vgpr(s32) = COPY $vgpr0342 %2:sgpr(s32) = G_CONSTANT i32 -12343 %7:vgpr(s32) = COPY %2(s32)344 %3:vgpr(s32) = G_SMAX %0, %7345 %4:sgpr(s32) = G_CONSTANT i32 65346 %8:vgpr(s32) = COPY %4(s32)347 %5:vgpr(s32) = G_SMIN %3, %8348 $vgpr0 = COPY %5(s32)349 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0350...351