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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s3 4---5name: add_v2s16_ss6legalized: true7 8body: |9 bb.0:10 liveins: $sgpr0, $sgpr111 ; CHECK-LABEL: name: add_v2s16_ss12 ; CHECK: liveins: $sgpr0, $sgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr116 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)17 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1618 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)19 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)20 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C]](s32)21 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[BITCAST]], [[BITCAST1]]22 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s32) = G_ADD [[LSHR]], [[LSHR1]]23 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ADD]](s32), [[ADD1]](s32)24 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_CONSTANT i16 25525 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16)26 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(<2 x s16>) = G_AND [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR]]27 %0:_(<2 x s16>) = COPY $sgpr028 %1:_(<2 x s16>) = COPY $sgpr129 %2:_(<2 x s16>) = G_ADD %0, %130 %3:_(s16) = G_CONSTANT i16 25531 %4:_(<2 x s16>) = G_BUILD_VECTOR %3, %332 %5:_(<2 x s16>) = G_AND %2, %433...34 35---36name: add_v2s16_sv37legalized: true38 39body: |40 bb.0:41 liveins: $sgpr0, $vgpr042 ; CHECK-LABEL: name: add_v2s16_sv43 ; CHECK: liveins: $sgpr0, $vgpr044 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr046 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr047 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)48 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY2]], [[COPY1]]49 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(<2 x s16>) = G_AND [[ADD]], [[ADD]]50 %0:_(<2 x s16>) = COPY $sgpr051 %1:_(<2 x s16>) = COPY $vgpr052 %2:_(<2 x s16>) = G_ADD %0, %153 %3:_(<2 x s16>) = G_AND %2, %254...55 56---57name: add_v2s16_vs58legalized: true59 60body: |61 bb.0:62 liveins: $sgpr0, $vgpr063 ; CHECK-LABEL: name: add_v2s16_vs64 ; CHECK: liveins: $sgpr0, $vgpr065 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr067 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr068 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)69 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY2]]70 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(<2 x s16>) = G_AND [[ADD]], [[ADD]]71 %0:_(<2 x s16>) = COPY $vgpr072 %1:_(<2 x s16>) = COPY $sgpr073 %2:_(<2 x s16>) = G_ADD %0, %174 %3:_(<2 x s16>) = G_AND %2, %275...76 77---78name: add_v2s16_vv79legalized: true80 81body: |82 bb.0:83 liveins: $vgpr0, $vgpr184 ; CHECK-LABEL: name: add_v2s16_vv85 ; CHECK: liveins: $vgpr0, $vgpr186 ; CHECK-NEXT: {{ $}}87 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr088 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr189 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY1]]90 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(<2 x s16>) = G_AND [[ADD]], [[ADD]]91 %0:_(<2 x s16>) = COPY $vgpr092 %1:_(<2 x s16>) = COPY $vgpr193 %2:_(<2 x s16>) = G_ADD %0, %194 %3:_(<2 x s16>) = G_AND %2, %295...96