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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s4 5---6name: exp_compr_v2f16_s7legalized: true8 9body: |10 bb.0:11 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr312 ; CHECK-LABEL: name: exp_compr_v2f16_s13 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr314 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr016 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr117 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)18 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)19 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), 0, 0, [[COPY2]](s32), [[COPY3]](s32), 0, 020 %0:_(s32) = COPY $sgpr021 %1:_(s32) = COPY $sgpr122 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), 0, 0, %0, %1, 0, 023...24---25name: exp_compr_v2f16_v26legalized: true27 28body: |29 bb.0:30 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr331 ; CHECK-LABEL: name: exp_compr_v2f16_v32 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr333 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr035 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr136 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), 0, 0, [[COPY]](s32), [[COPY1]](s32), 0, 037 %0:_(s32) = COPY $vgpr038 %1:_(s32) = COPY $vgpr139 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), 0, 0, %0, %1, 0, 040...41