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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s4 5---6name: div_fmas_sss_scc7legalized: true8 9body: |10 bb.0:11 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr312 ; CHECK-LABEL: name: div_fmas_sss_scc13 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr314 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr016 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr117 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr218 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr319 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 020 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]21 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)22 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)23 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)24 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)25 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)26 ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s1)27 %0:_(s32) = COPY $sgpr028 %1:_(s32) = COPY $sgpr129 %2:_(s32) = COPY $sgpr230 %3:_(s32) = COPY $sgpr331 %4:_(s32) = G_CONSTANT i32 032 %5:_(s1) = G_ICMP intpred(eq), %3, %433 %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %534...35 36---37name: div_fmas_sss_vcc38legalized: true39 40body: |41 bb.0:42 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr043 ; CHECK-LABEL: name: div_fmas_sss_vcc44 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr045 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr047 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr148 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr249 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr050 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 051 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)52 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]]53 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)54 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)55 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)56 ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[ICMP]](s1)57 %0:_(s32) = COPY $sgpr058 %1:_(s32) = COPY $sgpr159 %2:_(s32) = COPY $sgpr260 %3:_(s32) = COPY $vgpr061 %4:_(s32) = G_CONSTANT i32 062 %5:_(s1) = G_ICMP intpred(eq), %3, %463 %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %564...65 66---67name: div_fmas_vss_vcc68legalized: true69 70body: |71 bb.0:72 liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr173 ; CHECK-LABEL: name: div_fmas_vss_vcc74 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr175 ; CHECK-NEXT: {{ $}}76 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr077 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr078 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr179 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr180 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 081 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)82 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]]83 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)84 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)85 ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY5]](s32), [[COPY6]](s32), [[ICMP]](s1)86 %0:_(s32) = COPY $vgpr087 %1:_(s32) = COPY $sgpr088 %2:_(s32) = COPY $sgpr189 %3:_(s32) = COPY $vgpr190 %4:_(s32) = G_CONSTANT i32 091 %5:_(s1) = G_ICMP intpred(eq), %3, %492 %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %593...94 95---96name: div_fmas_vvv_vcc97legalized: true98 99body: |100 bb.0:101 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3102 ; CHECK-LABEL: name: div_fmas_vvv_vcc103 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0106 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1107 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2108 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3109 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0110 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)111 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]]112 ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[ICMP]](s1)113 %0:_(s32) = COPY $vgpr0114 %1:_(s32) = COPY $vgpr1115 %2:_(s32) = COPY $vgpr2116 %3:_(s32) = COPY $vgpr3117 %4:_(s32) = G_CONSTANT i32 0118 %5:_(s1) = G_ICMP intpred(eq), %3, %4119 %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5120...121