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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s4 5---6name: interp_p1_f16_ss7legalized: true8tracksRegLiveness: true9 10body: |11 bb.0:12 liveins: $sgpr0, $sgpr113 14 ; CHECK-LABEL: name: interp_p1_f16_ss15 ; CHECK: liveins: $sgpr0, $sgpr116 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr018 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr119 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)20 ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), [[COPY2]](s32), 1, 1, 1, [[COPY1]](s32)21 %0:_(s32) = COPY $sgpr022 %1:_(s32) = COPY $sgpr123 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), %0, 1, 1, 1, %124...25 26---27name: interp_p1_f16_sv28legalized: true29tracksRegLiveness: true30 31body: |32 bb.0:33 liveins: $sgpr0, $vgpr034 ; CHECK-LABEL: name: interp_p1_f16_sv35 ; CHECK: liveins: $sgpr0, $vgpr036 ; CHECK-NEXT: {{ $}}37 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr038 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr039 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)40 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec41 ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), [[COPY2]](s32), 1, 1, 1, [[V_READFIRSTLANE_B32_]](s32)42 %0:_(s32) = COPY $sgpr043 %1:_(s32) = COPY $vgpr044 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), %0, 1, 1, 1, %145...46