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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s4 5---6name: readlane_ss7legalized: true8 9body: |10 bb.0:11 liveins: $sgpr0, $sgpr112 ; CHECK-LABEL: name: readlane_ss13 ; CHECK: liveins: $sgpr0, $sgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr016 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr117 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)18 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)19 %0:_(s32) = COPY $sgpr020 %1:_(s32) = COPY $sgpr121 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %122...23 24---25name: readlane_vs26legalized: true27 28body: |29 bb.0:30 liveins: $vgpr0, $sgpr031 ; CHECK-LABEL: name: readlane_vs32 ; CHECK: liveins: $vgpr0, $sgpr033 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr035 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr036 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[COPY1]](s32)37 %0:_(s32) = COPY $vgpr038 %1:_(s32) = COPY $sgpr039 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %140...41 42---43name: readlane_vv44legalized: true45 46body: |47 bb.0:48 liveins: $vgpr0, $vgpr149 ; CHECK-LABEL: name: readlane_vv50 ; CHECK: liveins: $vgpr0, $vgpr151 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr053 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr154 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec55 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)56 %0:_(s32) = COPY $vgpr057 %1:_(s32) = COPY $vgpr158 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %159...60 61---62name: readlane_sv63legalized: true64 65body: |66 bb.0:67 liveins: $vgpr0, $sgpr068 ; CHECK-LABEL: name: readlane_sv69 ; CHECK: liveins: $vgpr0, $sgpr070 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr072 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr073 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)74 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec75 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)76 %0:_(s32) = COPY $sgpr077 %1:_(s32) = COPY $vgpr078 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %179...80 81---82name: readlane_aa83legalized: true84 85body: |86 bb.0:87 liveins: $agpr0, $agpr188 ; CHECK-LABEL: name: readlane_aa89 ; CHECK: liveins: $agpr0, $agpr190 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr092 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr193 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)94 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)95 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec96 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)97 ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s32)98 %0:_(s32) = COPY $agpr099 %1:_(s32) = COPY $agpr1100 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %1101 S_ENDPGM 0, implicit %2102...103 104---105name: readlane_as106legalized: true107 108body: |109 bb.0:110 liveins: $agpr0, $sgpr0111 ; CHECK-LABEL: name: readlane_as112 ; CHECK: liveins: $agpr0, $sgpr0113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0115 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0116 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)117 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)118 %0:_(s32) = COPY $agpr0119 %1:_(s32) = COPY $sgpr0120 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %1121...122 123---124name: readlane_sa125legalized: true126 127body: |128 bb.0:129 liveins: $agpr0, $sgpr0130 ; CHECK-LABEL: name: readlane_sa131 ; CHECK: liveins: $agpr0, $sgpr0132 ; CHECK-NEXT: {{ $}}133 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0134 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0135 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)136 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)137 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec138 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)139 %0:_(s32) = COPY $sgpr0140 %1:_(s32) = COPY $agpr0141 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %1142...143 144---145name: readlane_va146legalized: true147 148body: |149 bb.0:150 liveins: $vgpr0, $agpr0151 ; CHECK-LABEL: name: readlane_va152 ; CHECK: liveins: $vgpr0, $agpr0153 ; CHECK-NEXT: {{ $}}154 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0155 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0156 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)157 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY2]](s32), implicit $exec158 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)159 %0:_(s32) = COPY $vgpr0160 %1:_(s32) = COPY $agpr0161 %2:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readlane), %0, %1162...163