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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -regbankselect-greedy -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -regbankselect-fast -o - %s | FileCheck %s4 5# TODO: We could use scalar6---7name: amdgpu_wave_address8legalized: true9body: |10 bb.0:11 ; CHECK-LABEL: name: amdgpu_wave_address12 ; CHECK: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:sgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr3213 ; CHECK-NEXT: S_ENDPGM 0, implicit [[AMDGPU_WAVE_ADDRESS]](p5)14 %0:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr3215 S_ENDPGM 0, implicit %016...17 18# TODO: Should infer v here19---20name: amdgpu_wave_address_v21legalized: true22body: |23 bb.0:24 ; CHECK-LABEL: name: amdgpu_wave_address_v25 ; CHECK: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF26 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:sgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr3227 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p5) = COPY [[AMDGPU_WAVE_ADDRESS]](p5)28 ; CHECK-NEXT: G_STORE [[COPY]](p5), [[DEF]](p1) :: (store (p5), addrspace 1)29 %0:_(p1) = G_IMPLICIT_DEF30 %1:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr3231 G_STORE %1, %0 :: (store (p5), addrspace 1)32...33