328 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s3 4---5name: and_s1_sgpr_sgpr6legalized: true7 8body: |9 bb.0:10 liveins: $sgpr0, $sgpr111 ; CHECK-LABEL: name: and_s1_sgpr_sgpr12 ; CHECK: liveins: $sgpr0, $sgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr116 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]17 ; CHECK-NEXT: S_ENDPGM 0, implicit [[AND]](s32)18 %0:_(s32) = COPY $sgpr019 %1:_(s32) = COPY $sgpr120 %2:_(s1) = G_TRUNC %021 %3:_(s1) = G_TRUNC %122 %4:_(s1) = G_AND %2, %323 %5:_(s32) = G_ANYEXT %424 S_ENDPGM 0, implicit %525...26 27---28name: and_s1_scc_scc29legalized: true30 31body: |32 bb.0:33 liveins: $sgpr0, $sgpr134 ; CHECK-LABEL: name: and_s1_scc_scc35 ; CHECK: liveins: $sgpr0, $sgpr136 ; CHECK-NEXT: {{ $}}37 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr038 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr139 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 040 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]41 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]42 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[ICMP1]]43 ; CHECK-NEXT: S_ENDPGM 0, implicit [[AND]](s32)44 %0:_(s32) = COPY $sgpr045 %1:_(s32) = COPY $sgpr146 %2:_(s32) = G_CONSTANT i32 047 %3:_(s1) = G_ICMP intpred(eq), %0, %248 %4:_(s1) = G_ICMP intpred(eq), %1, %249 %5:_(s1) = G_AND %3, %450 %6:_(s32) = G_ANYEXT %551 S_ENDPGM 0, implicit %652...53 54---55name: and_s1_vgpr_vgpr56legalized: true57 58body: |59 bb.0:60 liveins: $vgpr0, $vgpr161 ; CHECK-LABEL: name: and_s1_vgpr_vgpr62 ; CHECK: liveins: $vgpr0, $vgpr163 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr065 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr166 ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 167 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]68 ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 069 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]70 ; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[COPY1]], [[C]]71 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND1]](s32), [[C1]]72 ; CHECK-NEXT: [[AND2:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]73 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AND2]](s1), [[C]], [[C1]]74 %0:_(s32) = COPY $vgpr075 %1:_(s32) = COPY $vgpr176 %2:_(s1) = G_TRUNC %077 %3:_(s1) = G_TRUNC %178 %4:_(s1) = G_AND %2, %379 %5:_(s32) = G_ANYEXT %480...81 82---83name: and_s1_vcc_vcc84legalized: true85 86body: |87 bb.0:88 liveins: $vgpr0, $vgpr189 ; CHECK-LABEL: name: and_s1_vcc_vcc90 ; CHECK: liveins: $vgpr0, $vgpr191 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr093 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr194 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 095 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)96 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]97 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)98 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]99 ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]100 %0:_(s32) = COPY $vgpr0101 %1:_(s32) = COPY $vgpr1102 %2:_(s32) = G_CONSTANT i32 0103 %3:_(s1) = G_ICMP intpred(eq), %0, %2104 %4:_(s1) = G_ICMP intpred(eq), %1, %2105 %5:_(s1) = G_AND %3, %4106...107 108---109name: and_s1_sgpr_vgpr110legalized: true111 112body: |113 bb.0:114 liveins: $sgpr0, $vgpr0115 ; CHECK-LABEL: name: and_s1_sgpr_vgpr116 ; CHECK: liveins: $sgpr0, $vgpr0117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0119 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0120 ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1121 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY1]], [[C]]122 ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0123 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]124 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY]](s32)125 ; CHECK-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AMDGPU_COPY_VCC_SCC]], [[ICMP]]126 %0:_(s32) = COPY $sgpr0127 %1:_(s32) = COPY $vgpr0128 %2:_(s1) = G_TRUNC %0129 %3:_(s1) = G_TRUNC %1130 %4:_(s1) = G_AND %2, %3131...132 133---134name: and_s1_vgpr_sgpr135legalized: true136 137body: |138 bb.0:139 liveins: $vgpr0, $vgpr0140 ; CHECK-LABEL: name: and_s1_vgpr_sgpr141 ; CHECK: liveins: $vgpr0, $vgpr0142 ; CHECK-NEXT: {{ $}}143 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0144 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0145 ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1146 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]147 ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0148 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]149 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY1]](s32)150 ; CHECK-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[AMDGPU_COPY_VCC_SCC]]151 %0:_(s32) = COPY $vgpr0152 %1:_(s32) = COPY $sgpr0153 %2:_(s1) = G_TRUNC %0154 %3:_(s1) = G_TRUNC %1155 %4:_(s1) = G_AND %2, %3156...157 158# FIXME: Should just change the result bank of the scc compare.159---160name: and_s1_scc_vcc161legalized: true162 163body: |164 bb.0:165 liveins: $sgpr0, $vgpr0166 ; CHECK-LABEL: name: and_s1_scc_vcc167 ; CHECK: liveins: $sgpr0, $vgpr0168 ; CHECK-NEXT: {{ $}}169 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0170 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0171 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0172 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]173 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)174 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]]175 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)176 ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[AMDGPU_COPY_VCC_SCC]], [[ICMP1]]177 %0:_(s32) = COPY $sgpr0178 %1:_(s32) = COPY $vgpr0179 %2:_(s32) = G_CONSTANT i32 0180 %3:_(s1) = G_ICMP intpred(eq), %0, %2181 %4:_(s1) = G_ICMP intpred(eq), %1, %2182 %5:_(s1) = G_AND %3, %4183...184 185---186name: and_s1_vcc_scc187legalized: true188 189body: |190 bb.0:191 liveins: $vgpr0, $vgpr1192 ; CHECK-LABEL: name: and_s1_vcc_scc193 ; CHECK: liveins: $vgpr0, $vgpr1194 ; CHECK-NEXT: {{ $}}195 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0196 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1197 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0198 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)199 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]200 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)201 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]202 ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]203 %0:_(s32) = COPY $vgpr0204 %1:_(s32) = COPY $vgpr1205 %2:_(s32) = G_CONSTANT i32 0206 %3:_(s1) = G_ICMP intpred(eq), %0, %2207 %4:_(s1) = G_ICMP intpred(eq), %1, %2208 %5:_(s1) = G_AND %3, %4209...210 211 212# Test with a known result bank213# ---214# name: and_s1_vcc_sgpr_sgpr215# legalized: true216 217# body: |218# bb.0:219# liveins: $sgpr0, $sgpr1220 221# %0:_(s32) = COPY $sgpr0222# %1:_(s32) = COPY $sgpr1223# %2:_(s1) = G_TRUNC %0224# %3:_(s1) = G_TRUNC %1225# %4:vcc(s1) = G_AND %2, %3226# ...227 228# ---229# name: and_s1_vcc_vgpr_vgpr230# legalized: true231 232# body: |233# bb.0:234# liveins: $vgpr0, $vgpr1235 236# %0:_(s32) = COPY $vgpr0237# %1:_(s32) = COPY $vgpr1238# %2:_(s1) = G_TRUNC %0239# %3:_(s1) = G_TRUNC %1240# %4:vcc(s1) = G_AND %2, %3241# ...242 243# ---244# name: and_s1_vcc_vgpr_sgpr245# legalized: true246 247# body: |248# bb.0:249# liveins: $vgpr0, $sgpr0250# %0:_(s32) = COPY $vgpr0251# %1:_(s32) = COPY $sgpr0252# %2:_(s1) = G_TRUNC %0253# %3:_(s1) = G_TRUNC %1254# %4:vcc(s1) = G_AND %2, %3255# ...256 257# ---258# name: and_s1_vcc_sgpr_vgpr259# legalized: true260 261# body: |262# bb.0:263# liveins: $vgpr0, $sgpr0264# %0:_(s32) = COPY $sgpr0265# %1:_(s32) = COPY $vgpr0266# %2:_(s1) = G_TRUNC %0267# %3:_(s1) = G_TRUNC %1268# %4:vcc(s1) = G_AND %2, %3269# ...270 271---272name: and_s1_vgpr_sgpr_sgpr273legalized: true274 275body: |276 bb.0:277 liveins: $sgpr0, $sgpr1278 ; CHECK-LABEL: name: and_s1_vgpr_sgpr_sgpr279 ; CHECK: liveins: $sgpr0, $sgpr1280 ; CHECK-NEXT: {{ $}}281 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0282 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1283 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0284 ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1285 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY2]], [[C]]286 ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0287 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]288 ; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]289 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[AND1]](s32)290 ; CHECK-NEXT: [[AND2:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[AMDGPU_COPY_VCC_SCC]]291 %0:_(s32) = COPY $sgpr0292 %1:_(s32) = COPY $sgpr1293 %2:_(s32) = COPY $vgpr0294 %3:_(s1) = G_TRUNC %0295 %4:_(s1) = G_TRUNC %1296 %5:_(s1) = G_TRUNC %2297 %6:_(s1) = G_AND %3, %4298 %7:_(s1) = G_AND %5, %6299...300 301---302name: and_s1_sgpr_sgpr_sgpr303legalized: true304 305body: |306 bb.0:307 liveins: $sgpr0, $sgpr1308 ; CHECK-LABEL: name: and_s1_sgpr_sgpr_sgpr309 ; CHECK: liveins: $sgpr0, $sgpr1310 ; CHECK-NEXT: {{ $}}311 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0312 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1313 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0314 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]315 ; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[AND]]316 ; CHECK-NEXT: S_ENDPGM 0, implicit [[AND1]](s32)317 %0:_(s32) = COPY $sgpr0318 %1:_(s32) = COPY $sgpr1319 %2:_(s32) = COPY $sgpr0320 %3:_(s1) = G_TRUNC %0321 %4:_(s1) = G_TRUNC %1322 %5:_(s1) = G_TRUNC %2323 %6:_(s1) = G_AND %3, %4324 %7:_(s1) = G_AND %5, %6325 %8:_(s32) = G_ANYEXT %7326 S_ENDPGM 0, implicit %8327...328