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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s3 4---5name: build_vector_v2s32_ss6legalized: true7 8body: |9 bb.0:10 liveins: $sgpr0, $sgpr111 ; CHECK-LABEL: name: build_vector_v2s32_ss12 ; CHECK: liveins: $sgpr0, $sgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr116 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)17 %0:_(s32) = COPY $sgpr018 %1:_(s32) = COPY $sgpr119 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %120...21 22---23name: build_vector_v2s32_sv24legalized: true25 26body: |27 bb.0:28 liveins: $sgpr0, $vgpr029 ; CHECK-LABEL: name: build_vector_v2s32_sv30 ; CHECK: liveins: $sgpr0, $vgpr031 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr033 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr034 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)35 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)36 %0:_(s32) = COPY $sgpr037 %1:_(s32) = COPY $vgpr038 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %139...40 41---42name: build_vector_v2s32_vs43legalized: true44 45body: |46 bb.0:47 liveins: $vgpr0, $sgpr048 ; CHECK-LABEL: name: build_vector_v2s32_vs49 ; CHECK: liveins: $vgpr0, $sgpr050 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr053 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)54 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)55 %0:_(s32) = COPY $vgpr056 %1:_(s32) = COPY $sgpr057 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %158...59 60---61name: build_vector_v2s32_vv62legalized: true63 64body: |65 bb.0:66 liveins: $vgpr0, $vgpr167 ; CHECK-LABEL: name: build_vector_v2s32_vv68 ; CHECK: liveins: $vgpr0, $vgpr169 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr071 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr172 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)73 %0:_(s32) = COPY $vgpr074 %1:_(s32) = COPY $vgpr175 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %176...77 78---79name: build_vector_v2s32_aa80tracksRegLiveness: true81legalized: true82 83body: |84 bb.0:85 liveins: $agpr0, $agpr186 87 ; CHECK-LABEL: name: build_vector_v2s32_aa88 ; CHECK: liveins: $agpr0, $agpr189 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr091 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr192 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)93 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)94 %0:_(s32) = COPY $agpr095 %1:_(s32) = COPY $agpr196 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %197 S_ENDPGM 0, implicit %298...99 100---101name: build_vector_v2s32_va102tracksRegLiveness: true103legalized: true104 105body: |106 bb.0:107 liveins: $vgpr0, $agpr0108 109 ; CHECK-LABEL: name: build_vector_v2s32_va110 ; CHECK: liveins: $vgpr0, $agpr0111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0113 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr0114 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)115 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)116 %0:_(s32) = COPY $vgpr0117 %1:_(s32) = COPY $agpr0118 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1119 S_ENDPGM 0, implicit %2120...121 122---123name: build_vector_v2s32_av124tracksRegLiveness: true125legalized: true126 127body: |128 bb.0:129 liveins: $vgpr0, $agpr0130 131 ; CHECK-LABEL: name: build_vector_v2s32_av132 ; CHECK: liveins: $vgpr0, $agpr0133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0135 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0136 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)137 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)138 %0:_(s32) = COPY $agpr0139 %1:_(s32) = COPY $vgpr0140 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1141 S_ENDPGM 0, implicit %2142...143 144---145name: build_vector_v2s32_sa146tracksRegLiveness: true147legalized: true148 149body: |150 bb.0:151 liveins: $sgpr0, $agpr0152 153 ; CHECK-LABEL: name: build_vector_v2s32_sa154 ; CHECK: liveins: $sgpr0, $agpr0155 ; CHECK-NEXT: {{ $}}156 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0157 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr0158 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)159 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)160 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)161 %0:_(s32) = COPY $sgpr0162 %1:_(s32) = COPY $agpr0163 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1164 S_ENDPGM 0, implicit %2165...166 167---168name: build_vector_v2s32_as169tracksRegLiveness: true170legalized: true171 172body: |173 bb.0:174 liveins: $sgpr0, $agpr0175 176 ; CHECK-LABEL: name: build_vector_v2s32_as177 ; CHECK: liveins: $sgpr0, $agpr0178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0180 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0181 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)182 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)183 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)184 %0:_(s32) = COPY $agpr0185 %1:_(s32) = COPY $sgpr0186 %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1187 S_ENDPGM 0, implicit %2188...189 190---191name: build_vector_v3s32_aaa192tracksRegLiveness: true193legalized: true194 195body: |196 bb.0:197 liveins: $agpr0, $agpr1, $agpr2198 199 ; CHECK-LABEL: name: build_vector_v3s32_aaa200 ; CHECK: liveins: $agpr0, $agpr1, $agpr2201 ; CHECK-NEXT: {{ $}}202 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0203 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr1204 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $agpr2205 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)206 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>)207 %0:_(s32) = COPY $agpr0208 %1:_(s32) = COPY $agpr1209 %2:_(s32) = COPY $agpr2210 %3:_(<3 x s32>) = G_BUILD_VECTOR %0, %1, %2211 S_ENDPGM 0, implicit %3212...213 214---215name: build_vector_v4s32_aaaa216tracksRegLiveness: true217legalized: true218 219body: |220 bb.0:221 liveins: $agpr0, $agpr1, $agpr2222 223 ; CHECK-LABEL: name: build_vector_v4s32_aaaa224 ; CHECK: liveins: $agpr0, $agpr1, $agpr2225 ; CHECK-NEXT: {{ $}}226 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0227 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr1228 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $agpr2229 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $agpr2230 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)231 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>)232 %0:_(s32) = COPY $agpr0233 %1:_(s32) = COPY $agpr1234 %2:_(s32) = COPY $agpr2235 %3:_(s32) = COPY $agpr2236 %4:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3237 S_ENDPGM 0, implicit %4238...239 240---241name: build_vector_v8s32_aaaaaaaa242tracksRegLiveness: true243legalized: true244 245body: |246 bb.0:247 liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7248 249 ; CHECK-LABEL: name: build_vector_v8s32_aaaaaaaa250 ; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7251 ; CHECK-NEXT: {{ $}}252 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0253 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr1254 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $agpr2255 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $agpr3256 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $agpr4257 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $agpr5258 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $agpr6259 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $agpr7260 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)261 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>)262 %0:_(s32) = COPY $agpr0263 %1:_(s32) = COPY $agpr1264 %2:_(s32) = COPY $agpr2265 %3:_(s32) = COPY $agpr3266 %4:_(s32) = COPY $agpr4267 %5:_(s32) = COPY $agpr5268 %6:_(s32) = COPY $agpr6269 %7:_(s32) = COPY $agpr7270 %8:_(<8 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7271 S_ENDPGM 0, implicit %8272...273 274---275name: build_vector_v16s32_aaaaaaaaaaaaaaaa276tracksRegLiveness: true277legalized: true278 279body: |280 bb.0:281 liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15282 283 ; CHECK-LABEL: name: build_vector_v16s32_aaaaaaaaaaaaaaaa284 ; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15285 ; CHECK-NEXT: {{ $}}286 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $agpr0287 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $agpr1288 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $agpr2289 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $agpr3290 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $agpr4291 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $agpr5292 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $agpr6293 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY $agpr7294 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $agpr8295 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY $agpr9296 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr(s32) = COPY $agpr10297 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr(s32) = COPY $agpr11298 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr(s32) = COPY $agpr12299 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr(s32) = COPY $agpr13300 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vgpr(s32) = COPY $agpr14301 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vgpr(s32) = COPY $agpr15302 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)303 ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<16 x s32>)304 %0:_(s32) = COPY $agpr0305 %1:_(s32) = COPY $agpr1306 %2:_(s32) = COPY $agpr2307 %3:_(s32) = COPY $agpr3308 %4:_(s32) = COPY $agpr4309 %5:_(s32) = COPY $agpr5310 %6:_(s32) = COPY $agpr6311 %7:_(s32) = COPY $agpr7312 %8:_(s32) = COPY $agpr8313 %9:_(s32) = COPY $agpr9314 %10:_(s32) = COPY $agpr10315 %11:_(s32) = COPY $agpr11316 %12:_(s32) = COPY $agpr12317 %13:_(s32) = COPY $agpr13318 %14:_(s32) = COPY $agpr14319 %15:_(s32) = COPY $agpr15320 %16:_(<16 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15321 S_ENDPGM 0, implicit %16322...323